CN103439646A - Method for generating testing vectors of artificial circuit - Google Patents

Method for generating testing vectors of artificial circuit Download PDF

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CN103439646A
CN103439646A CN2013103814666A CN201310381466A CN103439646A CN 103439646 A CN103439646 A CN 103439646A CN 2013103814666 A CN2013103814666 A CN 2013103814666A CN 201310381466 A CN201310381466 A CN 201310381466A CN 103439646 A CN103439646 A CN 103439646A
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王承
何进
杜彩霞
朱小安
何清兴
钟胜菊
梅金河
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SHENZHEN HUAYUE TIANXIN ELECTRONIC Co Ltd
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Abstract

The invention relates to a method for generating testing vectors of an artificial circuit. The method for generating the testing vectors of the artificial circuit comprises the steps of carrying out testability analysis on the circuit to be tested, namely the optimum testing node set of the circuit to be tested is selected from valid testing nodes according to a testability measurement value T of the circuit to be tested, and when the testability measurement value T is smaller than the number of circuit elements in the circuit to be tested, regular ambiguity sets are determined and at most one element is selected from each set to serve as the element to be diagnosed; establishing the sensitivity equation of each testing point in the optimum testing node set according to the variance (y(t)-y'(t)) <2> and obtaining a needed testing vector set by calculating the frequency of the extreme point of a flexibility curve, wherein y(t) is the normal output of each testing node and the y'(t) is the fault output of each testing node; deleting part of the testing vectors in the testing vector set to optimize the number of the testing vectors. The method for generating the testing vectors of the artificial circuit has the advantages that the complexity of calculation and processing is reduced, and the fault diagnosing speed is improved. The method for generating the testing vectors of the artificial circuit is particularly suitable for being used for testing and diagnosis of large-scale analogue integrated circuits.

Description

A kind of analog circuit test vector generation method
Technical field
The present invention relates to the ic test technique field, be specifically related to a kind of analog circuit test vector and generate (test and excitation) method.
Background technology
The essence of objective world signal has determined the ubiquitous and irreplaceability of mimic channel, carries out relevant theory and method research is particularly important.Fast development along with electronic technology, particularly the density of integrated circuit and integrated level improve, available test point is limited, traditional mode got involved by external contact is helpless, and this provides development opportunity for research and the application that mimic channel carries out Testability Analysis and test vector generation.
In recent years, researchers have carried out many work aspect analog circuit fault diagnosing, but attention rate is less aspect the test vector generation, usually rule of thumb selected, as: square wave, pulse and white noise etc., there is certain randomness, lack research qualitatively.The technical matters that the present invention solves is, overcome the above-mentioned defect that prior art exists, a kind of analog circuit test vector generation method based on Testability Analysis is provided: its core is that circuit is carried out to Testability Analysis, selects the Validity Test point of circuit-under-test, realizes determining fuzzy device; Then by Calculation of Sensitivity, instruct test vector to generate, and test vector is compressed to obtain optimum test set.The present invention generates very effective to the analog circuit test vector, reduced the computing complexity, has improved fault diagnosis speed, has stronger practicality.
Summary of the invention
The technical issues that need to address of the present invention are, how a kind of analog circuit test vector generation method is provided, can have reduced the computing complexity, improved fault diagnosis speed, there is very strong practicality, especially effective to extensive Analogous Integrated Electronic Circuits test and diagnosis.
Above-mentioned technical matters of the present invention solves like this: build a kind of analog circuit test vector generation method, it is characterized in that, comprise the following steps:
Testability Analysis: circuit under test is carried out to Testability Analysis, choose the best test node collection of circuit-under-test from the Validity Test node according to the measurability measure value T of circuit under test, and, when measurability measure value T is less than the circuit under test number of circuit elements, determines the Regularized Fuzzy group and from each group, select at most an element as element to be diagnosed;
Test vector generates: according to variance [y (t)-y ' (t)] 2set up best test node and concentrate the sensitivity equation of each test node, by the frequency at meter sensitivity curve extreme point place, obtain required test vector set; Y (t) is the normal output of test node, and y ' is (t) the fault output of test node;
Test vector compression: the test vector in the test vector set is deleted, optimized the test vector number.
According to generation method provided by the invention, described Testability Analysis step specifically comprises:
Calculate the network transfer function of each Validity Test point: but the diagnosis equation of circuit-under-test element by the network transfer function of selected test point, formed, but effectively the network transfer function of measuring point is as follows for each:
H l ( k ) ( s ) = N l ( p , s ) D ( p , s ) = &Sigma; i = 0 n a i ( k ) ( p ) b m ( k ) ( p ) s i s m + &Sigma; j = 0 m - 1 b j ( k ) ( p ) b m ( k ) ( p ) s j ; l=1,2Λ,K
Wherein: P=[p 1, p 2, Λ, p r] tbe the incipient fault vector, S is complex variable, and it is natural number that test node is counted K; Coefficient
Figure BDA0000373469020000022
with
Figure BDA0000373469020000023
being is the function of circuit element parameter; D is admittance matrix, N lthe matrix that k in admittance matrix D is capable in order to scratch, form after l row all elements.
Calculate the testability matrix of each test node: the testability matrix B that establishes k test node kas follows:
B k = 1 ( b m ( k ) ) 2 b m ( k ) &PartialD; a 0 ( k ) &PartialD; p 1 - a 0 ( k ) &PartialD; b m ( k ) &PartialD; p 1 K b m ( k ) &PartialD; a 0 ( k ) &PartialD; p q - a 0 ( k ) &PartialD; b m ( k ) &PartialD; p q &Lambda; &Lambda; &Lambda; b m ( k ) &PartialD; a n ( k ) &PartialD; p 1 - a n ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; a n ( k ) &PartialD; p q - a n ( k ) &PartialD; b m ( k ) &PartialD; p q b m ( k ) &PartialD; b 0 ( k ) &PartialD; p 1 - b 0 ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; b 0 ( k ) &PartialD; p q - b 0 ( k ) &PartialD; b m ( k ) &PartialD; p q &Lambda; &Lambda; &Lambda; b m ( k ) &PartialD; b m - 1 ( k ) &PartialD; p 1 - b m - 1 ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; b m - 1 ( k ) &PartialD; p q - b m - 1 ( k ) &PartialD; b m ( k ) &PartialD; p q
Wherein: P=[p 1, p 2, Λ, p q] tbe the incipient fault vector, it is natural number that test node is counted K; Coefficient
Figure BDA0000373469020000032
with
Figure BDA0000373469020000033
being is the function of circuit element parameter.
Preferred test point: calculate the measurability measure value T of circuit under test, formula is as follows:
T=rank(B T)=rank([B 1,B 2,Λ,B k] T)
According to the measurability measure value T of circuit under test, can choose the best test node collection of circuit-under-test; Wherein rank asks rank of matrix;
Determine fuzzy components and parts group: when measurability measure value T is less than the circuit under test number of circuit elements, determines the Regularized Fuzzy group and from each group, select at most an element as element to be diagnosed; If described measurability measure value T is more than or equal to the circuit under test number of circuit elements, choose arbitrarily element to be diagnosed from circuit under test.
According to generation method provided by the invention, the function of described circuit element parameter comprises inverse.
According to generation method provided by the invention, test vector generates step and specifically comprises:
Calculate best test node and concentrate the sensitivity equation of each test node: test frequency is selected in the application sensitivity analysis, and computing formula is as follows:
S p i H l ( k ) ( f ) = x H l ( k ) &PartialD; H l ( k ) &PartialD; p i = x H l ( k ) &PartialD; &PartialD; p i ( N l ( f , p i ) D ( f , p i ) )
Wherein: x is incipient fault components and parts values,
Figure BDA0000373469020000041
for Internet Transmission function, p ibe the incipient fault components and parts, D is admittance matrix, N lthe matrix that k in admittance matrix D is capable in order to scratch, form after l row all elements.
Draw best test node and concentrate the sensitivity curve figure of each test node;
The frequency at meter sensitivity curve extreme point place, obtain required test vector set.
According to generation method provided by the invention, described test vector compression step comprises that selecting one from a plurality of test frequencies makes the maximized frequency of each sensitivity curve difference.
Analog circuit test vector generation method provided by the invention, Analogous Integrated Electronic Circuits is being carried out on the basis of Testability Analysis, utilize the Calculation of Sensitivity formula to generate test vector, make normal output and the alienation of fault output difference of mimic channel reach maximum, thereby simplify the analog circuit fault diagnosing difficulty, finally the compression of test vector is processed, can be shortened the actual test duration, promote testing efficiency.The method can be carried out localization of fault fast and accurately to hard fault, soft fault and the multi-Fault State of mimic channel, has higher engineering using value.
The accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, further the present invention is described in detail.
Fig. 1 is the specific implementation steps flow chart schematic diagram of analog circuit test vector generation method of the present invention;
Fig. 2 is the emulation experiment circuit of application the inventive method: the logical state variable filter of band (Band Pass State Variable Filter is called for short BPSVF) circuit;
Fig. 3 is test point testability matrix 1.~5. in circuit shown in Fig. 2;
Fig. 4 is test point sensitivity curve figure 1. in circuit shown in Fig. 2;
Fig. 5 is test point sensitivity curve figure 3. in circuit shown in Fig. 2;
Fig. 6 is test point sensitivity curve figure 4. in circuit shown in Fig. 2;
Fig. 7 is test point sensitivity curve figure 5. in circuit shown in Fig. 2;
Fig. 8 is test point and test frequency schematic in circuit shown in Fig. 2.
Embodiment
At first, analog circuit test vector generation method of the present invention is described:
(i) principle
The method is carried out Testability Analysis to mimic channel to be measured: at first test point selected and rejected, then components and parts being carried out to ambiguity group and determine, having reduced the testing complex degree, having reduced the uncertainty in the test.The present invention calculates test frequency by sensitivity analysis, makes normal output y (t) and fault output y ' significant difference (t), i.e. variance [y (t)-y ' (t)] 2maximum, facilitated follow-up fault detect and location.To the compression of test vector, further reduced the calculated amount in the test process, promoted testing efficiency.
(ii) specific implementation
Mimic channel dynamic supply current generation method of the present invention comprises the following steps:
101) circuit under test is carried out to Testability Analysis.Select the Validity Test point of circuit-under-test, realize determining fuzzy device;
102) test vector generates.Then by Calculation of Sensitivity, carry out the test vector generation; And test vector is compressed to obtain optimum test set
103) test vector compression.The test vector obtained is compressed to obtain optimum test set;
Further, for step 101) in Testability Analysis, implementation procedure is as follows:
201) calculate the network transfer function of each test point.But the diagnosis equation of circuit-under-test element is comprised of the network transfer function of selected test point.But the network transfer function of each measuring point is as follows:
H l ( k ) ( s ) = N l ( p , s ) D ( p , s ) = &Sigma; i = 0 n a i ( k ) ( p ) b m ( k ) ( p ) s i s m + &Sigma; j = 0 m - 1 b j ( k ) ( p ) b m ( k ) ( p ) s j ; l=1,2,Λ,K
Wherein: P=[p 1, p 2, Λ, p r] tbe the incipient fault vector, K is the test node number; Coefficient
Figure BDA0000373469020000062
with
Figure BDA0000373469020000063
being is the function of circuit element parameter.
202) calculate the testability matrix of each test node.If the testability matrix B of k test node kas follows:
B k = 1 ( b m ( k ) ) 2 b m ( k ) &PartialD; a 0 ( k ) &PartialD; p 1 - a 0 ( k ) &PartialD; b m ( k ) &PartialD; p 1 K b m ( k ) &PartialD; a 0 ( k ) &PartialD; p q - a 0 ( k ) &PartialD; b m ( k ) &PartialD; p q &Lambda; &Lambda; &Lambda; b m ( k ) &PartialD; a n ( k ) &PartialD; p 1 - a n ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; a n ( k ) &PartialD; p q - a n ( k ) &PartialD; b m ( k ) &PartialD; p q b m ( k ) &PartialD; b 0 ( k ) &PartialD; p 1 - b 0 ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; b 0 ( k ) &PartialD; p q - b 0 ( k ) &PartialD; b m ( k ) &PartialD; p q &Lambda; &Lambda; &Lambda; b m ( k ) &PartialD; b m - 1 ( k ) &PartialD; p 1 - b m - 1 ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; b m - 1 ( k ) &PartialD; p q - b m - 1 ( k ) &PartialD; b m ( k ) &PartialD; p q
203) preferred test point.Calculate the measurability measure value T of circuit under test, formula is as follows:
T=rank(B T)=rank([B 1,B 2,Λ,B k] T)
According to the measurability measure value T of circuit under test, can choose the best test node collection of circuit-under-test.
204) determine fuzzy components and parts group.If in top (3), measurability measure value T is more than or equal to component number to be diagnosed, can guarantee the uniqueness of fault element isolation in circuit; If measurability measure value T is less than component number to be diagnosed, fault element can not uniquely be determined, ambiguity group just occurred.
For step 102) middle test vector generation, implementation procedure is as follows:
301) calculate the sensitivity equation of each test node.Test frequency is selected in the application sensitivity analysis, and differential sensitivity is applicable to soft fault diagnosis, is a kind of effective solution, makes normal output y (t) and fault output y ' significant difference (t), i.e. variance [y (t)-y ' (t)] 2maximum.Computing formula is as follows:
S p i H l ( k ) ( f ) = x H l ( k ) &PartialD; H l ( k ) &PartialD; p i = x H l ( k ) &PartialD; &PartialD; p i ( N ( f , p i ) D ( f , p i ) )
302) draw the sensitivity curve figure of each test node;
303) frequency at meter sensitivity curve extreme point place, obtain required test vector set.
For step 103) middle test vector compression, for a plurality of close test frequencies, can be accepted or rejected, realize the compression to test vector, to reduce the test duration.
The second, below in conjunction with concrete embodiment and accompanying drawing, the present invention is further elaborated, but the present invention is not limited to following embodiment.
Fig. 1 is performing step process flow diagram of the present invention.Mainly comprise content: Testability Analysis, realize that test point is preferably definite with the components and parts ambiguity group; Test vector generates, and utilizes sensitivity analysis to calculate test frequency; The test vector compression, reject the approaching Frequency point of partial data.
Fig. 2 is the BPSVF experimental circuit, and 5 available test nodes are: 1.~5..Below carry out test vector using the circuit of BPSVF shown in Fig. 2 as actual circuit under test and generate explanation.
As shown in Figure 3, be the testability matrix B of circuit under test shown in Fig. 2.Wherein:, be the admittance of each resistance element.Circuit is carried out to Testability Analysis, calculate the measurability measure value T=8 of circuit test node, in circuit, the diagnosable fault element number gone out is no more than at most 8, and the best test node collection of selected this circuit 1. 3. 4. 5..
After selected best test point set, carry out determining of ambiguity group element, guarantee the uniqueness that fault element to be measured solves.Determine that in experimental circuit, Regularized Fuzzy element group is: [C2, G9], [G6, G7], [G2, G3, G11], [G5, G10] and [C1, G1, G4, G8], in selected experimental circuit, fault element to be diagnosed is: { G2, G5, G6, C1, C2}, corresponding components and parts are { R2, R5, R6, C1, C2}.
Corresponding four selected test points, carry out respectively Calculation of Sensitivity, draws the sensitivity curve figure (as shown in Fig. 4 to 7) of each test node, thereby obtain the best fault diagnosis frequency of each fault element.The frequency (as shown in Figure 8) at meter sensitivity curve extreme point place.From Fig. 8, extract required test vector set: ω={ 1.3,0.6,1.8,1.9,2.0} (unit: 10 5the rad/s radian per second).By analyzing, the multifrequency test vector is compressed: as ω=1.8x10 5rad/s, can detect fully and can identify above-mentioned fault.
From the example of concrete enforcement, a kind of analog circuit test vector generation method that the present invention proposes, have purpose and practical characteristics, and the test vector formation speed is fast, very effective to the fault diagnosis of follow-up mimic channel.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the claims in the present invention scope change and modify, and all should belong to the covering scope of the claims in the present invention.

Claims (5)

1. an analog circuit test vector generation method, is characterized in that, comprises the following steps:
Testability Analysis: circuit under test is carried out to Testability Analysis, choose the best test node collection of circuit-under-test from the Validity Test node according to the measurability measure value T of circuit under test, and, when measurability measure value T is less than the circuit under test number of circuit elements, determines the Regularized Fuzzy group and from each group, select at most an element as element to be diagnosed;
Test vector generates: according to variance [y (t)-y ' (t)] 2set up best test node and concentrate the sensitivity equation of each test node, by the frequency at meter sensitivity curve extreme point place, obtain required test vector set; Y (t) is the normal output of test node, and y ' is (t) the fault output of test node;
Test vector compression: the test vector in the test vector set is deleted, optimized the test vector number.
2. generate according to claim 1 method, it is characterized in that, described Testability Analysis step specifically comprises:
Calculate the network transfer function of each Validity Test point: but the diagnosis equation of circuit-under-test element by the network transfer function of selected test point, formed, but each effective network transfer function of measuring point (s) as follows:
H l ( k ) ( s ) = N l ( p , s ) D ( p , s ) = &Sigma; i = 0 n a i ( k ) ( p ) b m ( k ) ( p ) s i s m + &Sigma; j = 0 m - 1 b j ( k ) ( p ) b m ( k ) ( p ) s j ; l=1,2,Λ,K
Wherein: P=[p 1, p 2, Λ, p r] tbe the incipient fault vector, S is complex variable, and it is natural number that test node is counted K; Coefficient
Figure FDA0000373469010000013
being is the function of circuit element parameter; D is admittance matrix, N lthe matrix that k in admittance matrix D is capable in order to scratch, form after l row all elements.
Calculate the testability matrix of each test node: the testability matrix B that establishes k test node kas follows:
B k = 1 ( b m ( k ) ) 2 b m ( k ) &PartialD; a 0 ( k ) &PartialD; p 1 - a 0 ( k ) &PartialD; b m ( k ) &PartialD; p 1 K b m ( k ) &PartialD; a 0 ( k ) &PartialD; p q - a 0 ( k ) &PartialD; b m ( k ) &PartialD; p q &Lambda; &Lambda; &Lambda; b m ( k ) &PartialD; a n ( k ) &PartialD; p 1 - a n ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; a n ( k ) &PartialD; p q - a n ( k ) &PartialD; b m ( k ) &PartialD; p q b m ( k ) &PartialD; b 0 ( k ) &PartialD; p 1 - b 0 ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; b 0 ( k ) &PartialD; p q - b 0 ( k ) &PartialD; b m ( k ) &PartialD; p q &Lambda; &Lambda; &Lambda; b m ( k ) &PartialD; b m - 1 ( k ) &PartialD; p 1 - b m - 1 ( k ) &PartialD; b m ( k ) &PartialD; p 1 &Lambda; b m ( k ) &PartialD; b m - 1 ( k ) &PartialD; p q - b m - 1 ( k ) &PartialD; b m ( k ) &PartialD; p q
Wherein: P=[p 1, p 2, Λ, p q] tbe the incipient fault vector, it is natural number that test node is counted K; Coefficient
Figure FDA0000373469010000022
with
Figure FDA0000373469010000023
being is the function of circuit element parameter.
Preferred test point: calculate the measurability measure value T of circuit under test, formula is as follows:
T=rank(B T)=rank([B 1,B 2,Λ,B k] T)
According to the measurability measure value T of circuit under test, can choose the best test node collection of circuit-under-test; Rank () means to ask rank of matrix;
Determine fuzzy components and parts group: when measurability measure value T is less than the circuit under test number of circuit elements, determines the Regularized Fuzzy group and from each group, select at most an element as element to be diagnosed; If described measurability measure value T is more than or equal to the circuit under test number of circuit elements, choose arbitrarily element to be diagnosed from circuit under test.
3. generate according to claim 2 method, it is characterized in that, the function of described circuit element parameter comprises inverse.
4. generate according to claim 1 method, it is characterized in that, described test vector generates step and specifically comprises:
Calculate best test node and concentrate the sensitivity equation of each test node: test frequency is selected in the application sensitivity analysis, and computing formula is as follows:
S p i H l ( k ) ( f ) = x H l ( k ) &PartialD; H l ( k ) &PartialD; p i = x H l ( k ) &PartialD; &PartialD; p i ( N l ( f , p i ) D ( f , p i ) )
Wherein: x is incipient fault components and parts values,
Figure FDA0000373469010000025
for Internet Transmission function, p ibe the incipient fault components and parts, D is admittance matrix, N lthe matrix that k in admittance matrix D is capable in order to scratch, form after l row all elements.
Draw best test node and concentrate the sensitivity curve figure of each test node;
The frequency at meter sensitivity curve extreme point place, obtain required test vector set.
5. generate according to claim 1 method, it is characterized in that, described test vector compression step comprises that selecting one from a plurality of test frequencies makes the maximized frequency of each sensitivity curve difference.
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CN107085179B (en) * 2017-05-12 2019-07-02 哈尔滨工业大学 It is a kind of based on tightness evaluation analog circuit fault detection in test and excitation generation method
CN111175635A (en) * 2019-12-31 2020-05-19 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) Integrated circuit testing device
CN111175635B (en) * 2019-12-31 2021-12-03 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) Integrated circuit testing device
CN111398777A (en) * 2020-03-10 2020-07-10 哈尔滨工业大学 Simulation circuit test excitation optimization method based on synthetic deviation
CN111398777B (en) * 2020-03-10 2022-03-15 哈尔滨工业大学 Simulation circuit test excitation optimization method based on synthetic deviation

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Application publication date: 20131211