CN109725248A - A kind of the on piece detection system and test method of identification aging recycling integrated circuit - Google Patents
A kind of the on piece detection system and test method of identification aging recycling integrated circuit Download PDFInfo
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Abstract
The present invention discloses the on piece detection system and test method of a kind of identification aging recycling integrated circuit, which includes target detection register, peripheral circuit, time-delay calibration module, clock path and the several parts of critical path；This method comprises: step 1: configuration target detection register；Step 2: the alignment path in time delay calibration module is calibrated；Step 3: calibration result is exported as test data vector；Step 4: ageing time is solved according to theoretical model；Step 5: Off-chip test process.The invention has the advantages that: area and power dissipation overhead are smaller；It is easy to be deployed on large-scale integrated circuit, is used as on-chip testing structure；The ageing time error very little for identifying the experience of aging recycling integrated circuit, is no more than 30 days；The measuring accuracy of time-delay calibration module is very high, can reach 15ps；It is able to detect working performance of the chip under current ageing state.
Description
Technical field
It is especially a kind of the present invention relates to the on piece detection system and test method of a kind of identification aging recycling integrated circuit
Aging can be identified in the way of path delay of time calibration or recycle the on piece detection system and test method of integrated circuit, belong to
In the field Design for testability of digital integrated circuits (Design For Test).
Background technique
In recent years, it more and more forges integrated circuit (Counterfeit Integrated Circuit) and flows into electronics
In component supply chain.This, which not only brings to IC design and manufacturer, feels economic loss, equally to user with
Great security threat and hidden danger are come.Nowadays it forges integrated circuit and has become the common of government and entire electronics and information industry
Worry.Wherein be more than 80% forgery integrated circuit be all aging recycling integrated circuit, and aging recycling integrated circuit must
Performance drop occurs for the effect that so will receive the aging effects such as negative bias thermal instability (NBTI) and hot carrier in jection (HCI)
Grade.Wherein performance parameter degradation the most significant is exactly the increase in the path delay of time, i.e. Δ P (t), wherein t is integrated circuit experience
Ageing time.
By retrieving to existing technical literature, we are it can be found that remove traditional forgery integrated circuit detection mode, such as
The unclonable function of physics (PUF, Physical Unclonable Function) design, hardware metering method (Hardware
Metering except), computer aided design (CAD, Computer-Aided Design), ring oscillator (RO, Ring
Oscillator) and Analysis of Reliability Data method (Reliability Statistical Analysis) is several present masters
The detection aging recycling integrated circuit means wanted.But the generally existing following items defect of above scheme:
1. area and power dissipation overhead are too big；
2. detection or accuracy of identification are not high enough；
3. user uses and testing cost is high；
4. the current performance state of chip can not be detected.
Summary of the invention
The purpose of the present invention is to provide it is a kind of identification aging recycling integrated circuit on piece detection system and test method,
Design the on piece detection system of deterioration degree Δ P (t) for being able to indicate that the path delay of time a kind of, thus identify integrated circuit or
The ageing time of chip experience.What the on piece detection system can be connected by controlling alignment path (Calibration Path)
Buffer (Buffer) number carry out time-delay calibration (Calibration) mode, will calibration the path delay of time and clock signal into
Row calibration.The variation of number of buffers N to be connected into the alignment path after the corresponding calibration of different ageing time t, characterization
Current ageing step and ageing time.Such on piece detection system design can reach a kind of work of ageing time " tagging "
With.
The on piece detection system for a kind of identification aging recycling integrated circuit that the present invention designs, mainly by following components
Composition:
1. target detection register.Jtag interface with chip for test interacts, and user is inputted by jtag interface and surveyed
Try data vector (TDV, Test Data Vector) configuration target detection register (TDR, Test Data Register).Pole
The pin expense of on piece design is saved greatly.
2. peripheral circuit.It is made of control logic, decoder and encoder.The Configuration Values of target detection register are by outer
Enclose circuit code, exporting one group of control signal gives time-delay calibration module later for decoding.
3. time-delay calibration module (DCM, Delay Calibration Module).DCM module is by alignment path and two
Register FF1 and FF2 composition, the output of FF1 enter the input of FF2 by alignment path later.Alignment path is one by delaying
Rush the long path that device and multiple selector are constituted, wherein a buffer and a multiple selector are exactly the one of alignment path
Grade.Selection signal (n-BSS, n-bit Buffer of the control signal exported from peripheral circuit as n grades of buffers
Selection Signal) number of buffers being connected into is controlled, change the time delay of alignment path, to carry out school with clock signal
It is quasi-.
4. clock path and critical path.The period of clock signal is capable of providing an accurate Delay, so through
The clock signal of system in oversampling clock path is used as the reference signal in calibration process.Critical path refers to the single clock domain of chip
It is interior, that maximum a collection of path of the path delay of time, therefore the influence for being most susceptible to aging effect causes the performance degradation of chip.Cause
This measures the time delay of critical path by the alignment path calibrated by clock signal, obtains chip under current ageing state
Performance.
A kind of test method of the on piece detection system for identification aging recycling integrated circuit that the present invention designs, specific steps
It is as follows:
Step 1: configuration target detection register.Using jtag interface input test data vector (hereinafter referred to as TDV),
Target detection register (hereinafter referred to as TDR) is configured, the logical value that each register stores in TDR is determined.TDR
Built-in command and TDV export control signal to time-delay calibration module for calibrating after peripheral circuit decodes.
Step 2: the alignment path in time delay calibration module is calibrated.By the n grade buffer of peripheral circuit output
Selection signal controls alignment path by way of being connected into the quantity of buffer in gating alignment path as control signal
Time delay increasing or decreasing step by step.Under the effect of different ageing times, the number of buffers difference of alignment path is connected by controlling,
Signal is calibrated.
Step 3: calibration result is exported as test data vector.When reference signal is calibrated correctly, by control at this time
Signal processed, TDR instruction, the test data output and input are exported as TDV to user.
Step 4: ageing time is solved according to theoretical model.It in the present invention will be with negative bias thermal instability
(NBTI, Negative-Bias Temperature Instability) aging effect is basic theoretical model, according to testing
To TDV and the path delay of time-ageing time model go solve to-be-measured integrated circuit ageing time.
Step 5: Off-chip test process.For carrying the completely new chip of on piece detection system of the invention, manufacturer obtains first
To its factory test parameter, that is, calibration result TDV；Then it to such one group completely new chip sample accelerated ageing, is corresponded to
The TDV of different ageing times；Database is established by sample, trains each aging moment using support vector machine classification method
TDV identify boundary；Ageing time look-up table is established according to these identification boundaries, for user query.
The on piece detection system and test method, advantage for a kind of identification aging recycling integrated circuit that the present invention designs exist
In:
1. area and power dissipation overhead are smaller；
2. being easy to be deployed on large-scale integrated circuit, it is used as on-chip testing structure；
3. identifying the ageing time error very little of the experience of aging recycling integrated circuit, it is no more than 30 days；
4. the measuring accuracy of time-delay calibration module is very high, 15ps can be reached；
5. being able to detect working performance of the chip under current ageing state.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the on piece detection system of identification aging recycling integrated circuit of the present invention.
Fig. 2 is the structural schematic diagram and coherent signal of time-delay calibration module (DCM).
Fig. 3 is the Off-chip test process that the present invention designs.
Specific embodiment
Below with reference to accompanying drawings, the concrete operations for the aging recycling integrated circuit on piece detection system that the present invention designs are introduced
Process and embodiment.
Step 1: tester and user have configured target detection by jtag test access port (hereinafter referred to as TAP) and have posted
Storage (hereinafter referred to as TDR) determines the logical value that each register stores in TDR.Instruction and test data inside TDR to
It is (following to measure (hereinafter referred to as TDV) selection signal of n grades of buffers of output after the control logic decoding of peripheral control circuits
Abbreviation n-BSS) control buffer (Buffer) quantity that alignment path is connected into.Wherein n-BSS signal will be used for subsequent step
Among the outer testing process of four piece.
Step 2: time-delay calibration module not only needs to be calibrated by clock signal, while can also play detection critical path
The effect of (Critical Path) time delay deterioration degree.In the design of DCM, clock path and critical path (Critical
Path it) is mutually calibrated by a multiple selector MUX1 as shown in Figure 1 with alignment path (Calibration Path).It is surveying
Under die trial formula, the d type flip flop (D flip-flop) for being named as FF1 automatically generates rising edge signal, then these pumping signals
The D input terminal of register FF2 is sent to by the alignment path (Calibration Path) entirely gated in DCM module.
At the same time, a same clock signal or the rising edge signal of pulse pass through the clock path selected or critical path
(Critical Path) is sent to the CK input end of clock of FF2, drives clock signal.When the logical value that the Q output of FF2 exports
When being ' 1 ', it may be said that the time delay of bright alignment path (Calibration Path) is more shorter than clock cycle.Conversely, working as the Q of FF2
When output end output logical value is ' 0 ', illustrate that the time delay of alignment path (Calibration Path) is longer than clock cycle.Together
Reason can also will calibrate the path delay of time when critical path (Critical Path) conduct, which is routed, to be connected by MUX1
It is compared with critical path time delay, to achieve the purpose that the detection system detects critical path time delay.
Before testing begins, the TDV inputted by TDI pin is after having configured TDR, first to the whole in DCM
Register (D Flip-Flop) resets.It is calibrated at this time, register FF2 output is ' 1 '.TAP controller is in jtag test
A state machine defined in agreement controls the test operation stage by internal state change, realizes test instruction and data
Input and output.TAP controller enters Update-DR state, and the test data TDV in configured TDR passes through parallel output
(PO, Parallel Output) interface inputs the peripheral circuit of system on chip, exports n- by control logic after decoding
BSS signal.TDV passes through the variation of the input logic value of control n-BSS signal, and the path delay of time for controlling alignment path successively decreases, directly
Output to register FF2 becomes ' 0 ' from logical value ' 1 '.When register FF2 output becomes ' 0 ' from ' 1 ', illustrate school at this time
The quasi- path delay of time and the period of clock alignment signal are closest, at this time one can consider that the path delay of time of alignment path is by school
Standard is system clock cycle.
Step 3: after calibration operation each time is completed, the logical value of n-BSS signal is after peripheral circuit code
By inputting (PI, Parallel Input) interface parallel by parallel read-out to target detection register (TDR), pass through TDO
Pin Serial output.Test data from the instruction of TDI serial input and from TDO Serial output is as a result, such as n-BSS signal logic
Value, TDR instruction etc., collectively constituting TDV will be used among subsequent outer testing process.
Step 4: with negative bias thermal instability (NBTI, Negative-Bias Temperature
Instability) aging effect is basic theoretical model, and the TDV and the path delay of time-ageing time model obtained according to test is gone
Solve the ageing time of to-be-measured integrated circuit.
The chip of aging recycling on piece detection system is deployed when dispatching from the factory test, alignment path (Calibration
Path the path delay of time) can be fixed to system clock cycle, can use T0It indicates.After it experienced one section using the time, warp
Certain ageing process is gone through, when alignment path, which postpones a meeting or conference, occurs a degree of deterioration, at this time can be with using the user of the chip
Alignment path (Calibration Path) is recalibrated by jtag interface, changes test input stimulus and instruction
TDV, control reduce the number of buffers being connected into and series step by step, until alignment path time delay was re-calibrated as the clock cycle
T0.According to path delay of time formula, available clock signal period T0It is surveyed with the n-BSS signal in test data vector T DV twice
Magnitude N0And N1Relationship, stated with following equation are as follows:
Wherein, N0And N1What is respectively represented be same chip in ageing time is t0And t1Moment, alignment path
The buffer series that (Calibration Path) is connected into, that is, the logical value result of n-BSS signal.N0And N1Entire old
There are among test data vector T DV in the testing process of change recycling integrated circuit.D0(i)Be ageing time be t0At the time of,
The gate delay of i-th of buffer in alignment path.D1(j)Be then ageing time be t1At the time of, in alignment path j-th it is slow
Rush the gate delay of device.
In addition, under the premise of ignoring manufacture uncertainty, it, can be to each according to test data existing in TDV
The time delay for the buffer being connected into is estimated.To according to the deterioration degree of each Buffer-Delay, it is established that the number in TDV
According to N0And N1, clock cycle T0With the relationship between ageing time t.In alignment path, single buffer gate delay is from t0To t1
The deterioration degree at moment are as follows:
Wherein Δ D is that the single Buffer-Delay in alignment path undergoes ageing time t (t=t1-t0) changing value.
Therefore, we are by (1) and (2) simultaneous, and it is old to be updated to time delay-under NBTI aging action described in (3)
Change in time model:
And by simplification of a formula parameter normalization, multiple N in available ageing time t and test data vector T DV it
Between relationship, stated with following equation:
Wherein ANBTIAnd BNBTIAll it is the complex parameter under the effect of NBTI effect, usually makees with device technology and material, aging
Use environmental correclation.
Step 5: it is integrated with outside the piece of the chip of the system on chip of identification aging recycling integrated circuit according to the present invention
Testing process is as follows.In Off-chip test process, using the data analysing method based on machine learning, support vector machines point is used
Class (SVM, Support Vector Machine Classification) is established by being trained to multi-group data vector
The path delay of time (Path Delay) for playing alignment path and test data vector (TDV) are at different ageing steps and moment
Classification boundaries.
As shown in figure 3, Off-chip test process is broadly divided into seven stages:
(1) completely new chip factory test parameter.When a completely new chip is produced factory, alignment path
The path delay of time of (Calibration Path) will be calibrated to T by clock signal0.Corresponding test data vector is TDV0,
TDV0The number of buffers and series that one group of alignment path of middle record is connected into are N0.Initial critical path will also be calibrated road
The number of buffers that diameter is connected into is calibrated to Np, information is recorded in test data vector T DVpAmong.These factory test parameters are remembered
Record opens in the product database of manufacturer to legitimate user.
(2) test data vector.Each chip to be measured can provide one group of test data vector T DVs, including
It is t in ageing time1Moment, record alignment path are connected into number of buffers N1Test data vector T DV1.It simultaneously further include note
Record critical path calibration result N at this timeqTest data vector T DVqEtc..In addition, in each test data vector T DV,
It in fact all include the calibration result N of multiple groups different zones, the alignment path of model and clock signal1(a), N1(b)... ...,
N1(x), so test data vector T DV1It can be expressed as the form of a vector
(3) factory test.When this batch of chip is just dispatched from the factory by manufacture, alignment path (Calibration
Path the path delay of time) will be calibrated by clock signal period, i.e. T0.Manufacturer is slow by what is be connected into alignment path at this time
Rush device number N0It is recorded as factory test parameter, deposits the test data vector T DV for recording the factory test parameter0, vector form expression
ForFactory test parameter N0And factory test data vectorIt will
It is supplied to user together with the product of factory.
(4) user tests.When user takes the chip bought through various channels, it is desirable to identify this one or a set of core
Piece whether be aging recycling forgery integrated circuit.Since the on piece detection system of recycling integrated circuit has been deployed in advance
On chip, while factory test parameter N also is provided for user0And factory test data vector
Therefore user only needs to configure target detection register TDR by jtag interface, by simple several steps to school
Quasi- path is calibrated with clock signal, obtains the calibration result i.e. N in this chip to be measured1And test data vector T DV1,
Vector form is expressed asThe N provided according to manufacturer0And TDV0, available to be connected into buffering
The changes delta N=N of device number0-N1And the difference of test data vectorIf user pays close attention to the chip
Critical component performance can also obtain critical path calibration result N by testqAnd corresponding test data vector T DVq, with
N1And TDV1It is similar, but do not do excessive discussion herein.
(5) burn-in test.Before chip factory, manufacturer is in order to screen out bad piece, determine the reliable of the batch chip
Property degree, can manufacture test among be added defect and accelerated ageing test (Burn-In Test).In accelerated ageing test
In the process, manufacturer can determine corresponding chip ageing time under different test pressure, under such testing condition to piece
Upper detection structure is calibrated, and determines this aging moment corresponding calibration result.As shown in figure 3, in chip ageing time
For t1At the time of, corresponding alignment path is connected into number of buffers N1And test data vector T DV1；It is in chip ageing time
t2At the time of, corresponding alignment path is connected into number of buffers N2And test data vector T DV2；……；In chip aging
Between be txAt the time of, corresponding alignment path is connected into number of buffers NxAnd test data vector T DVx。
(6) training boundary.Exist since manufacture is uncertain, experienced same ageing time t1Different chips it is corresponding
Calibration result N1And test data vector T DV1It is not the same, so can not be directly old according to single test result resume
Change time look-up table.Manufacturer must test a large amount of chip under a variety of test conditions and environment, obtain complete
The test result in face.After having collected enough test datas, according to ageing time t, calibration result N and test data
Vector T DVs can be used support vector machines (SVM, Support Vector Machine) training and obtain completely new integrated circuit
Boundary can also determine identification boundary by the method for svm classifier for each aging moment.It, can under this boundary condition
To set up ageing time look-up table, as long as user obtains calibration result N and test data vector T DVs just can be by looking into
The modes such as table determine the ageing time of chip to be measured.
(7) ageing time look-up table (LUT, Look-Up Table).Set up different calibration result difference DELTA N and survey
The look-up table that examination data vector TDVs corresponds to different ageing time ranges feeds back to user, for inquiry.
Claims (2)
1. a kind of on piece detection system of identification aging recycling integrated circuit, it is characterised in that: the system includes following portion
Point: target detection register, peripheral circuit, time-delay calibration module, clock path and critical path；
Target detection register, the jtag interface with chip for test interact, and user passes through jtag interface input test data
Vector, configuration target detection register；
Peripheral circuit is made of control logic, decoder and encoder, and the Configuration Values of target detection register pass through peripheral circuit
One group of control signal, which is exported, after coding, decoding gives time-delay calibration module；
Time-delay calibration module is made of alignment path and two registers FF1 and FF2, and the output of register FF1 is by calibration road
Enter the input of register FF2 after diameter；Alignment path is the long path being made of buffer and multiple selector,
In, a buffer and a multiple selector are exactly the level-one of alignment path；The control signal exported from peripheral circuit is as n
The selection signal of grade buffer controls the number of buffers being connected into, and changes the time delay of alignment path, to carry out with clock signal
Calibration；
Clock path and critical path: the period of clock signal is capable of providing an accurate Delay, so through oversampling clock
The clock signal of system in path is used as the reference signal in calibration process；Critical path refers in the single clock domain of chip, road
That maximum a collection of path of diameter time delay；The time delay that critical path is measured by the alignment path calibrated by clock signal, obtains
Performance of the chip under current ageing state.
2. a kind of test method of the on piece detection system of identification aging recycling integrated circuit, it is characterised in that: this method is specific
Steps are as follows:
Step 1: configuration target detection register
Using jtag interface input test data vector, target detection register is configured, determines target detection deposit
The logical value that each register stores in device；Target detection register built-in command and test data vector pass through peripheral circuit
After decoding, control signal is exported to time-delay calibration module for calibrating；
Step 2: the alignment path in time delay calibration module is calibrated
Control signal is used as by the selection signal of the n grade buffer of peripheral circuit output, it is slow by being connected into gating alignment path
The mode for rushing the quantity of device controls the time delay of alignment path increasing or decreasing step by step；Under the effect of different ageing times, pass through control
The number of buffers that system is connected into alignment path is different, calibrates to signal；
Step 3: calibration result is exported as test data vector
When reference signal is calibrated correctly, by control signal, target detection register instruction, the survey output and input at this time
Examination data are exported as test data vector to user；
Step 4: ageing time is solved according to theoretical model
It is basic theoretical model, the test data vector sum road obtained according to test with negative bias thermal instability aging effect
Diameter time delay-ageing time model goes to solve the ageing time of to-be-measured integrated circuit；
Step 5: Off-chip test process
To the completely new chip for carrying the on piece detection system, the factory test parameter i.e. calibration result for obtaining it first is tested
Data vector；Then to such one group completely new chip sample accelerated ageing, the test data for corresponding to different ageing times is obtained
Vector；Establish database by sample, using support vector machine classification method train the test data at each aging moment to
Amount identification boundary；Ageing time look-up table is established according to these identification boundaries, for user query.
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| CN110988652A (en) * | 2019-11-28 | 2020-04-10 | 西安电子科技大学 | Recovered chip detection method and detection circuit thereof |
| CN111175635A (en) * | 2019-12-31 | 2020-05-19 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Integrated circuit testing device |
| CN111693847A (en) * | 2020-05-18 | 2020-09-22 | 大唐微电子技术有限公司 | Chip testing method and device |
| CN113391193A (en) * | 2021-06-25 | 2021-09-14 | 合肥工业大学 | Circuit aging test method based on BIST structure and self-oscillation ring |
| RU2757977C1 (en) * | 2020-08-24 | 2021-10-25 | Виталий Николаевич Старцев | Method for identifying used counterfeit microchips based on the degradation properties of sram |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110988652A (en) * | 2019-11-28 | 2020-04-10 | 西安电子科技大学 | Recovered chip detection method and detection circuit thereof |
| CN110988652B (en) * | 2019-11-28 | 2021-07-02 | 西安电子科技大学 | Recovered chip detection method |
| CN111175635A (en) * | 2019-12-31 | 2020-05-19 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Integrated circuit testing device |
| CN111175635B (en) * | 2019-12-31 | 2021-12-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Integrated circuit testing device |
| CN111693847A (en) * | 2020-05-18 | 2020-09-22 | 大唐微电子技术有限公司 | Chip testing method and device |
| RU2757977C1 (en) * | 2020-08-24 | 2021-10-25 | Виталий Николаевич Старцев | Method for identifying used counterfeit microchips based on the degradation properties of sram |
| CN113391193A (en) * | 2021-06-25 | 2021-09-14 | 合肥工业大学 | Circuit aging test method based on BIST structure and self-oscillation ring |
| CN113391193B (en) * | 2021-06-25 | 2023-11-21 | 合肥工业大学 | Circuit burn-in test method based on BIST structure and self-oscillating ring |
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Application publication date: 20190507 |