CN116126366B - Chip input/output interface configuration method, device, medium and electronic equipment - Google Patents
Chip input/output interface configuration method, device, medium and electronic equipment Download PDFInfo
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Abstract
The invention discloses a method, a device, a medium and electronic equipment for configuring an input/output interface of a chip, which comprises the following steps: in response to the operation of the task to be executed, determining to complete function codes corresponding to a plurality of function subtasks corresponding to the task to be executed, and acquiring functions and pin information corresponding to each function code from a pre-configured function information model; according to the execution thread of the task to be executed, the functions and the pin information are mapped into the chip in sequence, and after the mapping is completed, the program burning is carried out on the integrated circuit functional blocks of the chip according to the function information in the functions and the pin information so as to complete the configuration of the input and output interfaces of the chip; and generating a burning completion report, displaying the burning completion report to a user, and executing a plurality of function subtasks according to the execution thread in response to the execution starting instruction. The method reduces the work of field personnel, facilitates the field engineering application, realizes the rapid deployment of tasks, accelerates the progress of engineering application, and reduces the equipment maintenance and update cost.
Description
Technical Field
The invention relates to the technical field of equipment control, in particular to a method, a device, a medium and electronic equipment for configuring an input/output interface of a chip.
Background
Along with the expansion of the control field and the diversification of various control scenes, the field device control application is continuously changed, and accordingly, the control device control application works such as program compiling and interface definition aiming at the control device. Currently, when service logic and service content of a service application site are unchanged, function input/output positions are unchanged, and the equipment has a parameter configuration function, field engineering technicians modify fixed parameters and store the parameters into the device, and under the condition that reprogramming is not needed, the adaptation to the field application is realized. When the business logic or the business content is changed, a programmer writes a corresponding program, the business input and the business output are fixedly corresponding to the corresponding hardware output, after the program is compiled, the field engineering technician downloads the compiled program to the device, and the field business requirement is met. When the field control object is changed, the whole set of control system needs to be updated or replaced to meet the field requirement.
In the prior art, when a function outlet or input is changed, a specific reprogramming test is needed, so that the deployment time of field service applications is prolonged, and more programmers are needed to participate in service development along with the increase of the field applications. The method of parameter configuration is only suitable for the scene that the business hardware outlet is not changed, and when the business control object is changed, the reprogramming is still needed.
Disclosure of Invention
Aiming at the technical problem of low convenience in chip input/output interface configuration in the prior art, the invention provides a chip input/output interface configuration method, a device, a medium and electronic equipment.
In order to achieve the above purpose, the invention is realized by the following technical scheme:
in a first aspect of the embodiment of the present invention, a method for configuring an input/output interface of a chip is provided, where the method includes:
determining to complete function codes corresponding to a plurality of function subtasks corresponding to a task to be executed in response to the operation of the task to be executed, and acquiring functions and pin information corresponding to each function code from a pre-configured function information model, wherein the function subtasks are minimum task units obtained by decoupling the task which can be executed by the chip, and the function codes corresponding to each function subtask are obtained by coding the pin number and pin position list of the function subtask;
according to the execution thread of the task to be executed, mapping the functions and the pin information into the chip in sequence, and after mapping is completed, programming an integrated circuit functional block of the chip according to the function information in the functions and the pin information so as to complete the configuration of the chip input/output interface;
After the programming is completed, a programming completion report is generated, the programming completion report is displayed to a user, and the execution starting instruction is responded, and the plurality of function subtasks are executed according to the execution thread to complete the task to be executed.
In one embodiment, the step of sequentially mapping the function and pin information into the chip according to the execution thread of the task to be executed includes:
writing the number of input pins and the number of output pins through a communication protocol of the chip, and after the number of the input pins is successfully written and the number of the output pins is successfully written, arranging the input pins according to the execution thread of the task to be executed to obtain a position list value of the input pins;
performing pin mapping on each input pin according to the position list value, performing pin mapping on an output pin corresponding to each input pin after the input pin mapping is completed, and arranging and generating the position list value of the output pin according to the position relation of the output pin after the output pin mapping is completed;
and mapping the pin information corresponding to the function and the pin information into the chip according to the position list value of the input pin and the position list value of the output pin.
In one embodiment, the step of arranging the input pin according to the execution thread of the task to be executed to obtain the position list value of the input pin includes:
arranging the input pins according to the execution thread of the task to be executed and the integrated circuit functional blocks of the chip, and determining whether different functional subtasks share the same integrated circuit functional block according to the integrated circuit functional blocks corresponding to the functional subtasks after the arrangement is completed;
and under the condition that the fact that any different functional subtasks share the same integrated circuit functional block is determined, obtaining the position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional blocks.
In one embodiment, the method further comprises:
under the condition that the fact that different function subtasks share the same integrated circuit functional block is determined, determining whether different function subtasks shared by the same integrated circuit functional block have execution conflicts according to the execution sequence of different function subtasks shared by the same integrated circuit functional block in an execution thread of the task to be executed, wherein the execution sequence of the different function subtasks shared by the same integrated circuit functional block in the execution thread of the task to be executed characterizes that the different function subtasks shared by the same integrated circuit functional block have the execution conflicts under the condition that the different function subtasks shared by the same integrated circuit functional block are executed simultaneously;
Under the condition that execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, obtaining a position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional block; or,
under the condition that execution conflict exists among different function subtasks shared by the same integrated circuit functional block, the same integrated circuit functional block shared by different function subtasks is determined to be the integrated circuit functional block to be adjusted, input pins corresponding to the function subtasks corresponding to the integrated circuit functional block to be adjusted are replaced to an idle integrated circuit functional block with the integrated circuit functional block to be adjusted in the chip until execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, and a position list value of the input pins is obtained according to the sequence of input pins after the integrated circuit functional block is adjusted and the position relation of the corresponding integrated circuit functional block.
In one embodiment, the step of determining, in response to obtaining the operation of the task to be performed, that the function codes corresponding to the plurality of function subtasks corresponding to the task to be performed are completed includes:
According to the operation of defining the number of input variables, the number of output variables and functions in the tool software by field personnel, generating a task to be executed;
responding to the operation of the task to be executed, and calling a preset task creation function according to the function, wherein the task creation function is used for decoupling the function so as to disassemble the function containing a plurality of function subtasks into a plurality of minimum task units, and the minimum task units and the function subtasks have a one-to-one correspondence;
and determining the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed according to the minimum task unit obtained after the function disassembly.
In one embodiment, the preconfigured function information model generates the function and pin information corresponding to each function code by:
for any function subtask, determining the number of input pins and the number of output pins corresponding to the function subtask;
writing the number of the input pins as the first-level information of the input pin information of the function subtask, and writing the number of the output pins as the first-level information of the output pin information of the function subtask;
Writing a pin position list in the primary information of the input pin information and a pin position list in the primary information of the output pin information, wherein the pin position list comprises pin positions corresponding to each list, the pin positions corresponding to the input pins are used as secondary information of the input pin information, and the pin positions corresponding to the output pins are used as secondary information of the output pin information;
and sequentially encoding according to the input pin information and the output pin information, and adding a function description after encoding is completed to obtain a function and pin information corresponding to the function encoding.
In one embodiment, the step of sequentially mapping the function and pin information into the chip according to the execution thread of the task to be executed includes:
and configuring the electronic equipment of the chip to execute a startup reading function, reading the stored function and pin information according to the execution thread of the task to be executed, and mapping the function and the pin information into the chip in sequence.
In a second aspect of the embodiment of the present invention, there is provided a chip input/output interface configuration apparatus, the apparatus including:
The function subtask determining module is configured to determine, in response to the operation of obtaining a task to be executed, function codes corresponding to a plurality of function subtasks corresponding to the task to be executed, and obtain functions and pin information corresponding to each function code from a pre-configured function information model, wherein the function subtasks are minimum task units obtained by decoupling the task which can be executed by the chip, and the function codes corresponding to each function subtask are obtained by coding the pin number and pin position list of the function subtask;
the program burning module is configured to map the functions and the pin information into the chip in sequence according to the execution thread of the task to be executed, and after mapping is completed, program burning is performed on the integrated circuit functional block of the chip according to the function information in the functions and the pin information so as to complete the configuration of the chip input/output interface;
and the execution module is configured to generate a recording completion report after the program recording is completed, display the recording completion report to a user, respond to an execution starting instruction, execute the plurality of function subtasks according to the execution thread and complete the task to be executed.
In one embodiment, the program burning module is configured to:
writing the number of input pins and the number of output pins through a communication protocol of the chip, and after the number of the input pins is successfully written and the number of the output pins is successfully written, arranging the input pins according to the execution thread of the task to be executed to obtain a position list value of the input pins;
performing pin mapping on each input pin according to the position list value, performing pin mapping on an output pin corresponding to each input pin after the input pin mapping is completed, and arranging and generating the position list value of the output pin according to the position relation of the output pin after the output pin mapping is completed;
and mapping the pin information corresponding to the function and the pin information into the chip according to the position list value of the input pin and the position list value of the output pin.
In one embodiment, the program burning module is configured to:
arranging the input pins according to the execution thread of the task to be executed and the integrated circuit functional blocks of the chip, and determining whether different functional subtasks share the same integrated circuit functional block according to the integrated circuit functional blocks corresponding to the functional subtasks after the arrangement is completed;
And under the condition that the fact that any different functional subtasks share the same integrated circuit functional block is determined, obtaining the position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional blocks.
In one embodiment, the program burning module is configured to:
under the condition that the fact that different function subtasks share the same integrated circuit functional block is determined, determining whether different function subtasks shared by the same integrated circuit functional block have execution conflicts according to the execution sequence of different function subtasks shared by the same integrated circuit functional block in an execution thread of the task to be executed, wherein the execution sequence of the different function subtasks shared by the same integrated circuit functional block in the execution thread of the task to be executed characterizes that the different function subtasks shared by the same integrated circuit functional block have the execution conflicts under the condition that the different function subtasks shared by the same integrated circuit functional block are executed simultaneously;
under the condition that execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, obtaining a position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional block; or,
Under the condition that execution conflict exists among different function subtasks shared by the same integrated circuit functional block, the same integrated circuit functional block shared by different function subtasks is determined to be the integrated circuit functional block to be adjusted, input pins corresponding to the function subtasks corresponding to the integrated circuit functional block to be adjusted are replaced to an idle integrated circuit functional block with the integrated circuit functional block to be adjusted in the chip until execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, and a position list value of the input pins is obtained according to the sequence of input pins after the integrated circuit functional block is adjusted and the position relation of the corresponding integrated circuit functional block.
In one embodiment, the functional subtask determination module is configured to:
according to the operation of defining the number of input variables, the number of output variables and functions in the tool software by field personnel, generating a task to be executed;
responding to the operation of the task to be executed, and calling a preset task creation function according to the function, wherein the task creation function is used for decoupling the function so as to disassemble the function containing a plurality of function subtasks into a plurality of minimum task units, and the minimum task units and the function subtasks have a one-to-one correspondence;
And determining the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed according to the minimum task unit obtained after the function disassembly.
In one embodiment, the preconfigured function information model generates the function and pin information corresponding to each function code by:
for any function subtask, determining the number of input pins and the number of output pins corresponding to the function subtask;
writing the number of the input pins as the first-level information of the input pin information of the function subtask, and writing the number of the output pins as the first-level information of the output pin information of the function subtask;
writing a pin position list in the primary information of the input pin information and a pin position list in the primary information of the output pin information, wherein the pin position list comprises pin positions corresponding to each list, the pin positions corresponding to the input pins are used as secondary information of the input pin information, and the pin positions corresponding to the output pins are used as secondary information of the output pin information;
and sequentially encoding according to the input pin information and the output pin information, and adding a function description after encoding is completed to obtain a function and pin information corresponding to the function encoding.
In one embodiment, the program burning module is configured to:
and configuring the electronic equipment of the chip to execute a startup reading function, reading the stored function and pin information according to the execution thread of the task to be executed, and mapping the function and the pin information into the chip in sequence.
In a third aspect of the embodiments of the present invention, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method for configuring a chip input-output interface according to any one of the first aspect.
In a fourth aspect of the embodiment of the present invention, there is provided an electronic device, including:
a memory having a computer program stored thereon;
and a processor, configured to execute the computer program in the memory, so as to implement the steps of the method for configuring a chip input/output interface according to any one of the first aspect.
Advantageous effects
The invention provides a chip input/output interface configuration method, a device, a medium and electronic equipment. Compared with the prior art, the method has the following beneficial effects:
in response to the operation of the task to be executed, determining to complete function codes corresponding to a plurality of function subtasks corresponding to the task to be executed, and acquiring functions and pin information corresponding to each function code from a pre-configured function information model; according to the execution thread of the task to be executed, the functions and the pin information are mapped into the chip in sequence, and after the mapping is completed, the program burning is carried out on the integrated circuit functional blocks of the chip according to the function information in the functions and the pin information so as to complete the configuration of the input and output interfaces of the chip; and generating a burning completion report, displaying the burning completion report to a user, and executing a plurality of function subtasks according to the execution thread in response to the execution starting instruction. The method reduces the work of field personnel, facilitates the field engineering application, realizes the rapid deployment of tasks, accelerates the progress of engineering application, and reduces the equipment maintenance and update cost.
Drawings
Fig. 1 is a flowchart of a method for configuring a chip input/output interface according to the present invention.
Fig. 2 is a flowchart for implementing step S12 in fig. 1 according to the present invention.
Fig. 3 is a flowchart for implementing step S121 in fig. 2 according to the present invention.
Fig. 4 is a block diagram of a configuration device for a chip input/output interface according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides a technical solution: a method for configuring an input/output interface of a chip, the method comprising the steps of:
in step S11, in response to obtaining the operation of the task to be executed, determining to complete the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed, and obtaining the function and pin information corresponding to each function code from a pre-configured function information model, where the function subtask is a minimum task unit obtained by decoupling the task that can be executed by the chip, and each function code corresponding to the function subtask is obtained by encoding the pin number and pin position list of the function subtask;
In step S12, the function and pin information are mapped into the chip in sequence according to the execution thread of the task to be executed, and after the mapping is completed, the program burning is performed on the integrated circuit function block of the chip according to the function information in the function and pin information, so as to complete the configuration of the input/output interface of the chip;
in the embodiment of the disclosure, after mapping is completed, the device writes the received data into a storage medium of the device, and after analyzing the data, maps configuration data of each function to each integrated circuit functional block. The data analysis comprises extracting data, and judging the type of the extracted data, wherein the type of the data can comprise script data type and buffer data type, and the following operations are respectively executed according to the type of the data: under the condition that the type of the data is the script data type, analyzing the data into a program code by a script engine in a script writing mode and burning the program code; and under the condition that the type of the data is a cache type, caching the data to the target memory address through a caching mechanism in the HTTP protocol.
In step S13, after the programming is completed, a report of completion of the programming is generated, the report of completion of the programming is displayed to the user, and in response to the start instruction, the plurality of functional sub-tasks are executed according to the execution thread, so as to complete the task to be executed.
According to the technical scheme, in response to the operation of the task to be executed, the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed are determined, and the function and pin information corresponding to each function code is obtained from a pre-configured function information model; according to the execution thread of the task to be executed, the functions and the pin information are mapped into the chip in sequence, and after the mapping is completed, the program burning is carried out on the integrated circuit functional blocks of the chip according to the function information in the functions and the pin information so as to complete the configuration of the input and output interfaces of the chip; and generating a burning completion report, displaying the burning completion report to a user, and executing a plurality of function subtasks according to the execution thread in response to the execution starting instruction. The method reduces the work of field personnel, facilitates the field engineering application, realizes the rapid deployment of tasks, accelerates the progress of engineering application, and reduces the equipment maintenance and update cost.
In one embodiment, referring to fig. 2, in step S12, the step of mapping the function and pin information into the chip sequentially according to the execution thread of the task to be executed includes:
s121, writing the number of input pins and the number of output pins through a communication protocol of the chip, and after the number of input pins is successfully written and the number of output pins is successfully written, arranging the input pins according to the execution thread of the task to be executed to obtain a position list value of the input pins;
S122, performing stitch mapping on each input stitch according to the position list value, performing stitch mapping on an output stitch corresponding to each input stitch after the input stitch mapping is completed, and arranging and generating the position list value of the output stitch according to the position relation of the output stitch after the output stitch mapping is completed;
s123, according to the position list value of the input pin and the position list value of the output pin, the pin information corresponding to the function and the pin information is mapped into the chip.
In one embodiment, referring to fig. 3, in step S121, the step of arranging the input pin according to the execution thread of the task to be executed to obtain the position list value of the input pin includes:
s1211, arranging the input pins according to the execution thread of the task to be executed and the integrated circuit functional blocks of the chip, and determining whether different functional subtasks share the same integrated circuit functional block according to the integrated circuit functional blocks corresponding to the functional subtasks after the arrangement is completed;
s1212, under the condition that any different functional subtasks do not share the same integrated circuit functional block, obtaining the position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional blocks.
In one embodiment, the method further comprises:
s1213, determining whether different function subtasks shared by the same integrated circuit functional block exist or not according to the execution sequence of the different function subtasks shared by the same integrated circuit functional block in the execution thread of the task to be executed, wherein the execution sequence of the different function subtasks shared by the same integrated circuit functional block in the execution thread of the task to be executed represents that the different function subtasks shared by the same integrated circuit functional block exist to execute simultaneously, and determining that the different function subtasks shared by the same integrated circuit functional block exist to execute the conflict;
s1214, under the condition that execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, obtaining a position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional block; or,
s1215, under the condition that execution conflict exists among different function subtasks shared by the same integrated circuit functional block, determining the same integrated circuit functional block shared by different function subtasks as an integrated circuit functional block to be adjusted, replacing input pins corresponding to the function subtasks corresponding to the integrated circuit functional block to be adjusted on an idle integrated circuit functional block provided with the integrated circuit functional block to be adjusted in the chip until execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, and obtaining the position list value of the input pins according to the sequence of the input pins after the integrated circuit functional block is adjusted and the position relation of the corresponding integrated circuit functional block.
In one embodiment, in step S11, the step of determining, in response to obtaining the operation of the task to be executed, to complete the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed includes:
according to the operation of defining the number of input variables, the number of output variables and functions in the tool software by field personnel, generating a task to be executed;
responding to the operation of the task to be executed, and calling a preset task creation function according to the function, wherein the task creation function is used for decoupling the function so as to disassemble the function containing a plurality of function subtasks into a plurality of minimum task units, and the minimum task units and the function subtasks have a one-to-one correspondence;
and determining the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed according to the minimum task unit obtained after the function disassembly.
In one embodiment, the preconfigured function information model generates the function and pin information corresponding to each function code by:
for any function subtask, determining the number of input pins and the number of output pins corresponding to the function subtask;
Writing the number of the input pins as the first-level information of the input pin information of the function subtask, and writing the number of the output pins as the first-level information of the output pin information of the function subtask;
writing a pin position list in the primary information of the input pin information and a pin position list in the primary information of the output pin information, wherein the pin position list comprises pin positions corresponding to each list, the pin positions corresponding to the input pins are used as secondary information of the input pin information, and the pin positions corresponding to the output pins are used as secondary information of the output pin information;
and sequentially encoding according to the input pin information and the output pin information, and adding a function description after encoding is completed to obtain a function and pin information corresponding to the function encoding.
It can be understood that the primary information and the secondary information are obtained by writing the received data into the corresponding data items of the corresponding function subtasks according to the data structure of the model and according to each function.
In one embodiment, the step of sequentially mapping the function and pin information into the chip according to the execution thread of the task to be executed includes:
And configuring the electronic equipment of the chip to execute a startup reading function, reading the stored function and pin information according to the execution thread of the task to be executed, and mapping the function and the pin information into the chip in sequence.
The service application implementation of the technical scheme is completed through configuration, and hardware designer realizes hardware generalized design under similar or same application scenes, so that hardware development work is reduced, and hardware reliability is ensured. On the business organization, the programmer and the engineering staff work cooperatively, the programmer concentrates on programming, and the engineering staff concentrates on business application. The functional input and output are relocated in a configuration mode, and the output or input can be changed according to engineering needs only by the field personnel familiar with corresponding tool software, so that the work of the program personnel is lightened, the field engineering application is convenient, and the technical level requirement on the field personnel is reduced. For users, the rapid deployment of the service is realized, and the engineering application progress is quickened. The service configuration defines IO input and output, is convenient for equipment maintenance and service upgrading and changing, is convenient for field application, and reduces maintenance and updating cost of equipment and systems.
The embodiment of the invention also provides a device for configuring the input/output interface of the chip, referring to fig. 4, the device 400 includes:
a function subtask determining module 410, configured to determine, in response to obtaining an operation of a task to be executed, a function code corresponding to a plurality of function subtasks corresponding to the task to be executed, and obtain a function and pin information corresponding to each function code from a pre-configured function information model, where the function subtask is a minimum task unit obtained by decoupling a task that can be executed by the chip, and each function code corresponding to the function subtask is obtained by encoding a pin number and a pin position list of the function subtask;
the program burning module 420 is configured to map the functions and pin information into the chip in sequence according to the execution thread of the task to be executed, and after mapping is completed, perform program burning on the integrated circuit functional block of the chip according to the function information in the functions and pin information so as to complete the configuration of the chip input/output interface;
and the execution module 430 is configured to generate a recording completion report after the program recording is completed, display the recording completion report to a user, and execute the plurality of function subtasks according to the execution thread in response to an execution starting instruction so as to complete the task to be executed.
In one embodiment, the program burning module 420 is configured to:
writing the number of input pins and the number of output pins through a communication protocol of the chip, and after the number of the input pins is successfully written and the number of the output pins is successfully written, arranging the input pins according to the execution thread of the task to be executed to obtain a position list value of the input pins;
performing pin mapping on each input pin according to the position list value, performing pin mapping on an output pin corresponding to each input pin after the input pin mapping is completed, and arranging and generating the position list value of the output pin according to the position relation of the output pin after the output pin mapping is completed;
and mapping the pin information corresponding to the function and the pin information into the chip according to the position list value of the input pin and the position list value of the output pin.
In one embodiment, the program burning module 420 is configured to:
arranging the input pins according to the execution thread of the task to be executed and the integrated circuit functional blocks of the chip, and determining whether different functional subtasks share the same integrated circuit functional block according to the integrated circuit functional blocks corresponding to the functional subtasks after the arrangement is completed;
And under the condition that the fact that any different functional subtasks share the same integrated circuit functional block is determined, obtaining the position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional blocks.
In one embodiment, the program burning module 420 is configured to:
under the condition that the fact that different function subtasks share the same integrated circuit functional block is determined, determining whether different function subtasks shared by the same integrated circuit functional block have execution conflicts according to the execution sequence of different function subtasks shared by the same integrated circuit functional block in an execution thread of the task to be executed, wherein the execution sequence of the different function subtasks shared by the same integrated circuit functional block in the execution thread of the task to be executed characterizes that the different function subtasks shared by the same integrated circuit functional block have the execution conflicts under the condition that the different function subtasks shared by the same integrated circuit functional block are executed simultaneously;
under the condition that execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, obtaining a position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional block; or,
Under the condition that execution conflict exists among different function subtasks shared by the same integrated circuit functional block, the same integrated circuit functional block shared by different function subtasks is determined to be the integrated circuit functional block to be adjusted, input pins corresponding to the function subtasks corresponding to the integrated circuit functional block to be adjusted are replaced to an idle integrated circuit functional block with the integrated circuit functional block to be adjusted in the chip until execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, and a position list value of the input pins is obtained according to the sequence of input pins after the integrated circuit functional block is adjusted and the position relation of the corresponding integrated circuit functional block.
In one embodiment, the functional subtask determination module 410 is configured to:
according to the operation of defining the number of input variables, the number of output variables and functions in the tool software by field personnel, generating a task to be executed;
responding to the operation of the task to be executed, and calling a preset task creation function according to the function, wherein the task creation function is used for decoupling the function so as to disassemble the function containing a plurality of function subtasks into a plurality of minimum task units, and the minimum task units and the function subtasks have a one-to-one correspondence;
And determining the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed according to the minimum task unit obtained after the function disassembly.
In one embodiment, the preconfigured function information model generates the function and pin information corresponding to each function code by:
for any function subtask, determining the number of input pins and the number of output pins corresponding to the function subtask;
writing the number of the input pins as the first-level information of the input pin information of the function subtask, and writing the number of the output pins as the first-level information of the output pin information of the function subtask;
writing a pin position list in the primary information of the input pin information and a pin position list in the primary information of the output pin information, wherein the pin position list comprises pin positions corresponding to each list, the pin positions corresponding to the input pins are used as secondary information of the input pin information, and the pin positions corresponding to the output pins are used as secondary information of the output pin information;
and sequentially encoding according to the input pin information and the output pin information, and adding a function description after encoding is completed to obtain a function and pin information corresponding to the function encoding.
In one embodiment, the program burning module 420 is configured to:
and configuring the electronic equipment of the chip to execute a startup reading function, reading the stored function and pin information according to the execution thread of the task to be executed, and mapping the function and the pin information into the chip in sequence.
The embodiment of the present invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the method for configuring a chip input/output interface according to any one of the foregoing embodiments.
The embodiment of the invention also provides electronic equipment, which comprises:
a memory having a computer program stored thereon;
a processor, configured to execute the computer program in the memory, to implement the steps of the method for configuring a chip input/output interface according to any one of the foregoing embodiments.
With the above-described preferred embodiments according to the present application as a teaching, the related workers can make various changes and modifications without departing from the scope of the technical idea of the present application. The technical scope of the present application is not limited to the contents of the specification, and must be determined according to the scope of claims.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A method for configuring an input/output interface of a chip, the method comprising:
determining to complete function codes corresponding to a plurality of function subtasks corresponding to a task to be executed in response to the operation of the task to be executed, and acquiring functions and pin information corresponding to each function code from a pre-configured function information model, wherein the function subtasks are minimum task units obtained by decoupling the task which can be executed by the chip, and the function codes corresponding to each function subtask are obtained by coding the pin number and pin position list of the function subtask;
according to the execution thread of the task to be executed, mapping the functions and the pin information into the chip in sequence, and after mapping is completed, programming an integrated circuit functional block of the chip according to the function information in the functions and the pin information so as to complete the configuration of the chip input/output interface;
After the programming is completed, generating a programming completion report, displaying the programming completion report to a user, and responding to an execution starting instruction, executing the plurality of function subtasks according to the execution thread to complete the task to be executed;
the step of mapping the function and the pin information into the chip in sequence according to the execution thread of the task to be executed comprises the following steps:
writing the number of input pins and the number of output pins through a communication protocol of the chip, and after the number of the input pins is successfully written and the number of the output pins is successfully written, arranging the input pins according to the execution thread of the task to be executed to obtain a position list value of the input pins;
performing pin mapping on each input pin according to the position list value, performing pin mapping on an output pin corresponding to each input pin after the input pin mapping is completed, and arranging and generating the position list value of the output pin according to the position relation of the output pin after the output pin mapping is completed;
according to the position list value of the input pin and the position list value of the output pin, mapping the pin information corresponding to the function and the pin information into the chip;
The preconfigured function information model generates the corresponding function and pin information of each function code in the following manner:
for any function subtask, determining the number of input pins and the number of output pins corresponding to the function subtask;
writing the number of the input pins as the first-level information of the input pin information of the function subtask, and writing the number of the output pins as the first-level information of the output pin information of the function subtask;
writing a pin position list in the primary information of the input pin information and a pin position list in the primary information of the output pin information, wherein the pin position list comprises pin positions corresponding to each list, the pin positions corresponding to the input pins are used as secondary information of the input pin information, and the pin positions corresponding to the output pins are used as secondary information of the output pin information;
and sequentially encoding according to the input pin information and the output pin information, and adding a function description after encoding is completed to obtain a function and pin information corresponding to the function encoding.
2. The method according to claim 1, wherein the step of arranging the input pins according to the execution thread of the task to be executed to obtain the position list value of the input pins includes:
Arranging the input pins according to the execution thread of the task to be executed and the integrated circuit functional blocks of the chip, and determining whether different functional subtasks share the same integrated circuit functional block according to the integrated circuit functional blocks corresponding to the functional subtasks after the arrangement is completed;
and under the condition that the fact that any different functional subtasks share the same integrated circuit functional block is determined, obtaining the position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional blocks.
3. The method according to claim 2, wherein the method further comprises:
under the condition that the fact that different function subtasks share the same integrated circuit functional block is determined, determining whether different function subtasks shared by the same integrated circuit functional block have execution conflicts according to the execution sequence of different function subtasks shared by the same integrated circuit functional block in an execution thread of the task to be executed, wherein the execution sequence of the different function subtasks shared by the same integrated circuit functional block in the execution thread of the task to be executed characterizes that the different function subtasks shared by the same integrated circuit functional block have the execution conflicts under the condition that the different function subtasks shared by the same integrated circuit functional block are executed simultaneously;
Under the condition that execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, obtaining a position list value of the input pins according to the arranged sequence of the input pins and the position relation of the corresponding integrated circuit functional block; or,
under the condition that execution conflict exists among different function subtasks shared by the same integrated circuit functional block, the same integrated circuit functional block shared by different function subtasks is determined to be the integrated circuit functional block to be adjusted, input pins corresponding to the function subtasks corresponding to the integrated circuit functional block to be adjusted are replaced to an idle integrated circuit functional block with the integrated circuit functional block to be adjusted in the chip until execution conflict does not exist among different function subtasks shared by the same integrated circuit functional block, and a position list value of the input pins is obtained according to the sequence of input pins after the integrated circuit functional block is adjusted and the position relation of the corresponding integrated circuit functional block.
4. The method according to claim 1, wherein the step of determining, in response to obtaining the operation of the task to be performed, that the function codes corresponding to the plurality of function subtasks corresponding to the task to be performed are completed includes:
According to the operation of defining the number of input variables, the number of output variables and functions in the tool software by field personnel, generating a task to be executed;
responding to the operation of the task to be executed, and calling a preset task creation function according to the function, wherein the task creation function is used for decoupling the function so as to disassemble the function containing a plurality of function subtasks into a plurality of minimum task units, and the minimum task units and the function subtasks have a one-to-one correspondence;
and determining the function codes corresponding to the plurality of function subtasks corresponding to the task to be executed according to the minimum task unit obtained after the function disassembly.
5. The method according to any one of claims 1-4, wherein the step of sequentially mapping the function and pin information into the chip according to the execution thread of the task to be executed comprises:
and configuring the electronic equipment of the chip to execute a startup reading function, reading the stored function and pin information according to the execution thread of the task to be executed, and mapping the function and the pin information into the chip in sequence.
6. A chip input-output interface configuration apparatus, the apparatus comprising:
The function subtask determining module is configured to determine, in response to the operation of obtaining a task to be executed, function codes corresponding to a plurality of function subtasks corresponding to the task to be executed, and obtain functions and pin information corresponding to each function code from a pre-configured function information model, wherein the function subtasks are minimum task units obtained by decoupling the task which can be executed by the chip, and the function codes corresponding to each function subtask are obtained by coding the pin number and pin position list of the function subtask;
the program burning module is configured to map the functions and the pin information into the chip in sequence according to the execution thread of the task to be executed, and after mapping is completed, program burning is performed on the integrated circuit functional block of the chip according to the function information in the functions and the pin information so as to complete the configuration of the chip input/output interface;
the execution module is configured to generate a recording completion report after the program recording is completed, display the recording completion report to a user, respond to an execution starting instruction, execute the plurality of function subtasks according to the execution thread and complete the task to be executed;
The program burning module is configured to:
writing the number of input pins and the number of output pins through a communication protocol of the chip, and after the number of the input pins is successfully written and the number of the output pins is successfully written, arranging the input pins according to the execution thread of the task to be executed to obtain a position list value of the input pins;
performing pin mapping on each input pin according to the position list value, performing pin mapping on an output pin corresponding to each input pin after the input pin mapping is completed, and arranging and generating the position list value of the output pin according to the position relation of the output pin after the output pin mapping is completed;
according to the position list value of the input pin and the position list value of the output pin, mapping the pin information corresponding to the function and the pin information into the chip;
the preconfigured function information model generates the corresponding function and pin information of each function code in the following manner:
for any function subtask, determining the number of input pins and the number of output pins corresponding to the function subtask;
Writing the number of the input pins as the first-level information of the input pin information of the function subtask, and writing the number of the output pins as the first-level information of the output pin information of the function subtask;
writing a pin position list in the primary information of the input pin information and a pin position list in the primary information of the output pin information, wherein the pin position list comprises pin positions corresponding to each list, the pin positions corresponding to the input pins are used as secondary information of the input pin information, and the pin positions corresponding to the output pins are used as secondary information of the output pin information;
and sequentially encoding according to the input pin information and the output pin information, and adding a function description after encoding is completed to obtain a function and pin information corresponding to the function encoding.
7. A computer readable storage medium having stored thereon a computer program, characterized in that the program when executed by a processor realizes the steps of the chip input output interface configuration method of any of claims 1-5.
8. An electronic device, comprising:
A memory having a computer program stored thereon;
a processor for executing the computer program in the memory to implement the steps of the chip input output interface configuration method of any one of claims 1-5.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| EP3142032A1 (en) * | 2015-09-08 | 2017-03-15 | dSPACE digital signal processing and control engineering GmbH | Method for changing the configuration of a programmable logic component |
| CN109165025A (en) * | 2018-08-01 | 2019-01-08 | 京信通信系统（中国）有限公司 | The offline method for burn-recording of chip, device, system, computer storage medium and equipment |
| CN113986799A (en) * | 2021-11-12 | 2022-01-28 | 上海威固信息技术股份有限公司 | Digital pin dynamic multiplexing method and device based on FPGA |
| CN114610370A (en) * | 2021-12-10 | 2022-06-10 | 厦门码灵半导体技术有限公司 | Method for controlling chip pin multiplexing, electronic device and computer storage medium |
| CN115857976A (en) * | 2022-12-28 | 2023-03-28 | 龙芯中科(太原)技术有限公司 | Chip burning method, device, equipment and storage medium |
-
2023
- 2023-04-19 CN CN202310421071.8A patent/CN116126366B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| EP3142032A1 (en) * | 2015-09-08 | 2017-03-15 | dSPACE digital signal processing and control engineering GmbH | Method for changing the configuration of a programmable logic component |
| CN109165025A (en) * | 2018-08-01 | 2019-01-08 | 京信通信系统（中国）有限公司 | The offline method for burn-recording of chip, device, system, computer storage medium and equipment |
| CN113986799A (en) * | 2021-11-12 | 2022-01-28 | 上海威固信息技术股份有限公司 | Digital pin dynamic multiplexing method and device based on FPGA |
| CN114610370A (en) * | 2021-12-10 | 2022-06-10 | 厦门码灵半导体技术有限公司 | Method for controlling chip pin multiplexing, electronic device and computer storage medium |
| CN115857976A (en) * | 2022-12-28 | 2023-03-28 | 龙芯中科(太原)技术有限公司 | Chip burning method, device, equipment and storage medium |
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