CN219811188U - Bridge circuit, bridge circuit integrated device and silicon substrate - Google Patents
Bridge circuit, bridge circuit integrated device and silicon substrate Download PDFInfo
- Publication number
- CN219811188U CN219811188U CN202320412684.0U CN202320412684U CN219811188U CN 219811188 U CN219811188 U CN 219811188U CN 202320412684 U CN202320412684 U CN 202320412684U CN 219811188 U CN219811188 U CN 219811188U
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- module
- banyan network
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 16
- 239000010703 silicon Substances 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 title claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 128
- 240000003537 Ficus benghalensis Species 0.000 claims abstract description 126
- 238000004891 communication Methods 0.000 claims abstract description 27
- 238000007781 pre-processing Methods 0.000 claims description 30
- 230000008054 signal transmission Effects 0.000 claims description 10
- 238000013507 mapping Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000001228 spectrum Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Communication Control (AREA)
Abstract
The utility model discloses a bridge circuit, a bridge circuit integrated device and a silicon substrate, wherein the circuit comprises: the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module; the first signal interface module is used for receiving an input signal of the first chip; the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel; the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel; and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip. The utility model can support the use of various scenes and has high flexibility.
Description
Technical Field
The present utility model relates to the field of circuit technology, and in particular, to a bridge circuit, a bridge circuit integrated device, and a silicon substrate.
Background
In advanced packaging technology, a chip (chip) is connected with the chip through a bridging manner to realize parallel connection or common operation of the chips.
Currently, in advanced packaging, a silicon interposer (interposer) may be used to implement chip-to-chip signal bridging.
However, the bridge system adopted in the above cannot realize free communication between chips, for example, the bridge link in the bridge system is generally fixed or limited, resulting in a low degree of freedom of communication between chips, and the transmission channel in the bridge system generally does not have a signal processing circuit capable of adapting to various communication requirements, which also results in a reduction in the degree of freedom of communication between chips.
Disclosure of Invention
The utility model provides a bridge circuit, a bridge circuit integrated device and a silicon substrate, which are used for solving the problem that free communication between chips cannot be realized in the related art.
To achieve the above object, in a first aspect, the present utility model provides a bridge circuit, comprising:
the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module;
the first signal interface module is used for receiving an input signal of the first chip;
the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel;
the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip;
and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip.
In one possible implementation, the first signal interface module includes n first signal interfaces, the signal processing module includes n signal processing circuits, and the second signal interface module includes n second signal interfaces, where n=2 k K is a positive integer greater than 1;
the n first signal interfaces are electrically connected with n input ends corresponding to the n signal processing circuits, wherein the n first signal interfaces are in one-to-one correspondence with the n input ends corresponding to the n signal processing circuits;
n output ends corresponding to the n signal processing circuits are electrically connected with n input ends corresponding to the Banyan network modules, wherein the n signal processing circuits are in one-to-one correspondence with the n input ends corresponding to the Banyan network modules;
and n output ends corresponding to the Banyan network modules are electrically connected with n second signal interfaces, wherein the n output ends corresponding to the Banyan network modules are in one-to-one correspondence with the n second signal interfaces.
In one possible implementation, the signal processing module includes a first channel selection sub-circuit, an interface pre-processing sub-circuit, a signal processing sub-circuit, and a second channel selection sub-circuit;
the interface preprocessing sub-circuit is electrically connected with the first signal interface module and is used for receiving an input signal transmitted by the first signal interface module and preprocessing the input signal to obtain a preprocessed input signal;
the first channel selection sub-circuit is electrically connected with the interface preprocessing sub-circuit and is used for receiving the preprocessed input signals transmitted by the interface preprocessing sub-circuit through a first preset channel;
the signal processing sub-circuit is electrically connected with the first channel selection sub-circuit and is used for receiving the preprocessed input signal transmitted by the first channel selection sub-circuit and processing the preprocessed input signal to obtain a processed input signal;
and the second channel selection sub-circuit is electrically connected with the signal processing sub-circuit and is used for receiving the processed input signal through a second preset channel and transmitting the processed input signal to the second signal interface module.
In one possible implementation, the signal processing subcircuit includes a signal relay processing circuit.
In one possible implementation, the signal processing subcircuit includes at least one of a general purpose signal circuit, a signal transmission dedicated circuit, and a signal receiving circuit.
In one possible implementation, the Banyan network module includes k×2 k-1 A plurality of switching circuits k.times.2 k-1 The switching circuits are electrically connected to form a network structure of n inputs and n outputs.
In one possible implementation, the switching circuit includes a Bar mode of operation and a Cross mode of operation.
In one possible implementation, the n output terminals corresponding to the n second channel selection sub-circuits are electrically connected to the n input terminals corresponding to the Banyan network module, where the n second channel selection sub-circuits are in one-to-one correspondence with the n input terminals corresponding to the Banyan network module.
In a second aspect, an embodiment of the present utility model provides a bridge circuit integrated device, including a plurality of bridge circuits as defined in any one of the above.
In a third aspect, an embodiment of the present utility model provides a silicon substrate, including at least a bridge circuit as defined in any one of the above.
The embodiment of the utility model provides a bridge circuit, a bridge circuit integrated device and a silicon substrate, comprising: the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module; the first signal interface module is used for receiving an input signal of the first chip; the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel; the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip; and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip. According to the utility model, the free communication between the first chip and the second chip can be realized only by setting the network channel between the first chip and the second chip through the Banyan network module, so that the use of various scenes can be supported, and the flexibility is high. In addition, the signal processing module is arranged in the bridge circuit, so that the bridge circuit can adapt to various communication requirements, and free communication between the first chip and the second chip is realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model, are incorporated in and constitute a part of this specification. The drawings and their description are illustrative of the utility model and are not to be construed as unduly limiting the utility model. In the drawings:
fig. 1 is an application scenario diagram of a bridge circuit according to an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of a bridge circuit according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a switching circuit according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of a bridge circuit of a 4 interface according to an embodiment of the present utility model;
fig. 5 is a schematic structural diagram of an 8-interface bridge circuit according to an embodiment of the present utility model;
fig. 6 is a schematic structural diagram of a 16-interface bridge circuit according to an embodiment of the present utility model;
fig. 7 is a schematic structural diagram of a 32-interface bridge circuit according to an embodiment of the present utility model;
fig. 8 is a schematic diagram of a signal processing circuit according to an embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein.
It should be understood that, in various embodiments of the present utility model, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present utility model.
It should be understood that in the present utility model, "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present utility model, "plurality" means two or more. "and/or" is merely an association relationship describing an association object, and means that three relationships may exist, for example, and/or B may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and C", "comprising A, B, C" means that all three of A, B, C comprise, "comprising A, B or C" means that one of the three comprises A, B, C, and "comprising A, B and/or C" means that any 1 or any 2 or 3 of the three comprises A, B, C.
It should be understood that in the present utility model, "B corresponding to a", "a corresponding to B", or "B corresponding to a" means that B is associated with a, from which B can be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information. The matching of A and B is that the similarity of A and B is larger than or equal to a preset threshold value.
As used herein, "if" may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context.
The technical scheme of the utility model is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
For the purpose of making the objects, technical solutions and advantages of the present utility model more apparent, the following description will be made by way of specific embodiments with reference to the accompanying drawings.
As shown in fig. 1, the present utility model provides a bridge circuit, which can be applied to the application scenario shown in fig. 1. Specifically, the application scenario includes two chips (chip) and the bridge circuit provided by the present utility model, where the two chips are a first chip and a second chip respectively. The A side of the bridge circuit is electrically connected with the first chip, and the B side of the bridge circuit is electrically connected with the second chip. The A side and the B side of the bridge circuit are two interfaces of the bridge circuit. By the bridge circuit, communication between the first chip and the second chip can be realized.
The first chip and the second chip may be a single chip or a chip obtained by integrating a plurality of chips. In addition, the types of the first chip and the second chip are not particularly limited, and may be set according to different requirements.
In one embodiment, as shown in fig. 2, a bridge circuit is provided and applied to the scenario in fig. 1, where the a side of the bridge circuit is a first signal interface module, and the B side of the bridge circuit is a second signal interface module, and the bridge circuit includes:
the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module;
the first signal interface module is used for receiving an input signal of the first chip;
the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel;
the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip;
and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip.
Wherein, the first signal interface module and the second signal interface module can be configured with control interfaces, such as I2C, SPI and other control interfaces.
The first signal interface module and the second signal interface module are respectively provided with an I2C interface, so that communication between the pins a and b of the first chip and the pins C and d of the second chip is realized, the pins a and b of the first chip can be electrically connected with the I2C interface through the first signal interface module, that is, the I2C interface of the first signal interface module receives signals of the pins a and b of the first chip as input signals, and then transmits the input signals to the signal processing module for processing, so that processed input signals are obtained, and the signal processing module also transmits the processed input signals to the Banyan network module through a preset channel, so that the Banyan network module transmits the processed input signals to the I2C interface of the second signal interface module through the Banyan network channel. And finally, the I2C interface of the second signal interface module transmits the processed input signals to pins C and d of the second chip, so that the communication of the two chips is completed.
After power up, external systems such as MCU (Microcontroller Unit, micro control unit) etc. can configure the bridge circuit through I2C, SPI or JTAG etc.; the configuration information may be written to an OTP (One Time Programmable) or an EFUSE (electrically programmable fuse) first, and after the system is powered on, the configuration information is read from the OTP or EFUSE by the power-on initialization circuit and configured into the bridge circuit.
The Banyan network module is a butterfly-shaped interconnection (exchange) network, and can realize non-blocking routing under specific conditions. Broadly, a switching network exists where there are multiple source data and multiple destination data exchanges. Such as ATM (Asynchronous Transfer Mode ) switched networks in communication networks, ethernet switched networks, FPGA (Field Programmable Gate Array ) chip interconnect networks in electronic circuits, etc., all belong to switched networks in the respective fields.
Common switching network structures include Crossbar networks, banyan networks, and Benes networks, and the Banyan network module of the present utility model may be replaced with other networks as described above.
Each node in the Crossbar network, the Banyan network, and the Benes network is called a switch, i.e., a switching circuit. Each switch has two modes of operation, namely "BAR" and "CROSS" modes of operation. Referring to FIG. 3, the "BAR" mode of operation represents a pass-through state in which a0 communicates with b0 and a1 communicates with b 1; the "CROSS" mode of operation refers to the switching state in which a0 communicates with b1 and a1 communicates with b 0.
The switching network structure of the present utility model comprises n inputs and n outputs, and the bridge circuit comprises:
the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module, wherein the first signal interface module comprises n first signal interfaces, the signal processing module comprises n signal processing circuits, the second signal interface module comprises n second signal interfaces, and n=2 k K is a positive integer greater than 1;
the n first signal interfaces are electrically connected with n input ends corresponding to the n signal processing circuits, wherein the n first signal interfaces are in one-to-one correspondence with the n input ends corresponding to the n signal processing circuits;
n output ends corresponding to the n signal processing circuits are electrically connected with n input ends corresponding to the Banyan network modules, wherein the n signal processing circuits are in one-to-one correspondence with the n input ends corresponding to the Banyan network modules;
and n output ends corresponding to the Banyan network modules are electrically connected with n second signal interfaces, wherein the n output ends corresponding to the Banyan network modules are in one-to-one correspondence with the n second signal interfaces.
The first signal interface module and the second signal interface module are respectively provided with an I2C interface, so that the pins a and b of the first chip and the pins C and d of the second chip can be communicated, the pins a and b of the first chip can be electrically connected with two first signal interfaces of n first interface signals, that is, the two first signal interfaces receive signals of the pins a and b of the first chip as input signals, then the input signals are processed through two signal processing circuits, the processed input signals are obtained, and the processed input signals are transmitted to two input ends of the Banyan network module through a preset channel. The two input ends of the Banyan network module receive the processed input signals, so that the Banyan network module transmits the processed input signals to the two second signal interfaces of the n second signal interfaces through the two output ends of the Banyan network module by the Banyan network channel. Finally, the two second signal interfaces transmit the processed input signals to pins c and d of the second chip, so that the communication of the two chips is completed.
In addition, since the Banyan network module has n inputs and n outputs no matter any network is adopted, each node in the network is a switch circuit, and the network comprises k×2 k-1 A plurality of switching circuits, and k is 2 k-1 The switching circuits are electrically connected to form a network structure of n inputs and n outputs.
The Banyan network module in the present utility model is exemplified by a Banyan network, which includes n inputs and n outputs, and in the case where n=4, the bridge circuit of the present utility model is shown in fig. 4. The bridge circuit includes 4 first signal interfaces A0, A1, A2, and A3,4 signal processing circuits, one 4-signal Banyan network, and 4 second signal interfaces B0, B1, B2, and B3. Wherein the 4-signal Banyan network includes 4 switching circuits.
In the case where the switching network structure includes a Banyan network including n inputs and n outputs, and n=8, the bridge circuit of the present utility model is shown in fig. 5. The bridge circuit comprises 8 first signal interfaces A0-A7,8 signal processing circuits, an 8 signal Banyan network, and 8 second signal interfaces B0-B7. Wherein the 8-signal Banyan network includes 12 switching circuits.
In the case where the switching network structure includes a Banyan network including n inputs and n outputs, and n=16, the bridge circuit of the present utility model is shown in fig. 6. The bridge circuit comprises 16 first signal interfaces A0-a15, 16 signal processing circuits, a 16 signal Banyan network, and 16 second signal interfaces B0-B15. Wherein the 16 signal Banyan network includes 32 switching circuits.
In the case where the switching network structure includes a Banyan network including n inputs and n outputs, and n=32, the bridge circuit of the present utility model is shown in fig. 7. The bridge circuit comprises 32 first signal interfaces A0-a31, 32 signal processing circuits, a 32 signal Banyan network, and 32 second signal interfaces B0-B31. Wherein the 32-signal Banyan network comprises 80 switching circuits.
It should be noted that the above 4-signal Banyan network means that the Banyan network includes 4 input interfaces and 4 output interfaces. The 8-signal Banyan network, the 16-signal Banyan network, and the 32-signal Banyan network are similar in meaning to the 4-signal Banyan network, and are not described in detail herein.
The bridge circuits shown in fig. 4-7 can be used alone or integrated together to support multiple scenarios, which is beneficial to reducing development cycle.
The signal processing module includes a first channel selection sub-circuit, an interface preprocessing sub-circuit, a signal processing sub-circuit and a second channel selection sub-circuit, as shown in fig. 8;
the interface preprocessing sub-circuit is electrically connected with the first signal interface module and is used for receiving an input signal transmitted by the first signal interface module and preprocessing the input signal to obtain a preprocessed input signal;
the first channel selection sub-circuit is electrically connected with the interface preprocessing sub-circuit and is used for receiving the preprocessed input signals transmitted by the interface preprocessing sub-circuit through a first preset channel;
the signal processing sub-circuit is electrically connected with the first channel selection sub-circuit and is used for receiving the preprocessed input signal transmitted by the first channel selection sub-circuit and processing the preprocessed input signal to obtain a processed input signal;
and the second channel selection sub-circuit is electrically connected with the signal processing sub-circuit and is used for receiving the processed input signal through a second preset channel and transmitting the processed input signal to the Banyan network module.
Specifically, n input ends corresponding to the n interface preprocessing sub-circuits are electrically connected with n first signal interfaces, n output ends corresponding to the n second channel selection sub-circuits are electrically connected with n input ends corresponding to the Banyan network modules, wherein n input ends corresponding to the n interface preprocessing sub-circuits are in one-to-one correspondence with n first signal interfaces, and n second channel selection sub-circuits are in one-to-one correspondence with n input ends corresponding to the Banyan network modules.
The first channel selection sub-circuit and the second channel selection sub-circuit can realize the processing mode of the preprocessed input signals through the configuration of a switch or other parameters.
Specifically, taking the first channel selection sub-circuit and the second channel selection sub-circuit as switch circuits as examples, when the signal processing module receives an input signal, the interface preprocessing sub-circuit performs preprocessing, such as amplification, gain processing, and the like, on the input signal to obtain a preprocessed input signal. The preprocessed input signal is transmitted to the signal processing sub-circuit through a configured first preset channel, wherein the configured first preset channel can be realized by controlling the switching of the first channel selection circuit.
After the preprocessed input signal is transmitted to the signal processing sub-circuit, the preprocessed input signal is processed, such as signal spectrum pre-emphasis processing, signal gain processing, and the like, to obtain a processed input signal. And then, the processed input signal is transmitted to the Banyan network module through the configured second preset channel. The configured second preset channel can be realized by controlling the switch of the second channel selection circuit.
Wherein the signal processing sub-circuit comprises a signal relay processing circuit, or the signal processing sub-circuit comprises at least one of a general-purpose signal circuit, a signal transmission dedicated circuit, and a signal receiving circuit. The general purpose signal circuit may be used for configuration of driving capability, pull-up and pull-down resistors, or serial resistors. The signal transmission dedicated circuit can be used for signal spectrum pre-emphasis processing and signal gain processing. The signal receiving circuit may be used for signal spectrum equalization, gain and delay processing. The signal relay processing circuit can be used for signal transmission, supports one-to-one and one-to-many signal transmission, and can rapidly transmit digital information. The interface preprocessing sub-circuit may be used to preprocess the signal, such as amplifying, gain processing, etc.
Specifically, taking the first channel selection sub-circuit and the second channel selection sub-circuit as switch circuits as examples, when the signal processing sub-circuit includes a general signal circuit, a signal transmission dedicated circuit and a signal receiving circuit, the switch of the first channel selection sub-circuit can be switched to enable the preprocessed input signal to pass through any one, any two or three of the general signal circuit, the signal transmission dedicated circuit and the signal receiving circuit so as to obtain the processed input signal, and then the switch of the second channel selection sub-circuit is switched to enable the processed input signal to be transmitted to the Banyan network module.
The embodiment of the utility model provides a bridge circuit, which comprises: the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module; the first signal interface module is used for receiving an input signal of the first chip; the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel; the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip; and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip. According to the utility model, the free communication between the first chip and the second chip can be realized only by setting the network channel between the first chip and the second chip through the Banyan network module, so that the use of various scenes can be supported, and the flexibility is high. In addition, the signal processing module is arranged in the bridge circuit, so that the bridge circuit can adapt to various communication requirements, and free communication between the first chip and the second chip is realized.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present utility model.
The following are device embodiments of the utility model, for details not described in detail therein, reference may be made to the corresponding method embodiments described above.
In an embodiment, the present utility model further provides a bridge circuit integrated device, wherein the bridge circuit integrated device includes a plurality of bridge circuits as defined in any one of the above.
Multiple bridge circuits may be integrated on the bridge circuit integrated device, and the number of interfaces of the multiple bridge circuits may be the same or different. For example, 2 bridge circuits are integrated in the bridge circuit integrated device, one bridge circuit is 4 interfaces, and the other bridge circuit is 16 interfaces. Alternatively, both bridge circuits are 16 interfaces. The bridge circuit integrated device may perform the setting of the bridge circuit number and the bridge circuit interface according to specific requirements, which is not limited herein.
In addition, a plurality of bridge circuits integrated on the bridge circuit integrated device can be connected in series and parallel to realize more complex signal connection and improve communication efficiency.
Specifically, a bridge circuit includes:
the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module;
the first signal interface module is used for receiving an input signal of the first chip;
the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel;
the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip;
and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip.
In one possible implementation, the first signal interface module includes n first signal interfaces, the signal processing module includes n signal processing circuits, and the second signal interface module includes n second signal interfaces, where n=2 k K is a positive integer greater than 1;
the n first signal interfaces are electrically connected with n input ends corresponding to the n signal processing circuits, wherein the n first signal interfaces are in one-to-one correspondence with the n input ends corresponding to the n signal processing circuits;
n output ends corresponding to the n signal processing circuits are electrically connected with n input ends corresponding to the Banyan network modules, wherein the n signal processing circuits are in one-to-one correspondence with the n input ends corresponding to the Banyan network modules;
and n output ends corresponding to the Banyan network modules are electrically connected with n second signal interfaces, wherein the n output ends corresponding to the Banyan network modules are in one-to-one correspondence with the n second signal interfaces.
In one possible implementation, the signal processing module includes a first channel selection sub-circuit, an interface pre-processing sub-circuit, a signal processing sub-circuit, and a second channel selection sub-circuit;
the interface preprocessing sub-circuit is electrically connected with the first signal interface module and is used for receiving an input signal transmitted by the first signal interface module and preprocessing the input signal to obtain a preprocessed input signal;
the first channel selection sub-circuit is electrically connected with the interface preprocessing sub-circuit and is used for receiving the preprocessed input signals transmitted by the interface preprocessing sub-circuit through a first preset channel;
the signal processing sub-circuit is electrically connected with the first channel selection sub-circuit and is used for receiving the preprocessed input signal transmitted by the first channel selection sub-circuit and processing the preprocessed input signal to obtain a processed input signal;
and the second channel selection sub-circuit is electrically connected with the signal processing sub-circuit and is used for receiving the processed input signal through a second preset channel and transmitting the processed input signal to the second signal interface module.
In one possible implementation, the signal processing subcircuit includes a signal relay processing circuit.
In one possible implementation, the signal processing subcircuit includes at least one of a general purpose signal circuit, a signal transmission dedicated circuit, and a signal receiving circuit.
In one possible implementation, the Banyan network module includes k×2 k-1 A plurality of switching circuits k.times.2 k-1 The switching circuits are electrically connected to form a network structure of n inputs and n outputs.
In one possible implementation, the switching circuit includes a Bar mode of operation and a Cross mode of operation.
In one possible implementation, the n output terminals corresponding to the n second channel selection sub-circuits are electrically connected to the n input terminals corresponding to the Banyan network module, where the n second channel selection sub-circuits are in one-to-one correspondence with the n input terminals corresponding to the Banyan network module.
In an embodiment, the present utility model further provides a silicon substrate, wherein the silicon substrate at least includes the bridge circuit as set forth in any one of the above.
Since the silicon substrate is provided with chips, and chips are added according to requirements when the silicon substrate is designed, the communication between the chips on the silicon substrate is realized, the connection of signals between the chips is required to be performed through bridge circuits, and the number of the bridge circuits and the types of the bridge circuits (based on the division of the number of interfaces) are adjusted according to the design of the silicon substrate, which is not particularly limited herein.
By arranging the bridge circuit on the silicon substrate, not only can the random mapping of signals between two chips be realized, but also the communication between a plurality of chips and various chips with different types can be satisfied.
Specifically, a bridge circuit includes:
the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module;
the first signal interface module is used for receiving an input signal of the first chip;
the signal processing module is electrically connected with the first signal interface module and is used for receiving an input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel;
the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip;
and the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip.
In one possible implementation, the first signal interface module includes n first signal interfaces, the signal processing module includes n signal processing circuits, and the second signal interface module includes n second signal interfaces, where n=2 k K is a positive integer greater than 1;
the n first signal interfaces are electrically connected with n input ends corresponding to the n signal processing circuits, wherein the n first signal interfaces are in one-to-one correspondence with the n input ends corresponding to the n signal processing circuits;
n output ends corresponding to the n signal processing circuits are electrically connected with n input ends corresponding to the Banyan network modules, wherein the n signal processing circuits are in one-to-one correspondence with the n input ends corresponding to the Banyan network modules;
and n output ends corresponding to the Banyan network modules are electrically connected with n second signal interfaces, wherein the n output ends corresponding to the Banyan network modules are in one-to-one correspondence with the n second signal interfaces.
In one possible implementation, the signal processing module includes a first channel selection sub-circuit, an interface pre-processing sub-circuit, a signal processing sub-circuit, and a second channel selection sub-circuit;
the interface preprocessing sub-circuit is electrically connected with the first signal interface module and is used for receiving an input signal transmitted by the first signal interface module and preprocessing the input signal to obtain a preprocessed input signal;
the first channel selection sub-circuit is electrically connected with the interface preprocessing sub-circuit and is used for receiving the preprocessed input signals transmitted by the interface preprocessing sub-circuit through a first preset channel;
the signal processing sub-circuit is electrically connected with the first channel selection sub-circuit and is used for receiving the preprocessed input signal transmitted by the first channel selection sub-circuit and processing the preprocessed input signal to obtain a processed input signal;
and the second channel selection sub-circuit is electrically connected with the signal processing sub-circuit and is used for receiving the processed input signal through a second preset channel and transmitting the processed input signal to the second signal interface module.
In one possible implementation, the signal processing subcircuit includes a signal relay processing circuit.
In one possible implementation, the signal processing subcircuit includes at least one of a general purpose signal circuit, a signal transmission dedicated circuit, and a signal receiving circuit.
In one possible implementation, the Banyan network module includes k×2 k-1 A plurality of switching circuits k.times.2 k-1 The switching circuits are electrically connected to form a network structure of n inputs and n outputs.
In one possible implementation, the switching circuit includes a Bar mode of operation and a Cross mode of operation.
In one possible implementation, the n output terminals corresponding to the n second channel selection sub-circuits are electrically connected to the n input terminals corresponding to the Banyan network module, where the n second channel selection sub-circuits are in one-to-one correspondence with the n input terminals corresponding to the Banyan network module.
The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and they should be included in the protection scope of the present utility model.
Claims (10)
1. A bridge circuit, comprising:
the system comprises a first signal interface module, a signal processing module, a Banyan network module and a second signal interface module;
the first signal interface module is used for receiving an input signal of the first chip;
the signal processing module is electrically connected with the first signal interface module and is used for receiving the input signal, processing the input signal to obtain a processed input signal and transmitting the processed input signal to the Banyan network module through a preset channel;
the Banyan network module is electrically connected with the signal processing module and is used for receiving the processed input signal and transmitting the processed input signal to the second signal interface module through a preset Banyan network channel, wherein the preset Banyan network channel is one network channel in the Banyan network module and is used for representing the signal mapping relation between the first chip and the second chip;
the second signal interface module is electrically connected with the Banyan network module and is used for transmitting the processed input signals to the second chip so as to realize communication between the first chip and the second chip.
2. The bridge circuit of claim 1, wherein the first one ofThe signal interface module comprises n first signal interfaces, the signal processing module comprises n signal processing circuits, and the second signal interface module comprises n second signal interfaces, wherein n=2 k K is a positive integer greater than 1;
the n first signal interfaces are electrically connected with n input ends corresponding to the n signal processing circuits, wherein the n first signal interfaces are in one-to-one correspondence with the n input ends corresponding to the n signal processing circuits;
the n output ends corresponding to the n signal processing circuits are electrically connected with the n input ends corresponding to the Banyan network module, wherein the n signal processing circuits are in one-to-one correspondence with the n input ends corresponding to the Banyan network module;
and n output ends corresponding to the Banyan network modules are electrically connected with the n second signal interfaces, wherein the n output ends corresponding to the Banyan network modules are in one-to-one correspondence with the n second signal interfaces.
3. The bridge circuit of claim 2, wherein the signal processing module comprises a first channel selection sub-circuit, an interface pre-processing sub-circuit, a signal processing sub-circuit, and a second channel selection sub-circuit;
the interface preprocessing sub-circuit is electrically connected with the first signal interface module and is used for receiving the input signal transmitted by the first signal interface module and preprocessing the input signal to obtain a preprocessed input signal;
the first channel selection sub-circuit is electrically connected with the interface preprocessing sub-circuit and is used for receiving the preprocessed input signals transmitted by the interface preprocessing sub-circuit through a first preset channel;
the signal processing sub-circuit is electrically connected with the first channel selection sub-circuit and is used for receiving the preprocessed input signal transmitted by the first channel selection sub-circuit and processing the preprocessed input signal to obtain a processed input signal;
the second channel selection sub-circuit is electrically connected with the signal processing sub-circuit and is used for receiving the processed input signal through a second preset channel and transmitting the processed input signal to the second signal interface module.
4. A bridge circuit as claimed in claim 3, wherein the signal processing sub-circuit comprises a signal relay processing circuit.
5. A bridge circuit as claimed in claim 3, wherein the signal processing sub-circuit comprises at least one of a general purpose signal circuit, a signal transmission dedicated circuit and a signal receiving circuit.
6. The bridge circuit of claim 2, wherein said Banyan network module comprises k x 2 k-1 A plurality of switching circuits, k is 2 k-1 The switching circuits are electrically connected to form a network structure of n inputs and n outputs.
7. The bridge circuit of claim 6, wherein the switching circuit comprises a Bar mode of operation and a Cross mode of operation.
8. The bridge circuit of claim 3, wherein n outputs of n second channel select sub-circuits are electrically connected to n inputs of said Banyan network module, wherein said n second channel select sub-circuits are in one-to-one correspondence with n inputs of said Banyan network module.
9. A bridge circuit integrated device comprising a plurality of bridge circuits according to any one of claims 1-8.
10. A silicon substrate comprising at least a bridge circuit according to any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320412684.0U CN219811188U (en) | 2023-02-24 | 2023-02-24 | Bridge circuit, bridge circuit integrated device and silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320412684.0U CN219811188U (en) | 2023-02-24 | 2023-02-24 | Bridge circuit, bridge circuit integrated device and silicon substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219811188U true CN219811188U (en) | 2023-10-10 |
Family
ID=88211902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320412684.0U Active CN219811188U (en) | 2023-02-24 | 2023-02-24 | Bridge circuit, bridge circuit integrated device and silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219811188U (en) |
-
2023
- 2023-02-24 CN CN202320412684.0U patent/CN219811188U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bainbridge et al. | Chain: a delay-insensitive chip area interconnect | |
| US5909427A (en) | Redundant switch system and method of operation | |
| EP2849079B1 (en) | Universal SPI (Serial Peripheral Interface) | |
| CN106252325A (en) | The hybrid redundancy scheme of interconnection between tube core in Multi-chip packages | |
| CN1519573B (en) | Integrated circuit device including scan test circuit and methods of testing same | |
| CN102301363A (en) | Data processsing node, system and method | |
| CN107645457A (en) | A kind of PCIe switch system and method | |
| CN109150645B (en) | Test method and system for switching chip | |
| CN114328318B (en) | DMA controller for direct equipment interconnection for microcontroller and interconnection control method | |
| CN214225912U (en) | Serial port level internal selection switching equipment and system | |
| WO2024120267A1 (en) | Multi-interface conversion device and vehicle | |
| US7206889B2 (en) | Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes | |
| US11343065B2 (en) | Serial bidirectional communication circuit and method thereof | |
| CN219811188U (en) | Bridge circuit, bridge circuit integrated device and silicon substrate | |
| CN116340245A (en) | Bridge circuit, bridge circuit integrated device and silicon substrate | |
| CN112069106A (en) | FPGA-based multi-server PECI link control system | |
| KR100745674B1 (en) | Packet processing apparatus and method with multiple switching ports support structure and packet processing system using the same | |
| US6700872B1 (en) | Method and system for testing a utopia network element | |
| EP0594198B1 (en) | Crossbar switch for synthesizing multiple backplane interconnect topologies in communications system | |
| CN103270490B (en) | Network processing unit and the method being connected with external network coprocessor thereof | |
| US6542952B1 (en) | PCI computer system having a transition module and method of operation | |
| CN113688091A (en) | Method and system for realizing RapidIO dynamic enumeration process based on Tsi721 | |
| CN108363672B (en) | Electronic device and electronic system | |
| US7426205B2 (en) | No-addressing modular-assembly Ethernet switch with a G.Link | |
| CN115134311B (en) | RapidIO endpoint controller and endpoint equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |