CN113985104A - Circuit and method for detecting voltage and current signals in chip - Google Patents
Circuit and method for detecting voltage and current signals in chip Download PDFInfo
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- CN113985104A CN113985104A CN202111253651.8A CN202111253651A CN113985104A CN 113985104 A CN113985104 A CN 113985104A CN 202111253651 A CN202111253651 A CN 202111253651A CN 113985104 A CN113985104 A CN 113985104A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
Abstract
The invention discloses an on-chip voltage and current detection circuit, which comprises a self-biased operational amplifier, a current detection circuit and a current detection circuit, wherein the self-biased operational amplifier is used for carrying out multi-stage gain amplification on an analog signal to be detected; the switch group and the control logic unit are used for controlling the on-off of the switch group according to the type of the analog signal to be detected; the static protection unit is used for eliminating the influence of static outside the chip on the detection circuit inside the chip; and the current limiting unit is used for limiting the current flowing into the detection circuit and protecting the circuit from being damaged. The invention can detect the voltage signal and the current signal in the chip in the same circuit, saves the area of the chip occupied by the circuit and has high detection precision.
Description
Technical Field
The invention relates to the technical field of chip internal power management, in particular to a circuit and a method for detecting voltage and current signals in a chip.
Background
As chip designs become more complex, the observable requirements for voltage current signals inside the chip become more stringent. By comparing the actual observed signal state with the expected state, it can be determined whether each circuit inside the chip is expected to operate as designed. If the work is not expected according to the design, the position where the problem point appears can be quickly locked, the time for troubleshooting the problem point is reduced, the risk of the problem of the whole chip is reduced, and the cost of changing the edition of the chip into the tape-out tape-out tape-.
Since the voltage and current values inside the chip are generally low, and the voltage value is usually only 2.8V, the requirement on the detection accuracy is high. In addition, a common detection method is to set detection circuits for voltage signals and current signals respectively, so that the chip area is occupied.
Disclosure of Invention
The invention aims to solve the technical problem of detecting voltage and current signals inside a chip. The invention aims to provide a circuit and a method for detecting voltage and current signals in a chip, which can detect the voltage signals and the current signals under the same circuit frame. The detection precision is high, and the occupied area of the chip is saved.
The invention is realized by the following technical scheme:
the invention provides a circuit for detecting voltage and current signals in a chip, which comprises a signal selection unit, a self-biased operational amplifier, a switch group, a control logic unit, an electrostatic protection unit and a current limiting unit, wherein the signal selection unit is used for selecting analog signals accessed into the detection circuit, the signal selection unit can be composed of a plurality of groups of switches connected in parallel, and the signal selection unit can only select one analog signal to be detected to flow into the detection circuit at one time;
the self-bias operational amplifier is used for accurately tracking the analog signal to be detected;
the switch group and control logic unit comprises A, B, C, D four groups of switches and is used for controlling the switch group to be switched on or switched off according to the test requirement;
the static protection unit comprises a primary static protection unit and a secondary static protection unit and is used for eliminating the influence of static outside the chip on the detection circuit inside the chip and preventing the detection circuit from being invalid;
and the current limiting unit is used for limiting the current flowing into the detection circuit and protecting the circuit from being damaged. The current limiting unit may be a resistor.
In a second aspect, the present invention further provides a method for detecting a voltage and current signal in a chip, including the following steps:
when the signal to be detected is a direct-current voltage signal, the path where the signal is located is enabled through the signal selection unit, other paths are kept in a closed state, then the switch unit A, B, D is in a closed state through the switch unit group and the control logic unit, the switch unit C is in an open state, and at the moment, the circuit is in an operational amplifier working mode; in addition, the switch unit C can be in a closed state and the switch unit A, B, D can be in an open state through the switch unit group and the control logic unit, at this time, the circuit is in a direct output working mode, finally, a signal is output from the pad, and the direct-current voltage value is observed by external observation equipment;
when the signal to be detected is an alternating voltage signal, firstly enabling a channel where the signal is located through the signal selection unit, keeping other channels in a closed state, then enabling the switch unit A, B, D to be in a closed state through the switch unit group and the control logic unit, enabling the switch unit C to be in an open state, enabling the circuit to be in an operational amplifier working mode, finally outputting the signal from the bonding pad, and observing an alternating voltage value through external observation equipment;
when the signal to be detected is an alternating current or direct current signal, the path where the signal is located is enabled through the signal selection unit, other paths are kept in a closed state, then the switch unit C is in a closed state through the switch unit group and the control logic unit, the switch unit A, B, D is in an open state, the circuit is in a direct output working mode at the moment, finally the signal is output from the pad, and the current value is observed through external observation equipment.
In a third aspect, the invention provides a self-bias operational amplifier for on-chip voltage and current signal detection, which comprises a rail-to-rail differential input unit, an I-V current and voltage conversion unit, a phase compensation unit, a secondary amplification unit, a bias voltage generation unit and a self-bias current generation unit.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the invention adopts the same detection circuit to detect the voltage signal and the current signal, thereby saving the area of the chip occupied by the circuit;
2. a unit gain negative feedback loop is formed in an operational amplifier mode, the stability of the whole loop is ensured, a stable output signal is obtained, and when the phase margin of the alternating current small signal is set to be more than or equal to 45 degrees, the difference value between the observed voltage output value and the voltage input value can be ensured to be almost ignored, so that the detection accuracy is ensured;
3. all switch input signals can be voltage signals or current signals, so that the possibility of each input signal is widened;
4. the detection range is wide, and the voltage range to be detected can be observed from 0 to VDD;
5. because no other circuit is needed to provide current, the voltage and current detection circuit can be placed at the corner position of the chip, and the area of the chip is fully utilized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of an on-chip voltage-current detection circuit according to the present invention;
FIG. 2 is a timing diagram of the operation of the circuit for detecting voltage signals in the operational amplifier mode according to the present invention;
FIG. 3 is a timing diagram illustrating the operation of the circuit for detecting DC voltage signals in the direct input mode according to the present invention;
FIG. 4 is a timing diagram illustrating the operation of the circuit for detecting current signals in the direct input mode according to the present invention;
FIG. 5 is a circuit diagram of a self-biased operational amplifier according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
In the circuit diagram of the present specification, the symbol "MN" refers to an N-channel MOS transistor, and "MP" refers to a P-channel MOS transistor.
Example 1
FIG. 1 is a diagram of an on-chip voltage-current signal detection circuit according to the present invention. As shown in fig. 1, the on-chip voltage/current signal detection circuit is composed of a signal selection unit, a self-biased operational amplifier, a switch set, a control logic unit, an electrostatic protection unit, and a current limiting unit.
The signal selection unit 101 is used for selecting the analog signals accessed to the detection circuit, the signal selection unit can be composed of a plurality of groups of switches connected in parallel, and the signal selection unit 101 can only select one analog signal to be detected to flow into the detection circuit at one time;
the self-bias operational amplifier 102 is used for accurately tracking the analog signal to be detected;
the switch group and control logic unit 103 comprises A, B, C, D four groups of switches and is used for controlling the switch group to be switched on or switched off according to the test requirement;
the electrostatic protection unit comprises a primary electrostatic protection unit 106 and a secondary electrostatic protection unit 104, and is used for eliminating the influence of static electricity outside the chip on the detection circuit inside the chip and protecting the circuit from static electricity;
the electrostatic protection unit adopts conventional electrostatic protection components in the field, such as an IO circuit, an EDS electrostatic diode and the like.
The detection circuit of the present invention is disabled once the inside of the chip is affected by static electricity, so that the chip needs to be protected by static electricity. The electrostatic discharge mainly includes a human body discharge mode (human body mode), a machine discharge mode (machine mode), a device charging mode (charged device mode), an electric field-induced mode (field-induced mode), and the like.
And a current limiting unit 105 for limiting the current flowing into the detection circuit and protecting the circuit from damage. The current limiting unit may be a resistor.
The input end of the signal selection unit 101 is connected with an analog signal to be detected, the output end of the signal selection unit 101 is connected with the non-inverting input end of the self-biased operational amplifier 102, the output end of the signal selection unit 101 is further connected with a switch group C, the output end of the self-biased operational amplifier 102 is connected with a switch group A, the inverting input end of the self-biased operational amplifier 102 is connected with a switch group B, the output ends of the switch group B and the switch group C are simultaneously connected with the output end of the switch group A, the output end of the switch group A is connected with the input end of the secondary electrostatic protection unit 104, the output end of the secondary electrostatic protection unit 104 is connected with the input end of the current limiting unit 105, the output end of the current limiting unit 105 is connected with the input end of the IO circuit 106, the output end of the IO circuit 106 is connected with a bonding pad 107, and the switch group D is arranged inside the self-biased operational amplifier 102.
The invention comprises two working modes of an operational amplifier mode and a direct output mode. The switching between the two modes is performed by a control signal selection unit 101, a self-biased operational amplifier 102, a switch group and a control logic unit 103. In the operational amplifier mode, voltage signals (including direct current or alternating current voltage signals) of each node in the chip can be observed. In the direct output mode, current signals (including direct current or alternating current signals) and voltage signals (limited to direct current voltage signals) of each node in the chip can be observed.
The working principle of the voltage and current signal detection circuit in the chip is as follows:
assuming that the IN _0 signal to be observed is a DC voltage signal, both the operational amplifier mode and the direct input mode can be used.
IN the operational amplifier mode, the signal selecting unit 101 enables the IN _0 path, all other paths are kept IN the off state, then the switch unit A, B, D is IN the on state and the switch unit C is IN the off state through the switch unit group and the control logic unit 102, and the IN _0 signal passes through the self-biased operational amplifier 102 and the switch unit D, B, A, then is sequentially transmitted to the secondary electrostatic protection unit 104, the current limiting unit 105, the primary electrostatic protection unit 106, and finally is output from the pad 107.
Fig. 2 is a timing diagram of the operation of the detection circuit in the operational amplifier mode. Fig. 2 shows that, IN the operational amplifier mode, the self-biased operational amplifier 102 and the switching unit A, B, D form a unity gain negative feedback loop IN combination, so that the output OUT of the detection circuit is clamped to the IN _0 voltage by the high gain of the self-biased operational amplifier and the unity negative feedback loop, whereby the IN _0 voltage value can be observed by an external observation device. Under the operational amplifier mode, a unit gain negative feedback loop is formed by matching the self-biased operational amplifier with the switch group ABD, so that the stability of the whole loop is ensured.
The principle that the invention can form a unit gain negative feedback loop in an operational amplifier mode is as follows: in the operational amplifier mode, the actual output value of the voltage will gradually increase with the time, which will affect the detection accuracy, and after the unity gain negative feedback loop is formed, the phase Margin (phase Margin) of the closed circuit formed by the switch group A, B, D being turned on at the same time is set to be equal to or greater than 45 °, preferably equal to or greater than 60 °, so that the difference between the observed voltage output value and the voltage input value can be almost ignored, thereby ensuring the detection accuracy. On the contrary, if no negative feedback loop is formed in the operational amplifier mode, the output voltage is amplified and finally equals to the power supply voltage, and the actual output value and the input value of the voltage have a large deviation, which results in that the voltage of the internal node of the chip cannot be detected.
The circuit working principle of the self-biased operational amplifier is as follows: the operational amplifier is provided with a non-inverting input end and an inverting input end, when an input signal passes through the inverting input end, an output signal is attenuated to a certain degree, the signal returns to the inverting input end through a negative feedback loop and is output again, the output signal is enhanced to a certain degree, when the phase margin is larger than or equal to 45 degrees and preferably larger than or equal to 60 degrees, the attenuation amplitude and the enhancement amplitude of the signal are almost equal, so that the observed voltage output and the voltage input value are almost the same, and the detection precision is high.
IN the direct input mode, the IN _0 path is enabled through the signal selection unit 101, all other paths are kept IN the off state, then the switch unit C is controlled to be IN the on state through the switch unit group and the control logic unit 102, the switch unit A, B, D is IN the off state, then the switch unit C is IN the on state through the switch logic of the switch unit a/B/C/D, and the switch unit a/B/D is IN the off state, so that the IN _0 input current signal passes through the path of the switch unit C, sequentially passes through the secondary electrostatic protection unit 104, the current limiting unit 105 and the primary electrostatic protection unit 106 without passing through the self-bias operational amplifier 102, and finally is output from the pad 107, and the voltage value of the IN _0 is observed by an external observation device. FIG. 3 is a timing diagram of the operation of the circuit for detecting voltage signals in the direct input mode.
If the signal to be observed is an ac voltage signal, only the operational amplifier mode can be used, and the operation timing diagram of the detection circuit is shown in fig. 2. The signal flow direction when detecting the ac voltage is the same as the signal flow direction when detecting the dc voltage signal.
If the IN _1 signal to be observed is a current signal (DC or AC), only the direct output mode can be selected for observation. IN the direct output mode, the signal selection unit 101 enables the path of IN _1, all other paths are kept IN the off state, then the switching unit C is IN the on state through the switching logic of the switching unit a/B/C/D, and the switching unit a/B/D is IN the off state, so that the IN _1 input current signal passes through the path of the switching unit C, sequentially flows through the secondary electrostatic protection unit 104, the current limiting unit 105 and the primary electrostatic protection unit 106 without passing through the self-bias operational amplifier 102, and is finally output from the pad 107, and the current value of IN _1 is observed by an external observation device. FIG. 4 is a timing diagram of the circuit operation of detecting a current signal in the direct input mode.
Example 2
FIG. 5 is a circuit diagram of a self-biased operational amplifier according to the present invention. As shown in fig. 5, the self-biased operational amplifier is composed of a rail-to-rail differential input unit 501, an I-V current-voltage conversion unit 502, a phase compensation unit 503, a secondary amplification unit 504, a bias voltage generation unit 505, and a bias current generation unit 506;
the rail-to-rail differential input unit 501 is used for converting a voltage signal into a current signal;
the I-V current-voltage conversion unit 502 is configured to convert the current signal into a voltage signal;
the phase compensation unit 503 is used for phase adjustment;
the secondary amplification unit 504 is used for realizing gain amplification;
the bias voltage generating unit 505 is configured to generate a bias voltage and provide a working voltage for other functional units;
the bias current generating unit 506 is configured to generate a bias current and provide the bias voltage generating unit 505 with an operating current.
The phase compensation unit is a circuit with a phase (frequency) compensation function, which is conventional in the field;
the bias voltage generating unit is a circuit capable of generating a bias voltage, which is conventional in the art.
The rail-to-rail differential input unit comprises P-channel MOS tubes MP1, MP2 and MP3, and N-channel MOS tubes MN1, MN2 and MN 3; the in-phase input signal INP is respectively accessed to the grids of the MOS tubes MP1 and MN2, the anti-phase input signal INN is respectively accessed to the grids of the MOS tubes MN1 and MP2, the source of the MN1 is connected with the source of the MN2, the common end of the source of the MN1 and the source of the MN2 is connected with the drain of the MN3, and the source of the MN3 is grounded; the source of MP3 is connected to the power supply, and the drain of MP3 is connected to the common terminal of the source of MP1 and the source of MP 2.
The I-V current-voltage conversion unit comprises P-type channel MOS tubes MP4, MP5, MP6 and MP7, and N-type channel MOS tubes MN6, MN7, MN4 and MN 5; the source of MP4 is connected with the power supply, the gate of MP4 is connected with the gate of MP5, the drain of MP4 is connected with the source of MP6, the gate of MP6 is connected with the gate of MP7, the drain of MP6 is connected with the drain of MN6, the gate of MN6 is connected with the gate of MN7, the source of MP6 is connected with the drain of MN4, the common end of the source of MN6 and the drain of MN4 is connected with the drain of MP1, the gate of MN4 is connected with the gate of MN5, the source of MN4 is grounded, the source of MN5 is grounded, the drain of MN5 is connected with the source of MN7, the common end of the drain of MN5 and the source of MN7 is connected with the drain of MP2, the drain of MN7 is connected with the drain of MP7, the source of MP7 is connected with the drain of MP5, and the source of MP5 is connected with the power supply; the common end of the gate of MN4 and the gate of MN5 is connected with the common end of the drain of MN7 and the drain of MP7, the common end of the drain of MP7 and the drain of MN7 is connected with the common end of the gate of MN4 and the gate of MN5, and the common end of the drain of MP5 and the source of MP7 is connected with the drain of MN 1.
The phase compensation unit comprises a first phase compensation unit and a second phase compensation unit, wherein the input end of the first phase compensation unit is connected with the common end of the drain electrode of the MP4 and the source electrode of the MP6, the output end of the first phase compensation unit is connected with the input end of the second phase compensation unit, and the output end of the second phase compensation unit is connected with the common end of the source electrode of the MN6 and the drain electrode of the MN 4.
The second-stage amplification unit comprises a source electrode of the MP8 connected with a power supply, a drain electrode of the MP8 connected with a drain electrode of the MN8, a common end of the drain electrode of the MP8 and the drain electrode of the MN8 is connected with common ends of the first phase compensation unit and the second phase compensation unit, and is also connected with a signal output end AMP OUT of the self-bias operational amplifier, a gate electrode of the MN8 connected with a common end of a drain electrode of the MP6 and a drain electrode of the MN6, and a source electrode of the MN8 connected with the ground.
The bias voltage generating unit comprises BIASP1, BIASP2, BIASN1 and BIASN2, wherein the output end of the BIASP1 is simultaneously connected with the grid of the MP3, the grid of the MP4, the grid of the MP5 and the grid of the MP8, the output end of the BIASP2 is connected with the common ends of the grid of the MP6 and the grid of the MP7, the output end of the BIASN2 is connected with the common ends of the grid of the MN6 and the grid of the MN7, and the output end of the BIASN1 is connected with the grid of the MN 3;
the input end A of the bias voltage generating unit is connected with a power supply, and the input end C is grounded.
The bias current generating unit comprises a variable resistor R, one end of the variable resistor R is connected with a power supply, the other end of the variable resistor R is connected with the drain electrode of MN9, and meanwhile, the common end of the drain electrode of MN9 and the grid electrode of MN9 is connected with bias voltage generating units BIASP1, BIASP2, BIASN1 and BIASN2, and the source electrode of MN9 is grounded.
The working principle of the self-biased operational amplifier for realizing high gain is as follows: first-level gain amplification is realized by the rail-to-rail differential input unit 501 and the I-V current-voltage conversion unit 502, and second-level gain amplification is realized by the second-level amplification unit 504. The gain calculation formula after the amplification of the self-biased operational amplifier is as follows:
Av＝Av1×Av2＝(gm1×R1)×(gm2×R2)
wherein gm1 is the transconductance of the rail-to-rail differential input unit (i.e. the transconductance of the first-stage amplification unit), gm2 is the transconductance of the second-stage amplification unit, R1 is the output impedance of the first-stage amplification unit, and R2 is the output impedance of the second-stage amplification unit.
Obviously, according to the requirement of gain amplification factor, multi-stage gain amplification can be realized by adding an amplification unit.
Hereinafter, the term "comprising" or "may include" used in various embodiments of the present invention indicates the presence of the invented function, operation or element, and does not limit the addition of one or more functions, operations or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that, if it is described that one constituent element is "connected" to another constituent element, the first constituent element may be directly connected to the second constituent element, and the third constituent element may be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element, it is understood that there is no third constituent element between the first constituent element and the second constituent element.
The terminology used in the various embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A voltage and current signal detection circuit in a chip is characterized by comprising a signal selection unit, a self-biased operational amplifier, a switch group, a control logic unit, an electrostatic protection unit and a current limiting unit;
the electrostatic protection unit comprises a primary electrostatic protection unit and a secondary electrostatic protection unit;
the input end of the signal selection unit is connected with an analog signal to be detected, the output end of the signal selection unit is connected with the in-phase input end of the self-biased operational amplifier, the output end of the signal selection unit is also connected with the switch group C, the output end of the self-biased operational amplifier is connected with the switch group A, the inverting input end of the self-biased operational amplifier is connected with the switch group B, the output ends of the switch group B and the switch group C are simultaneously connected with the output end of the switch group A, the output end of the switch group A is connected with the input end of the secondary electrostatic protection unit, the output end of the secondary electrostatic protection unit is connected with the input end of the current limiting unit, the output end of the current limiting unit is connected with the input end of the IO circuit, the output end of the IO circuit is connected with the bonding pad, and the switch group D is arranged in the self-biased operational amplifier;
the self-bias operational amplifier is used for accurately tracking the analog signal to be detected;
the switch group and the control logic unit are used for controlling the switch group to be switched on or switched off according to the test requirement;
the static protection unit is used for eliminating the influence of static outside the chip on the detection circuit in the chip and preventing the detection circuit from failing;
the current limiting unit is used for limiting the current flowing into the detection circuit and protecting the circuit from being damaged.
2. The on-chip voltage-current signal detection circuit of claim 1, wherein the signal selection unit is composed of a plurality of sets of switches connected in parallel, and only one analog signal to be detected is selected to flow into the detection circuit at a time; the electrostatic protection unit is an IO circuit and an EDS electrostatic diode; the current limiting unit is a resistor.
3. The on-chip voltage-current signal detection circuit according to claim 1, wherein the self-biased operational amplifier is composed of a rail-to-rail differential input unit, an I-V current-voltage conversion unit, a phase compensation unit, a secondary amplification unit, a bias voltage generation unit, and a bias current generation unit;
the rail-to-rail differential input unit is used for converting a voltage signal into a current signal;
the I-V current-voltage conversion unit is used for converting the current signal into a voltage signal;
the phase compensation unit is used for adjusting the phase;
the secondary amplification unit is used for realizing gain amplification;
the bias voltage generating unit is used for generating bias voltage and providing working voltage for other functional units;
the bias current generating unit is used for generating a bias current and providing a working current for the bias voltage generating unit.
4. The on-chip voltage-current signal detection circuit according to claim 3, wherein the rail-to-rail differential input unit comprises P-channel MOS transistors MP1, MP2, MP3, N-channel MOS transistors MN1, MN2, MN 3; the in-phase input signal INP is respectively accessed to the grids of the MOS tubes MP1 and MN2, the anti-phase input signal INN is respectively accessed to the grids of the MOS tubes MN1 and MP2, the source of the MN1 is connected with the source of the MN2, the common end of the source of the MN1 and the source of the MN2 is connected with the drain of the MN3, and the source of the MN3 is grounded; the source of MP3 is connected to the power supply, and the drain of MP3 is connected to the common terminal of the source of MP1 and the source of MP 2.
5. The on-chip voltage-current signal detection circuit of claim 3, wherein the I-V current-voltage conversion unit comprises P-channel MOS transistors MP4, MP5, MP6 and MP7, and N-channel MOS transistors MN6, MN7, MN4 and MN 5; the source of MP4 is connected with the power supply, the gate of MP4 is connected with the gate of MP5, the drain of MP4 is connected with the source of MP6, the gate of MP6 is connected with the gate of MP7, the drain of MP6 is connected with the drain of MN6, the gate of MN6 is connected with the gate of MN7, the source of MP6 is connected with the drain of MN4, the common end of the source of MN6 and the drain of MN4 is connected with the drain of MP1, the gate of MN4 is connected with the gate of MN5, the source of MN4 is grounded, the source of MN5 is grounded, the drain of MN5 is connected with the source of MN7, the common end of the drain of MN5 and the source of MN7 is connected with the drain of MP2, the drain of MN7 is connected with the drain of MP7, the source of MP7 is connected with the drain of MP5, and the source of MP5 is connected with the power supply;
the common end of the gate of MN4 and the gate of MN5 is connected with the common end of the drain of MN7 and the drain of MP7, the common end of the drain of MP7 and the drain of MN7 is connected with the common end of the gate of MN4 and the gate of MN5, and the common end of the drain of MP5 and the source of MP7 is connected with the drain of MN 1.
6. The on-chip voltage-current signal detection circuit of claim 3, wherein the phase compensation unit comprises a first phase compensation unit and a second phase compensation unit, an input terminal of the first phase compensation unit is connected with a common terminal of a drain of MP4 and a source of MP6, an output terminal of the first phase compensation unit is connected with an input terminal of the second phase compensation unit, and an output terminal of the second phase compensation unit is connected with a common terminal of a source of MN6 and a drain of MN 4.
7. The on-chip voltage current signal detection circuit of claim 3, wherein the secondary amplification unit comprises a source of MP8 connected to a power supply, a drain of MP8 connected to a drain of MN8, a common terminal of the drain of MP8 and the drain of MN8 connected to a common terminal of the first phase compensation unit and the second phase compensation unit, and also connected to a signal output terminal AMP OUT of the bias operational amplifier, a gate of MN8 connected to a common terminal of the drain of MP6 and the drain of MN6, and a source of MN8 connected to a ground.
8. The on-chip voltage-current signal detection circuit of claim 3, wherein the bias voltage generation unit comprises BIASP1, BIASP2, BIASN1 and BIASN2, the output terminal of the BIASP1 is connected to the gate of MP3, the gate of MP4, the gate of MP5 and the gate of MP8 at the same time, the output terminal of the BIASP2 is connected to the common terminal of the gate of MP6 and the gate of MP7, the output terminal of the BIASN2 is connected to the common terminal of the gate of MN6 and the gate of MN7, and the output terminal of the BIASN1 is connected to the gate of MN 3; the input end A of the bias voltage generating unit is connected with a power supply, and the output end C is grounded.
9. The on-chip voltage-current signal detection circuit of claim 3, wherein the bias current generation unit comprises a variable resistor R having one end connected to the power supply and the other end connected to the drain of the MN9, while the common end of the drain of the MN9 and the gate of the MN9 is connected to the input B of the bias voltage generation unit, and the source of the MN9 is grounded.
10. A method for detecting voltage and current signals in a chip is characterized by comprising the following steps:
when the signal to be detected is a direct-current voltage signal, the path where the signal is located is enabled through the signal selection unit, other paths are kept in a closed state, then the switch unit A, B, D is in a closed state through the switch unit group and the control logic unit, the switch unit C is in an open state, and at the moment, the circuit is in an operational amplifier working mode; in addition, the switch unit C can be in a closed state and the switch unit A, B, D can be in an open state through the switch unit group and the control logic unit, at this time, the circuit is in a direct output working mode, finally, a signal is output from the pad, and the direct-current voltage value is observed by external observation equipment;
when the signal to be detected is an alternating voltage signal, firstly enabling a channel where the signal is located through the signal selection unit, keeping other channels in a closed state, then enabling the switch unit A, B, D to be in a closed state through the switch unit group and the control logic unit, enabling the switch unit C to be in an open state, enabling the circuit to be in an operational amplifier working mode, finally outputting the signal from the bonding pad, and observing an alternating voltage value through external observation equipment;
when the signal to be detected is an alternating current or direct current signal, the path where the signal is located is enabled through the signal selection unit, other paths are kept in a closed state, then the switch unit C is in a closed state through the switch unit group and the control logic unit, the switch unit A, B, D is in an open state, the circuit is in a direct output working mode at the moment, finally the signal is output from the pad, and the current value is observed through external observation equipment.
The phase margin of the closed circuit formed by the simultaneous conduction of the switch groups A, B, D is 45 ° or more.
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