CN113972137A - Preparation method of alignment mark and preparation method of fin field effect transistor - Google Patents

Preparation method of alignment mark and preparation method of fin field effect transistor Download PDF

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Publication number
CN113972137A
CN113972137A CN202010715841.6A CN202010715841A CN113972137A CN 113972137 A CN113972137 A CN 113972137A CN 202010715841 A CN202010715841 A CN 202010715841A CN 113972137 A CN113972137 A CN 113972137A
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mark
forming
alignment mark
fin
layer
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陈庆煌
曾暐舜
刘志成
王见明
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Quanxin Integrated Circuit Manufacturing Jinan Co Ltd
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Quanxin Integrated Circuit Manufacturing Jinan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The embodiment of the invention provides a preparation method of an alignment mark and a preparation method of a fin field effect transistor, and relates to the technical field of semiconductors. The preparation method of the alignment mark comprises the following steps: forming a fin portion on a substrate; forming mark reference parts on the fin parts, and forming mark forming areas among the mark reference parts; and forming an alignment mark on the fin part of the mark forming area. The alignment mark formed by the preparation method has clearer patterns, can improve the signal intensity and the measurement accuracy, and is beneficial to forming miniature patterns in the semiconductor manufacturing process. The preparation method is also suitable for the existing fin field effect transistor manufacturing process and has good application prospect.

Description

Preparation method of alignment mark and preparation method of fin field effect transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for preparing an alignment mark and a method for preparing a fin field effect transistor.
Background
Semiconductor Integrated Circuit (IC) fabrication involves the formation of patterned layers of materials on a semiconductor wafer, each layer having to be aligned with previous layers so that the formed circuits function properly. Therefore, various alignment marks are designed, such as a photo mark for alignment between a photomask and a semiconductor wafer, and an overlay mark for alignment between layers in a semiconductor.
As semiconductor technology continues to advance toward circuits with smaller feature sizes, alignment requirements become more stringent. At present, fin field effect transistors are widely used in chip manufacturing processes to form micro patterns.
Therefore, the alignment mark is prepared in the fin field effect transistor, so that the pattern of the alignment mark can be clearer, and the signal intensity and the measurement accuracy are improved, which is a technical problem to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a preparation method of an alignment mark and a preparation method of a fin field effect transistor, which can enable the pattern of the alignment mark to be clearer and improve the signal intensity and the measurement accuracy.
Embodiments of the invention may be implemented as follows:
in a first aspect, an embodiment of the present invention provides a method for manufacturing an alignment mark, including: forming a fin portion on a substrate; forming mark reference parts on the fin parts, and forming mark forming areas among the mark reference parts; and forming an alignment mark on the fin part of the mark forming area.
In an alternative embodiment, the material of the alignment mark is SiP or SiGe.
In an optional embodiment, forming the mark reference parts on the fin part, and forming the mark forming region between the mark reference parts comprises: forming a first anti-reflection layer on the substrate and the fin portion; and patterning the first anti-reflection layer, wherein in the patterned first anti-reflection layer, the solid part is used as a mark reference part, and the hollow part is used as a mark forming area.
In an optional embodiment, after forming the first anti-reflection layer on the substrate and the fin, the method further comprises: sequentially forming a first spin-on glass layer and a first photoresist layer on the first anti-reflection layer; exposing and developing the first photoresist layer to form a plurality of first photoetching shielding parts; patterning the first anti-reflective layer includes: and removing materials of the first spin-on glass layer and the first anti-reflection layer corresponding to the projection position without the first photoetching shielding part to form a mark forming area.
In an optional embodiment, after removing the material of the first spin-on glass layer and the first anti-reflection layer corresponding to the projection position without the first photolithographic shielding part and forming the mark forming region, the method further comprises: and removing the first photoetching shielding part and the material of the first spin-on glass layer covered by the first photoetching shielding part to form the mark reference part.
In an optional embodiment, the marked reference portion is coated on the surface of the fin portion.
In an alternative embodiment, the marker reference is located at the top of the fin.
In an optional embodiment, the alignment mark includes a vertical portion on the fin and an extension portion extending laterally from the vertical portion.
In an optional embodiment, the alignment marks on two adjacent fins are connected with each other through the extension portion.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a fin field effect transistor, including the method for manufacturing an alignment mark of the first aspect.
The preparation method of the alignment mark and the preparation method of the fin field effect transistor provided by the embodiment of the invention have the beneficial effects that:
according to the preparation method, the mark reference part and the mark forming area are formed before the alignment mark is formed, so that the area where the alignment mark is formed is clearly defined, the formed pattern of the alignment mark is clearer, the signal intensity and the measurement accuracy can be improved, and the formation of a miniature pattern in a semiconductor manufacturing process is facilitated; the preparation method only adds the steps of forming the mark reference part and the mark forming region in the existing fin field effect transistor manufacturing process, so that the preparation method can be suitable for the existing fin field effect transistor manufacturing process and has good application prospect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a flowchart of a method for manufacturing an alignment mark according to a first embodiment of the present invention;
fig. 2a to fig. 2g are schematic structural diagrams illustrating a process of preparing an alignment mark according to a first embodiment of the present invention;
FIG. 3a is a schematic diagram of an alignment mark as an overlay mark;
FIG. 3b is a schematic diagram of an alignment mark as a light alignment mark;
FIG. 4 is a flowchart illustrating a method for fabricating an alignment mark according to a second embodiment of the present invention;
fig. 5a to 5o are schematic structural diagrams illustrating a process of manufacturing an alignment mark according to a first embodiment of the present invention.
Icon: 1-a substrate; 2-a fin portion; 3-a groove; 4-a first anti-reflection layer; 5-a first spin-on glass layer; 6-a first photoresist layer; 7-a first lithographic masking; 8-mark reference; 9-mark formation region; 10-alignment mark; 11-a substrate; 12-etching stop layer; 13-a hard mask layer; 14-a layer of sacrificial material; 15-a second anti-reflection layer; 16-a second spin-on glass layer; 17-a second photoresist layer; 18-a second lithographic mask; 19-a core section; 20-a cushion layer; 21-side wall.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
As semiconductor technology continues to advance toward circuits with smaller feature sizes, alignment requirements become more stringent. Embodiments of the present invention provide a method for manufacturing an Alignment mark and a method for manufacturing a fin field effect transistor, which can make a pattern of the Alignment mark clearer, and improve signal strength (Alignment Wafer Quality) and measurement accuracy.
First embodiment
Referring to fig. 1, the present embodiment provides a method for manufacturing an alignment mark, including the following steps:
s101: a fin 2 is formed on a substrate 1.
Referring to fig. 2a, the substrate 1 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped, such as with p-type or n-type dopants, or undoped. The substrate 1 may be a wafer, for example, a silicon wafer. In general, the SOI substrate 1 includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate 1, the substrate 1 typically being a silicon or glass substrate 1. Other substrates 1, for example, multilayer or gradient substrates 1, may also be used. In some embodiments, the semiconductor material of the substrate 1 may include silicon, germanium, a compound semiconductor, or an alloy semiconductor. Wherein the compound semiconductor comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; the alloy semiconductor includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.
In some embodiments, trenches 3 are formed between fins 2 by using, for example, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching process may be anisotropic. In some embodiments, the grooves 3 may be strips that are parallel to each other and closely spaced relative to each other. In some embodiments, the trench 3 may be continuous and surround the fin 2.
The material of the fin parts 2 is the same as that of the substrate 1, and the fin parts 2 protrude on the substrate 1 at intervals. The formation of the fins 2 may be patterned by photolithographic and etching techniques on the substrate 1. In summary, the fin 2 may be patterned by any suitable method. For example, the fin 2 may be patterned using one or more lithographic processes, including double patterning or multiple patterning processes. Typically, double-patterning or multi-patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns with, for example, smaller pitches than are obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over the substrate 1 and patterned using a photolithographic process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process, the sacrificial layer is then removed, and finally the fin 2 may be patterned using the remaining spacers or mandrels.
In other embodiments, the fin 2 may be formed on the substrate 1 after the substrate 1 is separately formed, and similar to the substrate 1, the fin 2 may include: silicon or other elemental semiconductors such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP; or a combination thereof. The fin 2 may be fabricated using a suitable process including a photolithography and etching process.
S102: mark reference portions 8 are formed on the fin portion 2, and mark formation regions 9 are formed between the mark reference portions 8.
First, referring to fig. 2b, a first anti-reflective layer 4, a first spin-on glass layer 5 and a first photoresist layer 6 are sequentially formed on the substrate 1 and the fin portion 2. The first antireflection layer 4 may be a SOC (spin on carbon), and the first spin-on glass layer 5 is also called an SOG (spin on glass) layer.
Next, referring to fig. 2c, the first photoresist layer 6 is exposed and developed to form a plurality of first photoresist masking portions 7, that is, the remaining material of the first photoresist layer 6 is used as the first photoresist masking portion 7. The first mask 7 is used to prepare the mark reference portion 8 for subsequent formation. The first photoetching shielding parts 7 are positioned right above the fin part 2, and the area between the first photoetching shielding parts 7 is positioned right above the mark forming area 9.
Then, referring to fig. 2d, the materials of the first spin-on glass layer 5 and the first anti-reflection layer 4 corresponding to the projection position without the first masking portion 7 are removed to form the mark forming region 9, that is, the materials of the first spin-on glass layer 5 and the first anti-reflection layer 4 without the masking portion 7 are etched away, wherein the hollow region in the first anti-reflection layer 4 forms the mark forming region 9, and the first masking portion 7 and the material right under the first masking portion are retained.
Finally, referring to fig. 2e, the first photoresist masking portion 7 and the material of the first spin-on-glass layer 5 covered by the first photoresist masking portion 7 are removed to form the mark reference portion 8, that is, the first photoresist masking portion 7 and the material of the first spin-on-glass layer 5 directly below the first photoresist masking portion are etched away, and the remaining material of the first anti-reflection layer 4 forms the mark reference portion 8.
In this embodiment, the mark reference portion 8 is covered on the surface of the fin portion 2, that is, the bottom surface of the fin portion 2 is connected to the substrate 1, and the top surface and the side surface of the fin portion 2 are covered by the mark reference portion 8. Thus, the position of the mark reference part 8 is more stable, which is beneficial to forming the alignment mark 10 with accurate position later.
In other embodiments, the mark reference portion 8 may be located at the top of the fin 2, that is, the mark reference portion 8 is located above the fin 2 and connected to the top surface of the fin 2.
S103: referring to fig. 2f, alignment marks 10 are formed on the fin 2 in the mark forming region 9.
An EPI (EPI) growth process is used to form an alignment mark 10 on the fin portion 2 of the mark forming region 9, and the alignment mark 10 is made of SiP or SiGe. Since the epitaxial material is grown only on the fin 2, the alignment mark 10 is formed by Self-Aligned (Self-Aligned) growth without affecting the alignment measurement result. Moreover, under the EPI photomask, the pattern of the alignment mark 10 is formed in a whole piece, and the formed appearance is clear.
The formed alignment mark 10 may be polygonal, in this embodiment, the shape of the alignment mark 10 is hexagonal, specifically, the alignment mark 10 includes a vertical portion located on the fin portion 2 and an extension portion laterally extending from the vertical portion, where the vertical portion is rectangular, the extension portion is triangular, and the alignment marks 10 on two adjacent fin portions 2 are connected to each other through the extension portion, so that the formed alignment mark 10 is more clear in graph, the signal strength and the measurement accuracy can be improved, and formation of a micro pattern in a semiconductor manufacturing process is facilitated.
In other embodiments, two adjacent fins 2 may be spaced apart from each other by a certain distance, and as such, the pattern of the alignment mark 10 can be made clearer. Other options for the shape of the alignment mark 10 are possible, such as: the extension part is oval, rectangular and the like.
S104: referring to fig. 2g, the mark reference part 8 is removed.
Specifically, after the alignment mark 10 is formed, the mark reference part 8 is washed away, and the process for manufacturing the alignment mark 10 is completed. In some embodiments, the wet etch process is performed using a suitable etchant, such as dilute hydrofluoric acid (dHF) or a solution containing di-ionized water and ozone (DIO 3). In some embodiments, the wet etch process removes the marker references 8.
Referring to fig. 3a, the alignment Mark 10 formed by the manufacturing method of the present embodiment may be used as an Overlay Mark (english name) for alignment between layers in a semiconductor. The overall form of the overlay mark may be: the mark is formed by arranging a plurality of groups of marks, two adjacent groups of marks are mutually vertical, and each group of marks comprises a plurality of columns of marks which are uniformly arranged at intervals.
Referring to fig. 3b, the Alignment Mark 10 formed by the manufacturing method of the present embodiment can be used as an Alignment Mark (english name) for Alignment between a photomask and a semiconductor wafer. The overall form of the light signature may be: the multilayer marks are uniformly distributed at intervals, each layer of marks comprises two lines of marks connected at a preset angle, the preset angle can be 90 degrees, and angle bisectors of each layer of marks are arranged in a collinear mode.
The preparation method of the alignment mark provided by the embodiment has the beneficial effects that:
1. according to the preparation method, the mark reference part 8 and the mark forming area 9 are formed before the alignment mark 10 is formed, so that the area formed by the alignment mark 10 is clearly limited, the formed pattern of the alignment mark 10 is clearer, the signal intensity and the measurement accuracy can be improved, and a miniature pattern can be formed in the semiconductor manufacturing process;
2. the preparation method only adds the steps of forming the mark reference part 8 and the mark forming region 9 in the existing fin field effect transistor manufacturing process, so that the preparation method is suitable for the existing fin field effect transistor manufacturing process and has good application prospect.
Second embodiment
Referring to fig. 4, the present embodiment provides a method for fabricating a fin field effect transistor, which includes the method for fabricating an alignment mark provided in the first embodiment. The method for manufacturing the fin field effect transistor provided by the embodiment comprises the following steps:
s201: referring to fig. 5a, an etch stop layer 12, a hard mask layer 13, a sacrificial material layer 14, a second anti-reflection layer 15, a second spin-on-glass layer 16 and a second photoresist layer 17 are sequentially formed on a substrate 11.
The substrate 11 may be a semiconductor substrate 11, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate 11, or the like, which may be doped, such as with a p-type or n-type dopant, or undoped. The substrate 11 may be a wafer, for example, a silicon wafer. In general, the SOI substrate 11 includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate 11, the substrate 11 typically being a silicon or glass substrate 11. Other substrates 11 may also be used, for example, a multilayer or gradient substrate 11. In some embodiments, the semiconductor material of the substrate 11 may include silicon, germanium, a compound semiconductor, or an alloy semiconductor. Wherein the compound semiconductor comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; the alloy semiconductor includes SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.
In the present embodiment, the etch stop layer 12 may be a silicon nitride layer formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). In other embodiments, the material of the etch stop layer 12 includes silicon germanium oxide (SiGeO), silicon germanium (SiGe), silicon oxide (SiO), silicon phosphide (SiP), silicon phosphate (SiPO), or a combination thereof.
In the present embodiment, the hard mask layer 13 (english name: "hard mask") may be formed by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The hard mask layer 13 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride.
In this embodiment, the material of the sacrificial material layer 14 may be polysilicon, silicon oxide, amorphous carbon, SiCO, SiCOH, or the like. The sacrificial material layer 14 may be formed by a spin coating process so that its upper surface is flush.
The second anti-reflection layer 15 may employ a SOC (so-called spin on carbon). The second spin-on glass layer 16 is also referred to as a SOG (spin on glass) layer.
S202: referring to fig. 5b, the second photoresist layer 17 is exposed and developed to form a plurality of second photoresist masking portions 18.
That is, the material of the remaining second photoresist layer 17 serves as the second photoresist masking portion 18. The second mask 18 serves to protect the underlying material covered thereby to form the desired material pattern.
S203: referring to fig. 5c, the materials of the second spin-on-glass layer 16, the second anti-reflection layer 15 and the sacrificial material layer 14 corresponding to the projection position without the second masking photoresist 18 are removed to form a core portion 19.
That is, the materials of the second spin-on glass layer 16, the second anti-reflection layer 15 and the sacrificial material layer 14, which are not masked by the second mask 18, are etched away, wherein the remaining material of the sacrificial material layer 14 forms a core 19, and the core 19 functions to provide a reference for the subsequent formation of the sidewall 21.
Wherein, the materials of the second spin-on glass layer 16, the second anti-reflection layer 15 and the sacrificial material layer 14 can be removed by dry etching, wet etching or a combination of the two.
S204: referring to fig. 5d, the materials of the second spin-on-glass layer 16 and the second anti-reflection layer 15 covered by the second masking photoresist 18 and the second masking photoresist 18 are removed to expose the core portion 19.
That is, the second photoresist masking portion 18 and the materials of the second SOG layer 16 and the second anti-reflective layer 15 directly below the second SOG layer are etched away, and the remaining material of the sacrificial material layer 14 forms the core portion 19 and is exposed. Wherein the second photolithography shielding part 18 can be removed by an ashing method.
S205: referring to fig. 5e, a pad layer 20 is formed on the hard mask layer 13 and the core 19.
The pad layer 20 may be a thin film including silicon oxide formed using a thermal oxidation process, for example. In some embodiments, the liner layer 20 may be formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof, and may be formed using Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).
S206: referring to fig. 5f, the material of the liner layer 20 on the top surface of the core 19 is removed to form sidewalls 21.
That is, the material of the liner layer 20 above the core 19 is etched away, the material of the liner layer 20 on both sides of the core 19 remains, and the remaining material of the liner layer 20 forms the sidewalls 21.
S207: referring to FIG. 5g, the core 19 is removed to expose the sidewalls 21.
That is, the core portion 19 is etched away, and the remaining material of the pad layer 20 forms the core portion 19 and is exposed. Sidewalls 21 are spaced apart on the hard mask layer 13, the sidewalls 21 serving to protect underlying material covered thereby to facilitate formation of the fin 2 on the substrate 11. The pattern of the sidewalls 21 is therefore the same as the desired pattern of the fins 2.
S208: referring to fig. 5h, the second anti-reflection layer 15, the material of the etch stop layer 12 corresponding to the projected position without the sidewall 21, and a portion of the material of the base 11 corresponding to the projected position without the sidewall 21 are removed to form the substrate 1 and the fin portion 2.
That is, the material of the second anti-reflection layer 15 and the etch stop layer 12, which are not masked by the sidewall 21, are etched away, and the material of the substrate 11, which is not masked by the sidewall 21, is etched away. The material in the thickness direction of the base 11 remains to form the substrate 1, the material of the base 11 on the substrate 1 forming the fin 2.
Wherein, the materials of the second anti-reflection layer 15, the etching stop layer 12 and the substrate 11 can be removed by dry etching, wet etching or a combination of the two. In some embodiments, the fins 2 are formed by etching trenches 3 in the substrate 11 using, for example, Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or the like, or combinations thereof. The etching process may be anisotropic. In some embodiments, the grooves 3 may be strips that are parallel to each other and closely spaced relative to each other. In some embodiments, the trench 3 may be continuous and surround the fin 2.
Due to the insertion of the etching stop layer 12, the etching depth and the interval of the trench 3 on the substrate 11 can be strictly controlled, so that the finally formed fin portion 2 has a better appearance, and the electrical performance of the semiconductor device is improved.
S209: referring to fig. 5i, the sidewalls 21 and the hard mask layer 13 and the etch stop layer 12 covered by the sidewalls 21 are removed to expose the substrate 1 and the fin portion 2.
That is, the material of the sidewall 21 and the hard mask layer 13 and the etch stop layer 12 directly below the sidewall are etched away, so that the substrate 1 and the fin 2 are exposed.
S210: referring to fig. 5j, a first anti-reflective layer 4, a first spin-on glass layer 5 and a first photoresist layer 6 are sequentially formed on the substrate 1 and the fin portion 2.
The first antireflection layer 4 may be a SOC (spin on carbon), and the first spin-on glass layer 5 is also called an SOG (spin on glass) layer.
S211: referring to fig. 5k, the first photoresist layer 6 is exposed and developed to form a plurality of first photoresist masks 7.
That is, the material of the remaining first photoresist layer 6 serves as the first photoresist masking portion 7. The first mask 7 is used to prepare the mark reference portion 8 for subsequent formation. The first photoetching shielding parts 7 are positioned right above the fin part 2, and the area between the first photoetching shielding parts 7 is positioned right above the mark forming area 9.
S212: referring to fig. 5l, the materials of the first spin-on-glass layer 5 and the first anti-reflection layer 4 corresponding to the projection positions without the first masking portion 7 are removed to form a mark forming region 9.
That is, the materials of the first spin-on glass layer 5 and the first anti-reflection layer 4 that are not shielded by the first mask portion 7 are etched away, wherein the hollow area in the first anti-reflection layer 4 forms the mark forming area 9, and meanwhile, the first mask portion 7 and the material right below the first mask portion are retained.
S213: referring to fig. 5m, the first photoresist masking portion 7 and the material of the first spin-on-glass layer 5 covered by the first photoresist masking portion 7 are removed to form the mark reference portion 8.
That is, the material of the first photoresist masking portion 7 and the first spin-on-glass layer 5 directly below the first photoresist masking portion is etched away, and the remaining material of the first anti-reflection layer 4 forms the mark reference portion 8.
S214: referring to fig. 5n, alignment marks 10 are formed on the fin 2 in the mark forming region 9.
An EPI (EPI) growth process is used to form an alignment mark 10 on the fin portion 2 of the mark forming region 9, and the alignment mark 10 is made of SiP or SiGe. The alignment mark 10 is formed in a hexagonal shape, specifically, the alignment mark 10 includes a vertical portion on the fin portion 2 and an extension portion laterally extending from the vertical portion, and the alignment marks 10 on two adjacent fin portions 2 are connected to each other through the extension portion.
Since the fin 2 has a good profile and a clear mark formation region 9 is defined by the mark reference part 8, a clear alignment mark 10 can be formed. In addition, the alignment mark 10 is made of SiP or SiGe, which can keep the profile of the alignment mark 10 stable, further ensure the clear topography of the alignment mark 10, improve the signal strength and the measurement accuracy, and facilitate the formation of micro patterns in the semiconductor manufacturing process.
S215: referring to fig. 5o, the mark reference part 8 is removed.
That is, after the alignment mark 10 is formed, the mark reference part 8 is washed away, and the process of manufacturing the alignment mark 10 is completed.
The alignment mark 10 formed by the preparation method provided by this embodiment can be used as an overlay mark and also as an alignment mark.
In this embodiment, the contents of S210 to S215 are similar to those of S101 to S104 in the first embodiment, and the first embodiment can be referred to specifically.
The method for manufacturing the fin field effect transistor has the advantages that:
according to the preparation method, the mark reference part 8 and the mark forming area 9 are formed before the alignment mark 10 is formed, so that the area formed by the alignment mark 10 is clearly defined, the formed pattern of the alignment mark 10 is clearer, the signal intensity and the measurement accuracy can be improved, and the formation of a miniature pattern in a semiconductor manufacturing process is facilitated.
The semiconductor device formed by the fabrication method of the present embodiment may also be subjected to processing to form various components and regions known in the art. For example, subsequent processing may form an interlayer dielectric (ILD) layer, contact openings, contact metals, and various contacts/vias/lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 1 configured to connect the various features to form functional circuitry that may include one or more FinFET devices. In yet another example, the multi-layer interconnect may include a vertical interconnect such as a via or contact and a horizontal interconnect such as a metal line. Various conductive materials including copper, tungsten, and/or silicide may be used for the various interconnect features. In one example, damascene and/or dual damascene processes are used to form copper-related multi-level interconnect structures.
The method for manufacturing the fin field effect transistor provided by the embodiment is suitable for manufacturing a fin multi-gate transistor (also called a FinFET device), which can be a double-gate device, a triple-gate device, a bulk device, a silicon-on-insulator (SOI) device and/or other configurations. Other examples of semiconductor devices will be recognized by those of ordinary skill in the art, given the benefit of the present description. For example, some embodiments described herein may also be applied to a Gate All Around (GAA) device, an omega gate (gate) device, or a Pi gate (II gate) device.
It should be understood that the fabrication method provided by the present embodiment includes steps having features of a Complementary Metal Oxide Semiconductor (CMOS) technology process flow, and therefore, is only briefly described herein. Additional steps may be performed before, after and/or during the manufacturing process. Also, it should be noted that the structural schematics of the corresponding methods, including those given with reference to fig. 5 a-5 o, are merely exemplary and are not intended to limit what is specifically recited in the appended claims.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A method of making an alignment mark, the method comprising:
forming a fin portion (2) on a substrate (1);
forming mark reference parts (8) on the fin parts (2), and forming mark forming regions (9) between the mark reference parts (8);
and forming an alignment mark (10) on the fin part (2) of the mark forming region (9).
2. The method for preparing an alignment mark according to claim 1, wherein the material of the alignment mark (10) is SiP or SiGe.
3. The method for preparing an alignment mark according to claim 1, wherein the forming of the mark reference portions (8) on the fin portion (2), the forming of the mark formation regions (9) between the mark reference portions (8) comprises:
forming a first anti-reflection layer (4) on the substrate (1) and the fin portion (2);
and patterning the first anti-reflection layer (4), wherein in the patterned first anti-reflection layer (4), a solid part is used as the mark reference part (8), and a hollow part is used as the mark forming area (9).
4. The method for preparing an alignment mark according to claim 3, wherein after forming a first anti-reflection layer (4) on the substrate (1) and the fin (2), the method further comprises:
sequentially forming a first spin-on glass layer (5) and a first photoresist layer (6) on the first anti-reflection layer (4);
exposing and developing the first photoresist layer (6) to form a plurality of first photoetching shielding parts (7);
the patterning of the first anti-reflection layer (4) comprises:
and removing materials of the first spin-on glass layer (5) and the first anti-reflection layer (4) corresponding to the projection position without the first photoetching shielding part (7) to form the mark forming area (9).
5. The method for preparing an alignment mark according to claim 4, wherein the removing the material of the first spin-on glass layer (5) and the first anti-reflection layer (4) corresponding to the projected position without the first photolithographic shield (7) further comprises, after the forming the mark forming region (9):
and removing the first photoetching shielding part (7) and the material of the first spin-on glass layer (5) covered by the first photoetching shielding part (7) to form the mark reference part (8).
6. The method for preparing an alignment mark according to claim 5, wherein the mark reference portion (8) is coated on the surface of the fin portion (2).
7. The method for preparing an alignment mark according to claim 5, wherein the mark reference portion (8) is located at a top end of the fin portion (2).
8. The method of manufacturing an alignment mark according to claim 1, wherein the alignment mark (10) comprises a vertical portion on the fin (2) and an extension extending laterally from the vertical portion.
9. The method for preparing an alignment mark according to claim 8, wherein the alignment marks (10) on two adjacent fins (2) are connected to each other by the extension.
10. A method for manufacturing a fin field effect transistor, the method comprising the method for manufacturing the alignment mark of any one of claims 1 to 9.
CN202010715841.6A 2020-07-23 2020-07-23 Preparation method of alignment mark and preparation method of fin field effect transistor Pending CN113972137A (en)

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Citations (5)

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US20120126375A1 (en) * 2010-11-19 2012-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming metrology structures from fins in integrated circuitry
CN103681622A (en) * 2012-09-04 2014-03-26 台湾积体电路制造股份有限公司 Enhanced FINFET process overlay mark
CN108089412A (en) * 2017-11-10 2018-05-29 上海华力微电子有限公司 Photoetching alignment precision measures the appraisal procedure of accuracy
CN110931352A (en) * 2018-09-20 2020-03-27 台湾积体电路制造股份有限公司 Method of forming an integrated circuit device
US10635007B1 (en) * 2018-11-13 2020-04-28 Globalfoundries Inc. Apparatus and method for aligning integrated circuit layers using multiple grating materials

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120126375A1 (en) * 2010-11-19 2012-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming metrology structures from fins in integrated circuitry
CN103681622A (en) * 2012-09-04 2014-03-26 台湾积体电路制造股份有限公司 Enhanced FINFET process overlay mark
CN108089412A (en) * 2017-11-10 2018-05-29 上海华力微电子有限公司 Photoetching alignment precision measures the appraisal procedure of accuracy
CN110931352A (en) * 2018-09-20 2020-03-27 台湾积体电路制造股份有限公司 Method of forming an integrated circuit device
US10635007B1 (en) * 2018-11-13 2020-04-28 Globalfoundries Inc. Apparatus and method for aligning integrated circuit layers using multiple grating materials

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