TWI811821B - Semiconductor structure and method for forming the same - Google Patents

Abstract

A method of forming a semiconductor structure includes forming a substrate. The method also includes forming a bottom layer over the substrate. The method also includes forming a blocking structure over the bottom layer. The blocking structure is in a periphery region. The method also includes covering a middle layer over the bottom layer and the blocking structure. The method also includes forming a patterned photoresist layer over the middle layer. The first portion of the patterned photoresist layer is in an array region and directly above the blocking structure in the periphery region. The method also includes transferring the pattern of the patterned photoresist layer to the bottom layer in sequence. The pattern of the patterned photoresist layer directly above the blocking structure is not formed in the bottom layer. The method also includes removing the blocking structure. The method also includes patterning the substrate. The first portion of the substrate is in the array region and is an active array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is periphery structure.

Description

Semiconductor structures and methods of forming them

Embodiments of the present invention relate to a semiconductor structure, and in particular, to a method of forming an active region array.

As the size of integrated circuits shrinks, the density of dynamic random access memory (DRAM) increases, resulting in an iso dense effect at the edge of the active area array area, resulting in active areas at the edge of the array area and the center of the array area. The size and spacing of the area arrays are different, so the proximity effect problem needs to be solved through optical proximity correction (OPC), which costs more and takes more time.

Some embodiments of the present invention provide a method for forming a semiconductor structure, including: forming a substrate, including an array area and a surrounding area; forming a bottom layer on the substrate; forming a barrier structure on the bottom layer, with the barrier structure located in the surrounding area; covering the middle Layer on the bottom layer and the barrier structure; form a patterned photoresist layer on the middle layer, the first part of the patterned photoresist layer is located in the array area and directly above the barrier structure in the surrounding area; transfer the patterned light sequentially the pattern of the resist layer to the bottom layer, and the pattern of the patterned photoresist layer directly above the barrier layer is not formed on the bottom layer; remove the barrier structure; and pattern the substrate, which includes a first part, a second part, and a third part, The first part of the substrate is located in the array The active area array is located in the area, the second part of the substrate is located in the surrounding area and is the protective ring, and the third part of the substrate is located in the surrounding area and is the surrounding structure.

Embodiments of the present invention further provide a semiconductor structure, including a substrate, including an array area and a surrounding area; a protective ring, located in the surrounding area, abutting and surrounding the array area; and an active area array, including an active area, located in the array area; and the surrounding structure, located within the surrounding area, with the protective ring and the surrounding structure being separated from each other.

10a:Array area

10b: Surrounding area

10aS,10bS: side wall

10i:Interface

100:Semiconductor Structure

102:Active zone

104:Protective ring

106: Surrounding structures

108:Substrate

110:Oxide layer

112: Bottom floor

114,114’: blocking structure

114S:Side wall

116: Photoresist layer

118:Middle layer

120:Top layer

121: Three-layer curtain structure

122:Patterned mask layer

122aS, 122bS: spacing

124: Three-layer photoresist structure

126: Bottom floor

128:Middle layer

130:Patterned photoresist layer

130a:Part 1

130b:Part 2

130aaS,130abS: spacing

132:Shallow trench isolation structure

134: character line

136:Isolation materials

102H, 104H: height

102W, 104W, 106W, 10bW: Width

2-2: Line

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of elements may be enlarged or reduced to clearly demonstrate the technical features of the embodiments of the present invention.

Figure 1 is a top view of a semiconductor structure according to some embodiments.

2A-2H are cross-sectional views illustrating various stages of forming a semiconductor structure according to some embodiments.

Embodiments of the present invention provide a semiconductor structure and a method for forming the same. By forming a barrier structure in the surrounding area abutting the array area, and forming an active area array pattern extending into the patterned photoresist layer above the barrier structure, the proximity effect occurs in the patterned photoresist layer on the barrier structure. , setting up a blocking structure can simultaneously eliminate the proximity effect at the edge of the active area array pattern and form a protective ring around the array area.

Figure 1 is a top view of a semiconductor structure 100 according to some embodiments. 2A-2H are cross-sectional views illustrating various stages of forming the semiconductor structure 100 according to some embodiments. Figures 2A-2H illustrate cross-sectional views of the semiconductor structure 100 taken along line 2-2 in Figure 1 .

As shown in Figure 1, the semiconductor structure 100 includes an array region 10a and a surrounding region 10b. The active area array 102 is included in the array area 10a. The surrounding area 10b includes a protective ring 104 and surrounding structure 106. The guard ring 104 and the surrounding structure 106 are spaced apart from each other. In some embodiments, guard ring 104 surrounds and abuts array area 10a.

As shown in FIG. 2A, the semiconductor structure 100 includes a substrate 108, including an array region 10a and a surrounding region 10b. The substrate 108 may be a semiconductor substrate, which may include element semiconductors, such as silicon (Si), germanium (Ge), etc.; compound semiconductors, such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), phosphorus Gallium (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors, such as silicon germanium alloy (SiGe), gallium arsenic phosphorus alloy (GaAsP), arsenic aluminum indium Alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic indium gallium alloy (GaInAs), phosphorus indium gallium alloy (GaInP), phosphorus indium gallium arsenic alloy (GaInAsP), or a combination of the above. In addition, the substrate 108 may also be a semiconductor on insulator (SOI). The substrate 108 may be of N-type or P-type conductivity type. N-type dopants may include phosphorus, arsenic, nitrogen, antimony ions, or combinations thereof. P-type dopants may include boron, gallium, aluminum, indium, boron trifluoride ions (BF ₃ ⁺ ), or combinations thereof.

Next, the oxide layer 110 is blanket-formed on the substrate 108 . In some embodiments, oxide layer 110 includes an oxide such as silicon oxide. The oxide layer 110 may be formed by a deposition process, such as a chemical vapor deposition process, a spin coating process, a sputtering process, a thermal oxidation process, or a combination thereof.

Next, a bottom layer 112 is formed blanketingly on the oxide layer 110 . The bottom layer 112 can serve as an etch stop layer for subsequent etching processes. The material of the bottom layer 112 and the oxide layer 110 can be made of different materials and have etching selectivity ratios. In some embodiments, bottom layer 112 includes polysilicon. The bottom layer 112 may be formed by a deposition process, such as a chemical vapor deposition process, a spin coating process, a sputtering process, or a combination thereof.

Subsequently, the barrier layer 114 is blanket-formed on the bottom layer 112 . The barrier layer 114 and the bottom layer 112 can be made of different materials and have etching selectivity ratios. In some embodiments, barrier layer 114 is in direct contact with bottom layer 112 . In some embodiments, barrier layer 114 includes a nitride, such as silicon nitride. Deposition processes such as chemical vapor deposition processes, such as chemical vapor deposition processes, spin coating processes, sputtering The barrier layer 114 is formed by a process, or a combination thereof.

Next, a photoresist layer 116 is formed on the barrier layer 114, and a photolithography process is used to form a pattern of the photoresist layer 116. In some embodiments, the pattern of the photoresist layer 116 surrounds the array area 10a and exposes the barrier layer 114 on the periphery of the array area 10a and the surrounding area 10b. The lithography process may include coating of photoresist (e.g. spin coating), soft baking, mask alignment, pattern exposure, post-exposure baking, developing photoresist, cleaning and drying (e.g. hard baking) )), other suitable technologies, or a combination of the above.

Next, as shown in Figure 2B, using the photoresist layer 116 as a mask, the barrier layer 114 is patterned to form a barrier structure 114'. In some embodiments, barrier structure 114 is located within surrounding area 10b. In some embodiments, sidewalls 114S of barrier structure 114' are aligned with interface 10i of array region 10a and surrounding region 10b. In some embodiments, the sidewalls 114S of the barrier structure 114' are vertically aligned with the sidewalls 10bS of the surrounding region 10b and the sidewalls 10aS of the array region 10a.

Next, as shown in Figure 2C, an intermediate layer 118 is formed to cover the bottom layer 112 and the barrier structure 114'. In some embodiments, the top surface of intermediate layer 118 is higher than the top surface of barrier structure 114'. In some embodiments, the intermediate layer 118, the barrier structure 114' and the bottom layer 112 are made of different materials and have etching selectivity ratios. In some embodiments, the intermediate layer 118 includes carbon, such as spin-on carbon (SOC). The intermediate layer 118 can be formed by a spin coating process, a deposition process, a sputtering process, or a combination of the above.

Next, a top layer 120 is blanket-formed on the middle layer 118 . The top layer 120 can serve as an etch stop layer for subsequent etching processes. The top layer 120 may be made of the same material as the bottom layer 112 . In some embodiments, top layer 120 includes polysilicon. The top layer 120 may be formed by a deposition process, such as a chemical vapor deposition process, a spin coating process, a sputtering process, or a combination thereof.

A three-layer mask structure 121 is formed on the oxide layer 110 . The three-layer mask structure 121 may include a bottom layer 112, a middle layer 118, and a top layer 120. In some embodiments, the barrier structure 114' is formed in the intermediate layer 118, and the intermediate layer 118 covers the barrier structure 114'.

Next, a patterned mask layer 122 is formed on the top layer 120 of the three-layer mask structure 121 . The patterned mask layer 122 may define the location of the active area array 102 in the array area 10a, such as the location of the lines forming the active area 102. In some embodiments, patterned mask layer 122 includes an oxide such as silicon oxide. In some embodiments, the pattern of patterned mask layer 122 is located in array area 10a and extends directly over barrier structure 114' in surrounding area 10b. In some embodiments, the pattern of patterned mask layer 122 vertically overlaps barrier structure 114'. The pattern of the patterned mask layer 122 has a pitch of 122aS in the array area 10a, and the pattern of the patterned mask layer 122 has a pitch of 122bS in the surrounding area 10b. In some embodiments, spacing 122aS is approximately equal to spacing 122bS.

Next, as shown in FIG. 2D , a three-layer photoresist structure 124 is formed on the patterned mask layer 122 . The three-layer photoresist structure 124 may include a bottom layer 126, an intermediate layer 128, and a top layer 130. The bottom layer 126 may include carbon, such as spin-on carbon material, the middle layer 128 may include a spin on silicon anti-reflection coating (SOSA), and the top layer 130 may include photoresist. The top layer 130 may also be referred to as the patterned photoresist layer 130 . The bottom layer 126 can be formed on the top layer 120 and the patterned mask layer 122 of the three-layer mask structure 121 through a spin coating process, a deposition process, a sputtering process, or a combination thereof. The bottom layer 126 may cover the sidewalls and top surface of the patterned mask layer 122 . The intermediate layer 128 can be blanket-formed on the bottom layer 126 by a deposition process or a spin coating process. The top layer 130 can be formed on the middle layer 128 by a spraying process, a spin coating process, or a deposition process, and the top layer 130 can be patterned.

The patterned photoresist layer 130 includes a first part 130a and a second part 130b. The first portion 130a may define the location of the active area array 102, such as a line cutting off the active area 102. Therefore, the first portion 130 a of the patterned photoresist layer 130 is different from the pattern of the mask layer 122 and partially overlaps with the pattern of the patterned mask layer 122 to form the active area array 102 . The second portion 130b of the patterned photoresist layer 130 may define a pattern in the surrounding area 10b, forming the surrounding structure 106 in FIG. 1 . In some embodiments, the active region array 102 and surrounding structures 106 are formed with the same patterned photoresist layer 130 definition.

The first portion 130a of the patterned photoresist layer 130 is located directly over the blocking structure 114' in the array area 10a and surrounding area 10b. The first portion 130a of the patterned photoresist layer 130 is in the array area The pitch in 10a is 130aaS, and the pitch of the first portion 130a of the patterned photoresist layer 130 in the surrounding area 10b is 130abS. In some embodiments, due to the proximity effect caused by the edge of the array, the spacing 130abS is not equal to the spacing 130aaS, and the spacing 130abS is greater than the spacing 130aaS.

Next, as shown in FIG. 2E , the patterned photoresist layer 130 and the patterned mask layer 122 are used as masks to pattern the bottom layer 112 . Through photolithography and etching processes, the patterned photoresist layer 130 and the patterned mask layer 122 can be sequentially transferred to the bottom layer 112 as a mask pattern. For example, the patterned photoresist layer 130 can be used as an etching mask, the intermediate layer 128 can be patterned to transfer the pattern of the patterned photoresist layer 130 to the intermediate layer 128 , and the patterned light can be removed while patterning the intermediate layer 128 resistive layer 130. Next, the intermediate layer 128 is used as an etching mask, and the bottom layer 126 and the patterned mask layer 122 are patterned and etched to transfer the pattern of the patterned photoresist layer 130 to the bottom layer 126 and the patterned mask layer 122 . At this time, the pattern of the active area array 102 is formed in the patterned mask layer 122 , and the pattern of the surrounding structure 106 is formed in the bottom layer 126 .

Next, using the pattern of the patterned mask layer 122 as an etching mask, the top layer 120 is patterned and etched, and the patterned mask layer 122 is removed when the top layer 120 is patterned. Next, using the pattern of the top layer 120 as an etching mask, the middle layer 118 is patterned and etched, and the top layer 120 is removed when the middle layer 118 is patterned. Since the barrier layer 114 and the intermediate layer 118 have an etching selectivity ratio, the patterns of the patterned photoresist layer 130 and the patterned mask layer 122 directly above the barrier layer 114 are not formed in the intermediate layer 118 .

Then, using the intermediate layer 118 and the barrier layer 114 as etching masks, the bottom layer 112 is patterned and etched, and the intermediate layer 118 is removed when the bottom layer 112 is patterned. Since the barrier layer 114 has an etching selectivity with the bottom layer 112 and the intermediate layer 118 , the barrier layer 114 remains above the bottom layer 112 . In some embodiments, since the barrier layer 114 is formed in the three-layer mask structure 121 , the patterns of the patterned photoresist layer 130 and the patterned mask layer 122 directly above the barrier layer 114 are not transferred to the bottom layer 112 . The underlying layer 112 directly beneath the barrier layer 114 forms a pattern of guard rings 104 .

Next, as shown in Figure 2F, the barrier structure 114' is removed and the bottom layer 112 underneath is exposed. The barrier structure 114' may be removed by a wet etching process or a dry etching process. In some embodiments, the barrier structure 114' is removed using a wet etching process, including using a phosphoric acid (H ₃ PO ₄ ) etching solution.

Next, as shown in FIG. 2G , the substrate 108 is patterned using the bottom layer 112 as a mask. The bottom layer 112 can be used as an etching mask. After the oxide layer 110 is patterned and the bottom layer 112 is removed, the substrate 108 is patterned using the oxide layer pattern 110 as an etching mask. The substrate 108 includes a first portion 102 , a second portion 104 , and a third portion 106 . The first portion 102 of the substrate 108 is located in the array area 10a and may be the active area array 102. The width 102W of each active area 102 in the active area array 102 is approximately the same. Additionally, each portion of each active region 102 has a substantially equal height 102H. The second portion 104 of the substrate 108 is located in the surrounding area 10b and may be the guard ring 104 . The guard ring 104 surrounds the active area array 102 and is in contact with the interface between the array area 10a and the surrounding area 10b. In some embodiments, the width 104W of the guard ring 104 is greater than the width 102W of each active region 102 . In some embodiments, the width 104W of the guard ring 104 ranges from about 150 nm to about 400 nm. The ratio of the width 104W of the guard ring 104 to the width 102W of each active region 102 ranges from about 3 to about 8. In some embodiments, guard ring 104 has a flat upper surface, and each portion of guard ring 104 has a substantially equal height 104H.

The third portion 106 of the substrate 108 is located in the surrounding area 10b and may be the surrounding structure 106 . In some embodiments, the width 104W of the guard ring 104 is greater than the width 106W of the surrounding structure 106 .

Next, as shown in FIG. 2H , a shallow trench isolation structure 132 is formed in the trench between each active region 102 , and the sidewalls and bottom of the shallow trench isolation structure 132 may form a liner. Next, word lines 134 are formed on and between the shallow trench isolation structures 132 . Word line 134 may include a gate dielectric layer, a barrier layer, and a conductive layer. Next, the trenches above the word lines 134 are filled with isolation material 136 .

As mentioned above, by forming the blocking structure in the surrounding area abutting the array area, and extending the pattern of the patterned photoresist layer forming the active area array directly above the blocking structure, the active area array photoresist pattern generates adjacent The edge portion of the effect can be located directly above the barrier structure. Therefore, when patterning the substrate, the barrier structure can block the proximity effect at the edge of the array pattern in the active area, so that in the array area Each active area in the domain is approximately the same size. In this way, the cost and time of optical proximity effect correction can be saved. In addition, the substrate underneath the barrier structure can simultaneously form a protective ring.

10a:Array area

10b: Surrounding area

108:Substrate

110:Oxide layer

112: Bottom floor

114’: blocking structure

118:Middle layer

120:Top layer

121: Three-layer curtain structure

122:Curtain layer

122aS, 122bS: spacing

124: Three-layer photoresist structure

126: Bottom floor

128:Middle layer

130: Photoresist layer

130a:Part 1

130b:Part 2

130aaS,130abS: spacing

Claims (12)

A method of forming a semiconductor structure, including: forming a substrate, including an array area and a surrounding area; forming a bottom layer on the substrate; forming a barrier structure on the bottom layer, wherein the barrier structure is located in the surrounding area in; covering an intermediate layer on the bottom layer and the barrier structure; forming a patterned photoresist layer on the intermediate layer, a first portion of the patterned photoresist layer is located in the array area and the surrounding area directly above the barrier structure; sequentially transfer a pattern of the patterned photoresist layer to the bottom layer, wherein the pattern of the patterned photoresist layer directly above the barrier structure is not formed on the bottom layer; remove the a barrier structure; and patterning the substrate, wherein the substrate includes a first part, a second part, and a third part, the first part of the substrate is located in the array area and is an active area array, and the substrate The second part is located in the surrounding area and is a protective ring. The third part of the substrate is located in the surrounding area and is a surrounding structure. The method of forming a semiconductor structure as claimed in claim 1, wherein a side wall of the barrier structure is aligned with an interface between the array region and the surrounding region. The method of forming a semiconductor structure as claimed in claim 1 further includes: forming a patterned mask layer on the intermediate layer, a pattern of the patterned mask layer being located in the array area and extending to the surrounding area Just above the barrier structure; wherein a pitch of the pattern of the patterned mask layer in the surrounding area is substantially equal to a pitch in the array area. The method of forming a semiconductor structure as claimed in claim 1, wherein a pitch of the patterned photoresist layer in the surrounding area is greater than a pitch in the array area. The method of forming a semiconductor structure as claimed in claim 1, wherein the barrier structure has an etching selectivity ratio with the bottom layer and the intermediate layer. The method of forming a semiconductor structure of claim 1, wherein the intermediate layer includes carbon, the barrier structure includes nitride, and the bottom layer includes polycrystalline silicon. The method of forming a semiconductor structure of claim 3, wherein the patterns of the patterned mask layer and the patterned photoresist layer are different, and the patterns of the patterned mask layer and the patterned photoresist layer partially overlap. The method of forming a semiconductor structure as claimed in claim 3, wherein the patterned mask layer defines the position of a line forming the active area array in the array area, and the first part of the patterned photoresist layer defines a line that cuts off the active area array. The position of the line. A semiconductor structure includes: a substrate including an array area and a surrounding area; a protective ring located in the surrounding area, abutting and surrounding the array area; and an active area array including a plurality of active areas located in the surrounding area. In the array area; a plurality of word lines located in and between a plurality of active areas; and a surrounding structure located in the surrounding area; wherein the guard ring and the surrounding structure are separated from each other. The semiconductor structure of claim 9, wherein in a cross-sectional view parallel to an edge of the array region, a width of the guard ring is greater than a width of each active region, and the width of the guard ring is greater than the surrounding structure of a width. The semiconductor structure of claim 9, wherein in a cross-sectional view parallel to an edge of the array region, the width of each active region is substantially equal. The semiconductor structure of claim 9, wherein in a cross-sectional view parallel to an edge of the array region, a width ratio of the guard ring to each active region ranges from about 3 to about 8.

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