CN114068400A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a layer to be etched; forming a plurality of first barrier structures on the surface of the layer to be etched; forming a plurality of second barrier structures on the surface of the layer to be etched, wherein the materials of the first barrier structures are different from those of the second barrier structures; forming a first patterning layer, wherein the first patterning layer is provided with a plurality of first openings, and each first opening at least exposes partial surfaces of 1 first barrier structure and 1 second barrier structure; etching the first blocking structure by taking the first patterning layer as a mask; forming a second patterned layer, wherein the second patterned layer is provided with a plurality of second openings, and each second opening at least exposes partial surfaces of 1 first barrier structure and 1 second barrier structure; and etching the second blocking structure by taking the second patterning layer as a mask. Therefore, the difficulty of the manufacturing process of the semiconductor structure is reduced.

Description

Method for forming semiconductor structure

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.

Background

With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance is improved along with the progress of miniaturization of devices. Increasingly advanced processes require as many devices as possible to be implemented in as small an area as possible.

In ultra-large scale integrated circuits, the use of metal interconnect layers is one of the methods for achieving electrical interconnection between devices. In general, in a high-density Metal interconnection layer, a Metal-cut layer (Metal-cut layer) is used to insulate adjacent Metal interconnection layers, so that the distance between ends of adjacent Metal interconnection layers needs to be smaller than the exposure limit size of an exposure process, so as to increase the density of the Metal interconnection layers and improve the integration level of an integrated circuit.

However, the process difficulty of the conventional semiconductor structure is still large.

Disclosure of Invention

The invention provides a method for forming a semiconductor structure, which aims to reduce the difficulty of the process for manufacturing the semiconductor structure.

In order to solve the above technical problem, an aspect of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming a plurality of first barrier structures on the surface of the layer to be etched; forming a plurality of second barrier structures on the surface of the layer to be etched, wherein the materials of the first barrier structures are different from those of the second barrier structures; forming a first patterning layer, wherein the first patterning layer is provided with a plurality of first openings, and each first opening at least exposes partial surfaces of 1 first barrier structure and 1 second barrier structure; etching the first blocking structure by taking the first patterning layer as a mask; forming a second patterned layer, wherein the second patterned layer is provided with a plurality of second openings, and each second opening at least exposes partial surfaces of 1 first barrier structure and 1 second barrier structure; and etching the second blocking structure by taking the second patterning layer as a mask.

Optionally, the method further includes: before forming the first patterning layer and the second patterning layer, forming a plurality of third barrier structures on the surface of the layer to be etched, wherein the third barrier structures comprise a first barrier layer and a second barrier layer positioned on part of the surface of the first barrier layer, the material of the first barrier layer is the same as that of the first barrier structure, and the material of the second barrier layer is the same as that of the second barrier structure.

Optionally, at least 1 of the first openings further exposes a portion of the surface of at least 1 of the third blocking structures.

Optionally, at least 1 of the second openings further exposes a portion of the surface of at least 1 of the third blocking structures.

Optionally, a first etching process is adopted, the first patterned layer is used as a mask, and a first blocking structure is etched, the first etching process has a first etching rate for the material of the first blocking structure, the first etching process has a second etching rate for the material of the second blocking structure, and the first etching rate is greater than the second etching rate.

Optionally, a ratio of the first etching rate to the second etching rate is greater than 5: 1.

Optionally, a second etching process is adopted, the second patterned layer is used as a mask, and the second blocking structure is etched, the second etching process has a third etching rate for the material of the first blocking structure, the second etching process has a fourth etching rate for the material of the second blocking structure, and the fourth etching rate is greater than the third etching rate.

Optionally, a ratio of the fourth etching rate to the third etching rate is greater than 5: 1.

Optionally, the method for forming the first barrier structure includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of first doping regions in the first barrier material layer; and etching the first barrier material layer after the first doping region is formed until the surface of the layer to be etched is exposed.

Optionally, the method for forming the first barrier layer includes: before the first barrier material layer is etched, a plurality of third doping regions are formed in the first barrier material layer, and ions doped in the third doping regions are the same as the ions doped in the first doping regions.

Optionally, the method for forming the second barrier structure includes: after the first barrier structure and the first barrier layer are formed, forming a second barrier material layer on the surface of the layer to be etched, the surface of the first barrier structure and the surface of the first barrier layer; forming a plurality of second doped regions in the second barrier material layer on the surface of the layer to be etched; and etching the second barrier material layer after the second doped region is formed until the surface of the layer to be etched, the surface of the first barrier structure and the surface of the first barrier layer are exposed.

Optionally, the method for forming the second barrier layer includes: before etching the second barrier material layer, forming a plurality of fourth doping regions in the second barrier material layer on the surface of part of the first barrier layer, wherein ions doped in the fourth doping regions are the same as the ions doped in the second doping regions.

Optionally, the material of the first barrier structure includes: titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

Optionally, the material of the second barrier structure includes: titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

Optionally, the method further includes: taking the first patterning layer as a mask, etching the first blocking structure, then continuing to etch the layer to be etched by taking the first patterning layer as the mask, and forming a plurality of first interconnection openings in the layer to be etched, wherein the first interconnection openings expose the side wall surfaces of the second blocking structure; a first interconnect structure is formed within each first interconnect opening.

Optionally, the method further includes: taking the second patterning layer as a mask, etching the second blocking structure, and then continuing to etch the layer to be etched by taking the second patterning layer as the mask, so as to form a plurality of second interconnection openings in the layer to be etched, wherein the second interconnection openings expose the side wall surfaces of the first blocking structure; a second interconnect structure is formed within each second interconnect opening.

Optionally, the method further includes: taking the first patterning layer as a mask, etching the first blocking structure, then continuing to etch the layer to be etched by taking the first patterning layer as the mask, and forming a plurality of third interconnection openings in the layer to be etched, wherein the third interconnection openings expose the side wall surfaces of at least one of the second blocking structure and the second blocking layer; a third interconnect structure is formed within each third interconnect opening.

Optionally, the method further includes: taking the second patterning layer as a mask, etching the second barrier structure, and then continuing to etch the layer to be etched by taking the second patterning layer as the mask, so as to form a plurality of fourth interconnection openings in the layer to be etched, wherein the fourth interconnection openings expose the side wall surfaces of at least one of the first barrier structure and the first barrier layer; a fourth interconnect structure is formed within each fourth interconnect opening.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, because the material of the first blocking structure is different from that of the second blocking structure, after the etching process parameters are adjusted, the first blocking structure can be selectively etched by taking the first patterning layer as a mask, and similarly, the second blocking structure can be selectively etched by taking the second patterning layer as a mask. Therefore, the layer to be etched can be etched by taking the first blocking structure and the second patterning layer as masks, and meanwhile, the second blocking structure which is not exposed is blocked (the exposed second blocking structure is selectively etched and removed), and further, the second blocking structure with the longer length can be formed. Similarly, the second blocking structure and the first patterning layer can be used as masks to etch the layer to be etched, and meanwhile, the exposed first blocking structure is not blocked (the exposed first blocking structure is selectively etched and removed), so that the first blocking structure with a long length can be formed. The first blocking structure and the second blocking structure which are longer in length can be formed, so that the requirement on the alignment precision of the patterns in the length direction of the first blocking structure and the length direction of the second blocking structure is reduced, the process window for forming the first blocking structure and the second blocking structure is increased, the process difficulty for manufacturing the first blocking structure and the second blocking structure is reduced, and the process difficulty for manufacturing the semiconductor structure is further reduced.

Drawings

FIGS. 1-2 are schematic structural diagrams of steps in a process for forming a semiconductor structure;

fig. 3 to 22 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.

Detailed Description

As described in the background, the process difficulty of the conventional semiconductor structure is still large. The analysis will now be described with reference to specific examples.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1-2 are schematic top views of steps in a process for forming a semiconductor structure.

Referring to fig. 1, a layer to be etched 100 is provided, where the layer to be etched 100 includes a first region I and a second region II arranged along a first direction X.

With continued reference to fig. 1, a first blocking structure 111 crossing the first region I and a second blocking structure 112 crossing the second region II are formed on the to-be-etched 100.

Referring to fig. 2, an interconnection patterning layer (not shown) is formed on the surface of the layer to be etched 100, and the interconnection patterning layer exposes the layer to be etched 100, the first barrier structures 111 and the second barrier structures 112 in the first region I and the second region II; and etching the layer to be etched 100 by using the interconnection patterning layer, the first blocking structures 111 and the second blocking structures 112 as masks, forming a plurality of first interconnection openings 121 and a plurality of second interconnection openings 122 in the layer to be etched 100, wherein adjacent first interconnection openings 121 are spaced by the first blocking structures 111, and adjacent second interconnection openings 122 are spaced by the second blocking structures 112.

After forming the first interconnect openings 121 and the second interconnect openings 122, a first interconnect structure (not shown) is formed in each of the first interconnect openings 121, and a second interconnect structure (not shown) is formed in each of the second interconnect openings 122.

However, in the above method, on the one hand, in order to reduce the pitch between the adjacent first interconnect structures, the width dimension of the first barrier structures 111 is smaller in the direction perpendicular to the first direction X, and likewise, the width dimension of the second barrier structures 112 is smaller; on the other hand, in order to form the second interconnect opening 122, the first interconnect structure 111 cannot block the layer to be etched 100 in the second region II, and similarly, the second interconnect structure 112 cannot block the layer to be etched in the first region I, so that the length dimension of the first barrier structure 111 and the length dimension of the second barrier structure 112 are smaller along the first direction X. Since the width and length of the first barrier structure 111 and the second barrier structure 112 are small, when the first barrier structure 111 and the second barrier structure 112 are formed, in the first direction X and the direction perpendicular to the first direction X, the patterns of the first barrier structure 111 and the second barrier structure 112 need to have high overlay accuracy, so that when the first barrier structure 111 and the second barrier structure 112 are formed, a process window is small, and the process difficulty of forming the first barrier structure 111 and the second barrier structure 112 is large.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which a first blocking structure and a second blocking structure with different materials are formed on a surface of a layer to be etched, and the first blocking structure and the second blocking structure are selectively etched by using a first patterning layer and a second patterning layer as masks, so that requirements for overlay accuracy of patterns in a length direction of the first blocking structure and a length direction of the second blocking structure are reduced, process windows for forming the first blocking structure and the second blocking structure are increased, and process difficulty for manufacturing the first blocking structure and the second blocking structure is reduced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 22 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention, providing a layer to be etched 200.

In this embodiment, the layer to be etched includes a substrate (not shown) and a dielectric layer (not shown) on the substrate.

The material of the substrate comprises a semiconductor material.

In this embodiment, the material of the substrate comprises silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.

In this embodiment, the substrate has a semiconductor device (not shown) therein, and the semiconductor device includes one or both of a PMOS transistor and an NMOS transistor. The substrate further includes a substrate interconnect structure (not shown) electrically connected to the semiconductor device, and an insulating layer (not shown) surrounding the semiconductor device and the substrate interconnect structure.

The material of the dielectric layer includes a dielectric material, such as silicon oxide or silicon nitride.

Then, a plurality of first barrier structures and a plurality of second barrier structures are formed on the surface of the layer to be etched 200.

In this embodiment, the method for forming a semiconductor structure further includes: and forming a plurality of third barrier structures on the surface of the layer to be etched 200, wherein the third barrier structures comprise a first barrier layer and a second barrier layer positioned on the surface of part of the first barrier layer, the material of the first barrier layer is the same as that of the first barrier structure, and the material of the second barrier layer is the same as that of the second barrier structure.

In other embodiments, the third barrier structure is not formed.

Please refer to fig. 4 to fig. 13 for a process of forming the first barrier structures, the second barrier structures, and the third barrier structures.

Referring to fig. 4 and 5, fig. 4 is a schematic cross-sectional view taken along the direction X-X1 in fig. 5, wherein a first barrier material layer 210 is formed on the surface of the layer to be etched 200; first doped regions 211 are formed within the first barrier material layer 210.

The first doped region 211 provides a material for forming a first barrier structure.

It should be noted that fig. 5 schematically shows 1 first doping region, and the number of the first doping regions may be 1 or multiple. And when the number of the first doping regions is multiple, the shape of each first doping region may be different according to design requirements.

In the present embodiment, the process of forming the first barrier material layer 210 includes a spin-on process or a deposition process, such as a chemical vapor deposition process (CVD), a physical vapor deposition Process (PVD), or an atomic layer deposition process (ALD).

In this embodiment, the method for forming a plurality of the first doping regions 211 includes: forming a first barrier patterning layer (not shown) on the surface of the first barrier material layer 210, wherein the first barrier patterning layer has a plurality of first barrier openings (not shown) therein, and the first barrier openings expose a portion of the surface of the first barrier material layer; the first blocking material layer 210 is ion-doped by using the first blocking patterning layer as a mask to form a plurality of first doping regions 211.

In other embodiments, when the number of the first barrier structures is multiple, the first doping process is performed on the first barrier material layer multiple times to form multiple first doping regions. Each first doping process comprises: forming a first barrier patterning layer on the surface of the first barrier material layer, wherein the first barrier patterning layer is internally provided with a plurality of first barrier openings, and a part of the surface of the first barrier material layer is exposed by the first barrier openings; performing a first ion doping step on the first barrier material layer by taking the first barrier patterning layer as a mask to form a part of first doping regions in the plurality of first doping regions; after the first doped region is formed, the first blocking patterning layer is removed.

Since the plurality of first doping regions are formed through a plurality of first doping processes, one first barrier patterning layer is formed in each first doping process. When the distance between different first blocking structures is small, the first doping regions corresponding to the first blocking structures can be formed in different first doping processes, that is, the first blocking openings with the closer distance are formed in different first blocking patterning layers, so that the defects of short circuits or poor pattern size precision and the like caused by the closer distance between different first blocking openings in the exposure process of the patterns forming the first blocking openings can be reduced. The pattern accuracy of the first blocking opening is improved, and thus, the pattern accuracy of the first doping region and the first blocking structure is improved.

In this embodiment, the process of the first ion doping step includes an ion implantation process.

In this embodiment, the first barrier pattern layer is removed after the first doping region 211 is formed.

In this embodiment, after forming the first doping regions 211, third doping regions 213 are formed in the first barrier material layer 210, and ions doped in the third doping regions 213 are the same as ions doped in the first doping regions 211.

The third doped region 213 provides material for forming a first barrier layer.

Since the ions doped in the third doped region 213 are the same as the ions doped in the first doped region 211, the material of the first barrier layer can be made the same as the material of the first barrier structure.

The purpose of making the material of the first barrier layer the same as the material of the first barrier structure is to: when the first barrier structure is subsequently and selectively etched, the first barrier layer can be simultaneously and selectively etched.

It should be noted that fig. 5 schematically shows 2 third doping regions, and the number of the third doping regions may be 1 or multiple. And when the number of the third doping regions is multiple, the shape of each third doping region may be different according to design requirements.

The method of forming the plurality of third doped regions 213 includes: forming a third barrier patterning layer (not shown) on the surface of the first barrier material layer 210, wherein the third barrier patterning layer has a plurality of third barrier openings (not shown) therein, and the third barrier openings expose a portion of the surface of the first barrier material layer; using the third barrier patterning layer as a mask, a third ion doping step is performed on the first barrier material layer 210 to form a plurality of third doped regions 213.

Since the first barrier patterning layer and the third barrier patterning layer are formed respectively, that is, the first barrier opening and the third barrier opening are formed in different barrier patterning layers, so that the defects of short circuits or poor dimensional accuracy of patterns and the like caused by the close distance between the first barrier opening and the third barrier opening in the exposure process of the patterns for forming the first barrier opening and the third barrier opening can be reduced. The pattern accuracy of the first blocking opening and the third blocking opening is improved, and thus, the pattern accuracy of the first doping region 211 and the first blocking structure, and the third doping region 213 and the first blocking layer is improved.

In this embodiment, the process of the third ion doping step includes an ion implantation process, and the ions implanted into the first barrier material layer 210 in the third ion doping step are the same as the ions implanted into the first barrier material layer 210 in the first ion doping step. Thereby, it can be achieved that the ions doped in the third doped region 213 are the same as the ions doped in the first doped region 211.

In other embodiments, when the number of the first barrier layers is multiple, a third doping process is performed on the first barrier material layer multiple times to form a plurality of third doped regions. Each third doping process comprises: forming a third barrier patterning layer on the surface of the first barrier material layer, wherein the third barrier patterning layer is internally provided with a plurality of third barrier openings, and a part of the surface of the first barrier material layer is exposed by the third barrier openings; performing a third ion doping step on the first blocking material layer by taking the third blocking patterning layer as a mask to form at least 1 third doped region in the plurality of third doped regions; and removing the third barrier patterning layer after the third doped region is formed.

Since the plurality of third doping regions are formed through a plurality of third doping processes, one third barrier patterning layer is formed in each third doping process. When the distance between different third blocking structures is small, the third doped regions corresponding to the third blocking structures can be formed in different third doping processes, that is, the third blocking openings with the closer distance are formed in different third blocking patterning layers, so that the defects of short circuits or poor pattern size precision and the like caused by the closer distance between the different third blocking openings in the exposure process of the patterns forming the third blocking openings can be reduced. The pattern accuracy of the third barrier opening is improved, and thus, the pattern accuracy of the third doped region and the first barrier layer is improved.

In other embodiments, third doped regions are formed within the first barrier material layer prior to forming the first doped regions.

In other embodiments, a plurality of third doped regions are formed within the first barrier material layer while a plurality of first doped regions are formed. The method for simultaneously forming the first doped region and the third doped region comprises the following steps: forming a fifth barrier patterning layer on the surface of the first barrier material layer, wherein the fifth barrier patterning layer is internally provided with a plurality of first barrier openings and a plurality of third barrier openings, the first barrier openings are used for defining the pattern of the first doped region, and the third barrier openings are used for defining the pattern of the third doped region; and carrying out ion doping on the first barrier material layer by taking the fifth barrier patterning layer as a mask so as to form a plurality of first doping regions and a plurality of third doping regions.

In this embodiment, the third barrier patterning layer is removed after the third doped region 213 is formed.

Referring to fig. 6 and 7, fig. 6 is a schematic cross-sectional view taken along the direction X-X1 in fig. 7, after forming the first doping region 211 and the third doping region 213, the first barrier material layer 210 is etched until the surface of the layer to be etched 200 is exposed, and a plurality of first barrier structures 221 and a plurality of first barrier layers 223 are formed.

In this embodiment, the first barrier structures 221 and the first barrier layers 223 are made of the same material.

The materials of the first barrier structure 221 and the first barrier layer 223 include: titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

The process of etching the first barrier material layer 210 includes at least one of a dry etching process or a wet etching process.

In another embodiment, the third barrier structure is not formed, and the method of forming the number of first barrier structures includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of mutually-separated first blocking mask structures on the surface of the first blocking material layer; and etching the first barrier material layer by taking the first barrier mask structure as a mask until the surface of the layer to be etched is exposed.

In other embodiments, a method of forming a number of first barrier structures and a number of first barrier layers includes: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of first blocking mask structures and a plurality of third blocking mask structures which are separated from each other on the surface of the first blocking material layer; and etching the first barrier material layer by taking the first barrier mask structure and the third barrier mask structure as masks until the surface of the layer to be etched is exposed.

Referring to fig. 8 to 10, fig. 8 is a schematic cross-sectional view taken along the direction X-X1 in fig. 10, fig. 9 is a schematic cross-sectional view taken along the direction Y-Y1 in fig. 10, after forming the first barrier structure 221 and the first barrier layer 223, a second barrier material layer 230 is formed on the surface of the layer to be etched 200, the surface of the first barrier structure 221 and the surface of the first barrier layer 223; second doping regions 232 are formed in the second barrier material layer 230 on the surface of the layer to be etched 200.

Specifically, the forming of the second doping regions 232 in the second barrier material layer 230 on the surface of the layer to be etched 200 refers to: second doped regions 232 are formed in the second barrier material layer 230 outside the second barrier material layer 230 on the first barrier structures 221 and the first barrier layers 223.

In the present embodiment, the second doping region 232 is located between the first barrier structure 221 and the first barrier layer 223.

The second doped region 232 provides a material for forming a second barrier structure.

It should be noted that fig. 10 schematically shows 2 second doping regions, and the number of the second doping regions may be 2, or may be 1 or more than 2. And when the number of the second doping regions is multiple, the shapes of the second doping regions may be different according to design requirements.

In the present embodiment, the process of forming the second barrier material layer 230 includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In this embodiment, the method for forming a plurality of the second doping regions 232 includes: forming a second barrier patterning layer (not shown) on the surface of the second barrier material layer 230, wherein the second barrier patterning layer has a plurality of second barrier openings (not shown) therein, and the second barrier openings expose a portion of the surface of the second barrier material layer; the second blocking material layer 230 is ion-doped by using the second blocking patterned layer as a mask to form a plurality of second doping regions 232.

In other embodiments, when the number of the second barrier structures is multiple, the second barrier material layer is subjected to a plurality of second doping processes to form a plurality of second doping regions. Each second doping process comprises: forming a second barrier patterning layer on the surface of the second barrier material layer, wherein the second barrier patterning layer is internally provided with a plurality of second barrier openings, and part of the surface of the second barrier material layer is exposed out of the second barrier openings; performing a second ion doping step on the second barrier material layer by taking the second barrier patterning layer as a mask to form at least 1 second doping region in the plurality of second doping regions; and removing the second blocking patterning layer after the second doping region is formed.

Since the plurality of second doping regions are formed through a plurality of second doping processes, one second barrier patterning layer is formed in each second doping process. When the distance between different second blocking structures is smaller, the second doping regions corresponding to the second blocking structures can be formed in different second doping processes, that is, the second blocking openings with closer distances are formed in different second blocking patterning layers, so that the defects of short circuits or poor pattern size precision and the like caused by closer distances between different second blocking openings in the exposure process of the patterns forming the second blocking openings can be reduced. The pattern accuracy of the second barrier opening is improved, and thus, the pattern accuracy of the second doping region and the second barrier structure is improved.

In this embodiment, the process of the second ion doping step includes an ion implantation process.

In this embodiment, the second barrier pattern layer is removed after the second doping region 232 is formed.

In the present embodiment, after forming the second doping regions 232, fourth doping regions 234 are formed in the second barrier material layer 230 on a portion of the surface of the first barrier layer 223, and ions doped in the fourth doping regions 234 are the same as ions doped in the second doping regions 232.

The fourth doped region 234 provides material for forming a second barrier layer.

Since the ions doped in the fourth doping region 234 are the same as the ions doped in the second doping region 232, the material of the second barrier layer can be the same as the material of the second barrier structure.

The purpose of making the material of the second barrier layer the same as the material of the second barrier structure is: and when the second barrier structure is subsequently and selectively etched, the second barrier layer can be simultaneously and selectively etched.

The method of forming the plurality of fourth doping regions 234 includes: forming a fourth barrier patterning layer (not shown) on the surface of the second barrier material layer 230, wherein the fourth barrier patterning layer has a plurality of fourth barrier openings (not shown) therein, and the fourth barrier openings expose a portion of the surface of the second barrier material layer 230 on the surface of the first barrier layer 223; using the fourth barrier patterning layer as a mask, a fourth ion doping step is performed on the second barrier material layer 230 to form a plurality of fourth doped regions 234.

Since the second barrier patterning layer and the fourth barrier patterning layer are formed respectively, that is, the second barrier opening and the fourth barrier opening are formed in different barrier patterning layers, so that the defects of short circuits or poor dimensional accuracy of patterns and the like caused by the close distance between the second barrier opening and the fourth barrier opening in the exposure process of the patterns for forming the second barrier opening and the fourth barrier opening can be reduced. The pattern accuracy of the second barrier opening and the fourth barrier opening is improved, and thus, the pattern accuracy of the second doping region 232 and the second barrier structure, and the fourth doping region 234 and the second barrier layer is improved.

In this embodiment, the process of the fourth ion doping step includes an ion implantation process, and the ions implanted into the second barrier material layer 230 in the fourth ion doping step are the same as the ions implanted into the second barrier material layer 230 in the second ion doping step. Thereby, it can be achieved that the ions doped in the fourth doping region 234 are the same as the ions doped in the second doping region 232.

In other embodiments, when the number of the second blocking layers is multiple, a fourth doping process is performed on the second blocking material layer multiple times to form a plurality of fourth doping regions. Each fourth doping process comprises: forming a fourth barrier patterned layer on the surface of the second barrier material layer, wherein the fourth barrier patterned layer is internally provided with a plurality of fourth barrier openings, and the fourth barrier openings expose the surface of the second barrier material layer on the partial surface of at least 1 first barrier layer; performing a fourth ion doping step on the second blocking material layer by taking the fourth blocking patterning layer as a mask to form at least 1 fourth doping region in a plurality of fourth doping regions; and removing the fourth blocking patterning layer after the fourth doped region is formed.

Since the plurality of fourth doping regions are formed through a plurality of fourth doping processes, one fourth barrier patterning layer is formed in each fourth doping process. When the distance between different fourth blocking structures is small, the fourth doping regions corresponding to the fourth blocking structures can be formed in different fourth doping processes, that is, the fourth blocking openings with the close distance are formed in different fourth blocking patterning layers, so that the defects of short circuits or poor pattern size precision and the like caused by the close distance between different fourth blocking openings in the exposure process of the patterns forming the fourth blocking openings can be reduced. The pattern accuracy of the fourth blocking opening is improved, and therefore, the pattern accuracy of the fourth doping region and the second blocking layer is improved.

In other embodiments, before forming the second doped regions, fourth doped regions are formed within the second barrier material layer.

In other embodiments, a plurality of fourth doped regions are formed within the second barrier material layer while a plurality of second doped regions are formed. The method for simultaneously forming the second doped region and the fourth doped region comprises the following steps: forming a sixth barrier patterning layer on the surface of the second barrier material layer, wherein the sixth barrier patterning layer is internally provided with a plurality of second barrier openings and a plurality of fourth barrier openings, the second barrier openings are used for defining the pattern of a second doping region, and the fourth barrier openings are used for defining the pattern of a fourth doping region; and carrying out ion doping on the second barrier material layer by taking the sixth barrier patterning layer as a mask so as to form a plurality of second doping regions and a plurality of fourth doping regions.

In the present embodiment, after the fourth doping region 234 is formed, the fourth barrier patterning layer is removed.

Referring to fig. 11 to 13, fig. 11 is a schematic cross-sectional view taken along the direction X-X1 in fig. 13, fig. 12 is a schematic cross-sectional view taken along the direction Y-Y1 in fig. 13, after the second doping region 232 and the fourth doping region 234 are formed, the second barrier material layer 230 is etched until the surface of the layer to be etched 200, the surface of the first barrier structure 221 and the surface of the first barrier layer 223 are exposed, and a plurality of second barrier structures 242 and a plurality of second barrier layers 244 are formed.

The first barrier layer 223 and the second barrier layer 224 on the surface of the first barrier layer 223 form a third barrier structure.

In the present embodiment, the second barrier structure 242 and the plurality of fourth barrier layers 244 are made of the same material.

The materials of the second barrier structure 242 and the fourth barrier layer 244 include: titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

The process of etching the second barrier material layer 230 includes at least one of a dry etching process or a wet etching process.

In another embodiment, the third barrier structure is not formed, and the method of forming the number of second barrier structures includes: forming a second barrier material layer on the surface of the layer to be etched; forming a plurality of second blocking mask structures which are separated from each other on the surface of the second blocking material layer; and etching the second barrier material layer by taking the second barrier mask structure as a mask until the surface of the layer to be etched is exposed.

In other embodiments, a method of forming a number of second barrier structures and a number of fourth barrier layers includes: forming a second barrier material layer on the surface of the layer to be etched, the surface of the first barrier structure and the surface of the first barrier layer; forming a plurality of second blocking mask structures and fourth blocking mask structures which are separated from each other on the surface of the second blocking material layer; and etching the second barrier material layer by taking the second barrier mask structure and the fourth barrier mask structure as masks until the surface of the layer to be etched, the surface of the first barrier structure and part of the surface of the first barrier layer are exposed.

Next, forming a first patterned layer having a plurality of first openings, each first opening exposing at least a portion of the surfaces of 1 first barrier structure 221 and 1 second barrier structure 242; etching the first blocking structure 221 by using the first patterning layer as a mask; forming a second patterned layer having a plurality of second openings, each second opening exposing at least a portion of the surfaces of 1 first barrier structure 221 and 1 second barrier structure 242; second blocking structure 242 is etched using the second patterned layer as a mask.

Since the first blocking structure 221 and the second blocking structure 242 are different, after the etching process parameters are adjusted, the first blocking structure 221 can be selectively etched by using the first patterning layer as a mask, and similarly, the second blocking structure 242 can be selectively etched by using the second patterning layer as a mask. Therefore, the layer to be etched 200 can be etched using the first blocking structure 221 and the second patterning layer as masks, and meanwhile, the second blocking structure 242 that is not exposed can be blocked (the exposed second blocking structure 242 is selectively etched and removed), so that the second blocking structure 242 with a longer length can be formed. Similarly, the layer to be etched 200 may be etched using the second blocking structure 242 and the first patterning layer as masks, while the exposed first blocking structure 221 is not blocked (the exposed first blocking structure 221 is selectively etched away), so that the first blocking structure 221 with a longer length may be formed. Because the first blocking structure 221 and the second blocking structure 242 with longer lengths can be formed, the requirement for the alignment precision of the patterns in the length direction of the first blocking structure 221 and the length direction of the second blocking structure 242 is reduced, the process window for forming the first blocking structure 221 and the second blocking structure 242 is increased, and the process difficulty for manufacturing the first blocking structure 221 and the second blocking structure 242 is reduced.

Since the first blocking layer 223 is made of the same material as the first blocking structure 221, and the second blocking layer 244 is made of the same material as the second blocking structure 242, when the third blocking structure surface is exposed by the first opening and the second opening, similarly, the first blocking layer 223 can be selectively etched while the first blocking structure 221 is selectively etched, and the exposed second blocking layer 244 can be selectively etched while the second blocking structure 242 is selectively etched, so that the first blocking layer 223 and the second blocking layer 224 with longer lengths can be formed, which is not described herein again.

It should be noted that the sequence between forming the first patterning layer and etching the first blocking structure 221 using the first patterning layer as a mask and forming the second patterning layer and etching the second blocking structure 242 using the second patterning layer as a mask does not affect the effect of the technical solution of the present invention. Therefore, after forming the first patterning layer and etching the first blocking structure 221 by using the first patterning layer as a mask, the second patterning layer may be formed and the second blocking structure 242 may be etched by using the second patterning layer as a mask. Alternatively, after forming the second patterning layer and etching the second blocking structure 242 with the second patterning layer as a mask, the first patterning layer may be formed and the first blocking structure 221 may be etched with the first patterning layer as a mask.

For convenience of understanding, in this embodiment, a first patterned layer is formed after forming a second patterned layer and etching the second blocking structure 242 by using the second patterned layer as a mask, and the first blocking structure 221 is etched by using the first patterned layer as a mask, for example, the detailed process is described with reference to fig. 14 to 21.

Referring to fig. 14 and 15, fig. 14 is a schematic cross-sectional view taken along a direction Y-Y1 in fig. 15, forming a second patterned layer 250, where the second patterned layer 250 has a plurality of second openings 251, and each second opening 251 exposes at least a portion of the surfaces of 1 first barrier structure 221 and 1 second barrier structure 242.

In this embodiment, at least 1 of the second openings 251 in the plurality of second openings 251 further exposes a portion of the surface of at least 1 third blocking structure.

In this embodiment, the method of forming the second patterned layer 250 includes: forming a second patterned material layer on the surface of the layer to be etched 200, the surface of the first barrier structure 221, the surface of the second barrier structure 242 and the surface of the third barrier structure; the second patterned material layer is exposed and developed to form the second patterned layer 250.

In this embodiment, the material of the second patterning layer 250 includes photoresist.

With continued reference to fig. 14 and fig. 15, the second barrier structure 242 is etched using the second patterned layer 250 as a mask.

In this embodiment, a second etching process is adopted, and the second patterning layer 250 is used as a mask to etch the second blocking structure 242, where the second etching process has a third etching rate for the material of the first blocking structure 221, the second etching process has a fourth etching rate for the material of the second blocking structure 242, and the fourth etching rate is greater than the third etching rate. Thereby, selective etch removal of second barrier structures 242 is achieved.

The ratio of the fourth etching rate to the third etching rate is 5:1 or more.

The ratio of the fourth etching rate to the third etching rate is too small, and when the second barrier structure 242 is etched, the exposed first barrier structure 221 is easily worn, so that it is not favorable for the second etching process to etch the layer to be etched 200 under the exposed first barrier structure 211 through the exposed first barrier structure 211 in the second etching process. Therefore, selecting a suitable ratio of the fourth etching rate to the third etching rate, that is, when the ratio of the fourth etching rate to the third etching rate is above 5:1, is beneficial to etching the second barrier structure 242 more selectively, so as to better block the second etching process from etching the layer to be etched 200 under the exposed first barrier structure 211 through the exposed first barrier structure 211 in the second etching process.

In this embodiment, when the second opening 251 exposes the surface of the third barrier structure, since the second barrier layer 244 is located on a portion of the surface of the first barrier layer 223, that is, the projection of the second barrier layer 244 on the surface of the layer to be etched 200 is within the projection range of the first barrier layer 223 on the surface of the layer to be etched 200, even if the second opening 251 exposes the surface of the second barrier layer 244 of the third barrier structure, the second etching process can be blocked from etching the layer to be etched 200 under the exposed third barrier structure by the first barrier layer 223 when the second barrier structure 242 is selectively etched.

The second etching process comprises at least one of a dry etching process or a wet etching process.

Referring to fig. 16 and 17, fig. 16 is a schematic cross-sectional view taken along a direction Y-Y1 in fig. 17, after etching the second barrier structure 242 by using the second patterning layer 250 as a mask, and then continuously etching the layer to be etched 200 by using the second patterning layer 250, the exposed first barrier structure 221 and the exposed first barrier layer 223 as masks, a plurality of fourth interconnect openings 252 are formed in the layer to be etched, and the fourth interconnect openings 252 expose sidewall surfaces of at least one of the first barrier structure 221 and the first barrier layer 223.

In the present embodiment, the second patterning layer 250 is removed after the fourth interconnect opening 252 is formed.

Referring to fig. 18 and fig. 19, fig. 18 is a schematic cross-sectional view taken along a direction X-X1 in fig. 19, after removing the second patterned layer 250, a first patterned layer 260 is formed, where the first patterned layer 260 has a plurality of first openings 261, and each first opening 261 exposes at least a portion of surfaces of 1 first blocking structure 221 and 1 second blocking structure 242.

In this embodiment, at least 1 of the first openings 261 further exposes a portion of the surface of at least 1 of the third blocking structures.

In this embodiment, the method for forming the first patterning layer 260 includes: forming a first patterning material layer on the surface of the layer to be etched 200, the surface of the first barrier structure 221, the surface of the second barrier structure 242 and the surface of the third barrier structure; the first patterned material layer is exposed and developed to form the first patterned layer 260.

In this embodiment, the material of the first patterning layer 260 includes photoresist.

With continued reference to fig. 18 and fig. 19, the first barrier structure 221 is etched using the first patterned layer 260 as a mask.

In this embodiment, a first etching process is adopted, and the first patterning layer 260 is used as a mask to etch the first blocking structure 221, where the first etching process has a first etching rate for the material of the first blocking structure 221, the first etching process has a second etching rate for the material of the second blocking structure 242, and the first etching rate is greater than the second etching rate.

In this embodiment, the process parameters of the first etching process and the second etching process are different.

In this embodiment, a ratio of the first etching rate to the second etching rate is 5:1 or more.

The ratio of the first etching rate to the second etching rate is too small, so that the exposed second barrier structure 242 is easily worn away when the first barrier structure 221 is etched, which is unfavorable for the first etching process to etch the layer to be etched 200 under the exposed second barrier structure 242 through the exposed second barrier structure 242. Therefore, selecting a suitable ratio of the first etching rate to the second etching rate, that is, when the ratio of the first etching rate to the second etching rate is above 5:1, facilitates better selective etching of the first barrier structure 221, so that in the first etching process, the first etching process is better blocked from etching the layer to be etched 200 under the exposed second barrier structure 242 through the exposed second barrier structure 242.

In this embodiment, when the first opening 261 exposes the surface of the first barrier 223 of the third barrier structure, since the material of the first barrier 223 is the same as that of the first barrier structure 221, the exposed first barrier 223 can be selectively etched and removed while the first barrier structure 221 is selectively etched. When the first opening 261 exposes the surface of the second barrier layer 244 of the third barrier structure, the exposed second barrier layer 244 is not etched because the material of the second barrier layer 244 is different from that of the first barrier structure 221, so that the first etching process can still be blocked from etching the layer to be etched 200 under the exposed second barrier layer 244 of the third barrier structure by the second barrier layer 244 when the first barrier structure 221 and the first barrier layer 223 are selectively etched.

The first etching process comprises at least one of a dry etching process or a wet etching process.

Referring to fig. 20 and 21, fig. 20 is a schematic cross-sectional view taken along a direction X-X1 in fig. 21, after etching the first blocking structure 221 by using the first patterning layer 260 as a mask, and then continuously etching the layer to be etched 200 by using the first patterning layer 260, the exposed second blocking structure 242, and the exposed second blocking layer 244 as masks, a plurality of third interconnect openings 262 are formed in the layer to be etched 200, and the third interconnect openings 262 expose sidewall surfaces of at least one of the second blocking structures 242 and the second blocking layer 244.

In the present embodiment, after the third interconnect opening 262 is formed, the first patterning layer 260, the first barrier structure 221, the second barrier structure 242, and the third barrier structure are removed.

Referring to fig. 22 on the basis of fig. 21, after removing the first patterning layer 260, the first blocking structure 221, the second blocking structure 242, and the third blocking structure, a third interconnect structure 263 is formed in each third interconnect opening 262, and a fourth interconnect structure 253 is formed in each fourth interconnect opening 252.

In this embodiment, the method of forming the third interconnect structure 263 and the fourth interconnect structure 253 includes: forming a layer of electrical interconnect material on the surface of the layer to be etched 200, in the third interconnect opening 263 and in the fourth interconnect opening 253; the layer of electrical interconnect material is planarized until the surface of the layer to be etched 200 is exposed.

In another embodiment, the third blocking structure is not formed, the first blocking structure is etched by using the first patterning layer as a mask, the layer to be etched is etched by continuously using the first patterning layer as a mask, a plurality of first interconnection openings are formed in the layer to be etched, and the side wall surfaces of the second blocking structure are exposed by the first interconnection openings; a first interconnect structure is formed within each first interconnect opening.

In another embodiment, the third blocking structure is not formed, the second patterning layer is used as a mask, the layer to be etched is etched continuously by using the second patterning layer as a mask after the second blocking structure is etched, a plurality of second interconnection openings are formed in the layer to be etched, and the side wall surfaces of the first blocking structure are exposed out of the second interconnection openings; a second interconnect structure is formed within each second interconnect opening.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:

providing a layer to be etched;

forming a plurality of first barrier structures on the surface of the layer to be etched;

forming a plurality of second barrier structures on the surface of the layer to be etched, wherein the materials of the first barrier structures are different from those of the second barrier structures;

forming a first patterning layer, wherein the first patterning layer is provided with a plurality of first openings, and each first opening at least exposes partial surfaces of 1 first barrier structure and 1 second barrier structure;

etching the first blocking structure by taking the first patterning layer as a mask;

forming a second patterned layer, wherein the second patterned layer is provided with a plurality of second openings, and each second opening at least exposes partial surfaces of 1 first barrier structure and 1 second barrier structure;

and etching the second blocking structure by taking the second patterning layer as a mask.

2. The method of forming a semiconductor structure of claim 1, further comprising: before forming the first patterning layer and the second patterning layer, forming a plurality of third barrier structures on the surface of the layer to be etched, wherein the third barrier structures comprise a first barrier layer and a second barrier layer positioned on part of the surface of the first barrier layer, the material of the first barrier layer is the same as that of the first barrier structure, and the material of the second barrier layer is the same as that of the second barrier structure.

3. The method of claim 2, wherein at least 1 of the first openings further exposes a portion of the surface of at least 1 of the third barrier structures.

4. The method for forming a semiconductor structure according to claim 2, wherein at least 1 of the second openings further exposes a portion of the surface of at least 1 of the third barrier structures.

5. The method for forming a semiconductor structure according to claim 1, wherein a first etching process is used to etch the first barrier structure using the first patterned layer as a mask, the first etching process has a first etching rate for the material of the first barrier structure, the first etching process has a second etching rate for the material of the second barrier structure, and the first etching rate is greater than the second etching rate.

6. The method of forming a semiconductor structure of claim 5, wherein a ratio of the first etch rate to the second etch rate is greater than 5: 1.

7. The method for forming a semiconductor structure according to claim 1, wherein a second etching process is used, the second patterned layer is used as a mask, a second barrier structure is etched, the second etching process has a third etching rate for the material of the first barrier structure, the second etching process has a fourth etching rate for the material of the second barrier structure, and the fourth etching rate is greater than the third etching rate.

8. The method of forming a semiconductor structure of claim 7, wherein a ratio of the fourth etch rate to the third etch rate is greater than 5: 1.

9. The method of forming a semiconductor structure of claim 2, wherein forming the first barrier structure comprises: forming a first barrier material layer on the surface of the layer to be etched; forming a plurality of first doping regions in the first barrier material layer; and etching the first barrier material layer after the first doping region is formed until the surface of the layer to be etched is exposed.

10. The method of forming a semiconductor structure of claim 9, wherein forming the first barrier layer comprises: before the first barrier material layer is etched, a plurality of third doping regions are formed in the first barrier material layer, and ions doped in the third doping regions are the same as the ions doped in the first doping regions.

11. The method of forming a semiconductor structure of claim 10, wherein forming the second barrier structure comprises: after the first barrier structure and the first barrier layer are formed, forming a second barrier material layer on the surface of the layer to be etched, the surface of the first barrier structure and the surface of the first barrier layer; forming a plurality of second doped regions in the second barrier material layer on the surface of the layer to be etched; and etching the second barrier material layer after the second doped region is formed until the surface of the layer to be etched, the surface of the first barrier structure and the surface of the first barrier layer are exposed.

12. The method of forming a semiconductor structure of claim 11, wherein forming the second barrier layer comprises: before etching the second barrier material layer, forming a plurality of fourth doping regions in the second barrier material layer on the surface of part of the first barrier layer, wherein ions doped in the fourth doping regions are the same as the ions doped in the second doping regions.

13. The method of forming a semiconductor structure of claim 1, wherein the material of the first barrier structure comprises: titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

14. The method of forming a semiconductor structure of claim 1, wherein the material of the second barrier structure comprises: titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, and silicon.

15. The method of forming a semiconductor structure of claim 1, further comprising: taking the first patterning layer as a mask, etching the first blocking structure, then continuing to etch the layer to be etched by taking the first patterning layer as the mask, and forming a plurality of first interconnection openings in the layer to be etched, wherein the first interconnection openings expose the side wall surfaces of the second blocking structure; a first interconnect structure is formed within each first interconnect opening.

16. The method of forming a semiconductor structure of claim 1, further comprising: taking the second patterning layer as a mask, etching the second blocking structure, and then continuing to etch the layer to be etched by taking the second patterning layer as the mask, so as to form a plurality of second interconnection openings in the layer to be etched, wherein the second interconnection openings expose the side wall surfaces of the first blocking structure; a second interconnect structure is formed within each second interconnect opening.

17. The method of forming a semiconductor structure of claim 3, further comprising: taking the first patterning layer as a mask, etching the first blocking structure, then continuing to etch the layer to be etched by taking the first patterning layer as the mask, and forming a plurality of third interconnection openings in the layer to be etched, wherein the third interconnection openings expose the side wall surfaces of at least one of the second blocking structure and the second blocking layer; a third interconnect structure is formed within each third interconnect opening.

18. The method of forming a semiconductor structure of claim 4, further comprising: taking the second patterning layer as a mask, etching the second barrier structure, and then continuing to etch the layer to be etched by taking the second patterning layer as the mask, so as to form a plurality of fourth interconnection openings in the layer to be etched, wherein the fourth interconnection openings expose the side wall surfaces of at least one of the first barrier structure and the first barrier layer; a fourth interconnect structure is formed within each fourth interconnect opening.

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