CN113964128A - Semiconductor device and capacitor forming method - Google Patents

Semiconductor device and capacitor forming method Download PDF

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Publication number
CN113964128A
CN113964128A CN202111209099.2A CN202111209099A CN113964128A CN 113964128 A CN113964128 A CN 113964128A CN 202111209099 A CN202111209099 A CN 202111209099A CN 113964128 A CN113964128 A CN 113964128A
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Prior art keywords
layer
support layer
interlayer
forming
supporting
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Granted
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CN202111209099.2A
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Chinese (zh)
Inventor
王晓玲
洪海涵
张民慧
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202111209099.2A priority Critical patent/CN113964128A/en
Priority to PCT/CN2021/138332 priority patent/WO2023065510A1/en
Publication of CN113964128A publication Critical patent/CN113964128A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The embodiment of the application provides a semiconductor device and a capacitor forming method, wherein the semiconductor device at least comprises: a substrate and a capacitor; the capacitor includes: a bottom supporting layer, a middle supporting layer and a top supporting layer which are arranged in parallel to the substrate in sequence; a first electrode layer disposed perpendicular to the substrate and penetrating the bottom support layer, the middle support layer, and the top support layer; wherein the intermediate support layer has an upper surface and a lower surface in a direction perpendicular to the substrate; in a direction parallel to the substrate, the side wall of the first electrode layer includes a first protrusion and a second protrusion protruding toward the middle support layer, the first protrusion being in contact with a lower surface of the middle support layer, the second protrusion being in contact with an upper surface of the middle support layer; the dielectric layer covers the surface of the first electrode layer; and the second electrode layer covers the surface of the dielectric layer.

Description

Semiconductor device and capacitor forming method
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, but not exclusively, to a method for forming a semiconductor device and a capacitor.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell includes a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to a capacitor.
As the size of DRAM devices becomes smaller and smaller, the aspect ratio of the capacitor hole in the capacitor becomes larger and larger, and the electrode layer of the capacitor is easily collapsed during the manufacturing process. Therefore, how to provide a capacitor structure with stronger support for the electrode layer is a problem to be solved urgently.
Disclosure of Invention
Embodiments of the present application provide a semiconductor device and a method for forming a capacitor.
In a first aspect, an embodiment of the present application provides a semiconductor device, where the semiconductor device at least includes: a substrate and a capacitor; the capacitor includes:
a bottom supporting layer, a middle supporting layer and a top supporting layer which are arranged in parallel to the substrate in sequence;
a first electrode layer disposed perpendicular to the substrate and penetrating the bottom support layer, the middle support layer, and the top support layer;
wherein the intermediate support layer has an upper surface and a lower surface in a direction perpendicular to the substrate; in a direction parallel to the substrate, the side wall of the first electrode layer includes a first protrusion and a second protrusion protruding toward the middle support layer, the first protrusion being in contact with a lower surface of the middle support layer, the second protrusion being in contact with an upper surface of the middle support layer;
the dielectric layer covers the surface of the first electrode layer;
and the second electrode layer covers the surface of the dielectric layer.
In some embodiments, the intermediate support layer comprises: a first sub-support layer and a second sub-support layer;
wherein, along a direction parallel to the substrate, the sidewall of the first electrode layer includes a third protrusion protruding toward the first sub-support layer and the second sub-support layer, the third protrusion is located between the first sub-support layer and the second sub-support layer, and the third protrusion is in contact with an upper surface of the first sub-support layer and a lower surface of the second sub-support layer.
In some embodiments, the first protrusion, the second protrusion, or the third protrusion has a thickness in a range of 2 to 5 nanometers and the intermediate support layer has a thickness in a range of 10 to 40 nanometers in a direction perpendicular to the substrate;
in a direction perpendicular to the substrate, a ratio of a sum of thicknesses of the first protrusion, the second protrusion, and the third protrusion to a thickness of the intermediate support layer ranges from 1: 1 to 1: 10. .
In some embodiments, the sidewalls of the first electrode layer include fourth protrusions protruding toward the bottom support layer in a direction parallel to the substrate, the fourth protrusions being in contact with an upper surface of the bottom support layer in a direction perpendicular to the substrate; and/or the presence of a gas in the gas,
the sidewalls of the first electrode layer include fifth protrusions protruding toward the top support layer in a direction parallel to the substrate, the fifth protrusions being in contact with a lower surface of the top support layer in a direction perpendicular to the substrate.
In some embodiments, the material of the bottom support layer, the middle support layer, and the top support layer comprises at least one of: silicon oxide; silicon nitride; silicon carbonitride; silicon oxynitride.
In some embodiments, the material of the first electrode layer comprises: metal nitrides and/or metal silicides;
the material of the second electrode layer includes: metal nitrides and/or metal silicides;
the material of the dielectric layer comprises at least one of the following materials: zirconium oxide; hafnium oxide; zirconium titanium oxide; ruthenium oxide; antimony oxide; alumina.
In a second aspect, an embodiment of the present application provides a method for forming a capacitor, where the method includes:
providing a substrate;
sequentially forming a laminated structure which covers the substrate and is provided with a bottom supporting layer, a first sacrificial layer, a middle supporting layer, a second sacrificial layer and a top supporting layer; a first support layer interlayer is formed between the first sacrificial layer and the middle support layer, and/or a second support layer interlayer is formed between the middle support layer and the second sacrificial layer;
forming a through hole penetrating through the laminated structure to expose the substrate; wherein, in a direction parallel to the substrate, the sidewalls of the through-hole comprise first protrusions protruding towards the first support layer interlayer and/or the sidewalls of the through-hole comprise second protrusions protruding towards the second support layer interlayer;
forming a first electrode layer covering the inner wall of the through hole;
and sequentially forming a dielectric layer and a second electrode layer which cover the first electrode layer along the radial direction of the through hole so as to form the capacitor.
In some embodiments, the laminate structure comprises the first support layer interlayer and the second support layer interlayer;
forming the intermediate support layer, comprising:
sequentially forming a first sub-supporting layer, a third supporting layer interlayer and a second sub-supporting layer which cover the first supporting layer interlayer;
the forming a via through the stacked structure includes:
forming the through holes sequentially penetrating through a top supporting layer, the second sacrificial layer, the second supporting layer interlayer, the second sub-supporting layer, the third supporting layer interlayer, the first sub-supporting layer, the first supporting layer interlayer, the first sacrificial layer, and the bottom supporting layer; wherein the through hole sidewall further includes a third protrusion protruding toward the third supporting layer interlayer.
In some embodiments, prior to forming the first sacrificial layer, the method further comprises:
forming a fourth support layer interlayer overlying the bottom support layer;
the forming a via through the stacked structure includes:
forming the through-holes sequentially penetrating the top support layer, the second sacrificial layer, the second support layer interlayer, the middle support layer, the first support layer interlayer, the first sacrificial layer, the fourth support layer interlayer, and the bottom support layer; wherein the through hole sidewall further includes a fourth protrusion protruding toward the fourth supporting layer interlayer.
In some embodiments, prior to forming the top support layer, the method further comprises:
forming a fifth support layer interlayer overlying the second sacrificial layer;
the forming a via through the stacked structure includes:
forming the through holes sequentially penetrating the top support layer, the fifth support layer interlayer, the second sacrificial layer, the second support layer interlayer, the middle support layer, the first support layer interlayer, the first sacrificial layer, and the bottom support layer; wherein the through hole includes a fifth protrusion toward the fifth supporting layer interlayer.
In some embodiments, after forming the top support layer, the method further comprises:
forming a patterned mask layer covering the top supporting layer; the mask layer is used for forming the through hole during etching.
In some embodiments, the forming a first electrode layer covering an inner wall of the through-hole includes:
forming an initial electrode layer covering the mask layer and the inner wall of the through hole;
removing the mask layer and the initial electrode layer covering the mask layer, and exposing the top supporting layer; wherein the remaining initial electrode layer forms the first electrode layer.
In some embodiments, after forming the first electrode layer, the method further comprises:
removing part of the top supporting layer to form a first opening; the first opening exposes the second sacrificial layer;
removing the remaining second sacrificial layer and the second supporting layer interlayer through the first opening, exposing the first electrode layer, and removing part of the middle supporting layer to form a second opening;
and removing the rest of the first support layer interlayer and the first sacrificial layer through the second opening to expose the bottom support layer to form a gap.
In some embodiments, the sequentially forming a dielectric layer and a second electrode layer covering the first electrode layer along a radial direction of the through hole to form the capacitor includes:
and sequentially forming the dielectric layer and the second electrode layer which cover the first electrode layer, the rest of the bottom supporting layer, the rest of the middle supporting layer and the rest of the top supporting layer in the gap.
In some embodiments, the forming a via through the stacked structure comprises:
etching the laminated structure by an etchant to form the through hole;
wherein the etching rate of the etchant to the second supporting layer interlayer and the first supporting layer interlayer is greater than the etching rate of the etchant to the middle supporting layer.
In some embodiments, the material of the first support layer interlayer and the second support layer interlayer comprises at least one of: hafnium oxide; alumina; tantalum oxide.
The semiconductor device and the capacitor forming method provided by the embodiment of the application provide a semiconductor device comprising a substrate and a capacitor, wherein the capacitor comprises a bottom supporting layer, a middle supporting layer and a top supporting layer which are sequentially arranged in parallel with the substrate, a first electrode layer arranged perpendicular to the substrate, a dielectric layer covering the first electrode layer and a second electrode layer, the first electrode layer penetrates through the bottom supporting layer, the middle supporting layer and the top supporting layer, the middle supporting layer is provided with an upper surface and a lower surface, and a first bulge and a second bulge which protrude towards the middle supporting layer are arranged on the side wall of the first electrode layer along the direction parallel to the substrate, wherein the first bulge is in contact with the lower surface of the middle supporting layer, and the second bulge is in contact with the upper surface of the middle supporting layer. Therefore, the supporting layer is embedded into the first electrode layer through the first electrode layer with the protrusions, the contact area between the supporting layer and the first electrode layer is increased, the supporting performance of the capacitor is stronger, and the capacitor structure is more stable.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Fig. 1A to 1D are partial structural schematic views of a capacitor in the related art;
fig. 2A to 2D are schematic partial structural diagrams of a semiconductor device provided in an embodiment of the present application;
fig. 3 is a schematic flow chart of a method for forming a capacitor according to an embodiment of the present disclosure;
fig. 4A to 4H are schematic partial structural diagrams corresponding to a method for forming a capacitor according to an embodiment of the present disclosure;
fig. 5 is a schematic partial structural diagram corresponding to a capacitor forming method according to an embodiment of the present disclosure;
fig. 6 is a schematic partial structural diagram corresponding to a capacitor forming method according to an embodiment of the present disclosure;
fig. 7A and 7B are schematic partial structural diagrams corresponding to a capacitor forming method according to an embodiment of the present disclosure.
Detailed Description
Specific technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Fig. 1A to 1D are partial structural schematic diagrams of a capacitor in the related art, and as shown in fig. 1A, a stacked structure including a substrate 101, a bottom support layer 102, a bottom sacrificial layer 103, a middle support layer 104, a top sacrificial layer 105, a top support layer 106, and a patterned photolithography layer 107 is provided.
As shown in fig. 1B, the stacked structure is etched through the patterned photoresist layer 107 to form a capacitor hole. However, during etching of the stack structure to form a capacitor hole, the surfaces of bottom support layer 102, bottom sacrificial layer 103, middle support layer 104, top sacrificial layer 105, and top support layer 106 adhere to solid adhesion 108 generated during etching, and the support layer surface is oxidized to form oxide 109 (only oxide 109 is shown on the surface of middle support layer 104).
Referring to fig. 1C and 1D, when the first electrode layer 110 is formed, the first electrode layer 110 is in contact with the attachment 108. When the bottom sacrificial layer 103 and the top sacrificial layer 105 are removed through the opening of the top support layer 106, the adhesion 108 and the oxide 109 are also removed, so that the bottom support layer 102, the middle support layer 104, and the top support layer 106 are separated from the first electrode layer 110, and the support layer in the capacitor cannot be effectively supported by the first electrode layer 110, which causes the first electrode layer 110 to easily collapse during the manufacturing process of the capacitor, resulting in the failure of the capacitor.
Based on the problems in the related art, an embodiment of the present application provides a semiconductor device 20, please refer to fig. 2A, where fig. 2A is a schematic view of a partial structure of the semiconductor device 20 provided in the embodiment of the present application, the semiconductor device 20 at least includes a capacitor 200 (as shown by a dashed line box in the figure) and a substrate 201, and as shown in fig. 2A, the capacitor 200 includes: a bottom support layer 202, a middle support layer 203, and a top support layer 204 arranged in order parallel to the substrate 201; a first electrode layer 205 disposed perpendicular to the substrate 201 and penetrating the bottom support layer 202, the middle support layer 203, and the top support layer 204; a dielectric layer 206 covering the surface of the first electrode layer 205; and a second electrode layer 207 covering the surface of the dielectric layer 206.
Note that, in a direction perpendicular to the substrate 201, the intermediate support layer 203 has an upper surface 2031 and a lower surface 2032; in a direction parallel to the substrate 201, the sidewalls of the first electrode layer 205 comprise a first protrusion 2051 and a second protrusion 2052 protruding towards the intermediate support layer 203, the first protrusion 2051 being in contact with the lower surface 2032 of the intermediate support layer, the second protrusion 2052 being in contact with the upper surface 2031 of the intermediate support layer 203.
In the semiconductor device provided by the embodiment of the application, the capacitor is embedded into the first electrode layer through the first electrode layer with the protrusions, so that the contact area between the support layer and the first electrode layer is increased, the support performance of the capacitor is stronger, and the capacitance structure is more stable.
In some embodiments, each support layer may be a multilayer structure. For example, as shown with reference to fig. 2B, the middle support layer 203 may include a first sub-support layer 203-1 and a second sub-support layer 203-2. In a direction parallel to the substrate 201, the sidewalls of the first electrode layer 205 include: and third protrusions 2053 protruding toward the first and second sub-support layers 203-1 and 203-2, the third protrusions 2053 being positioned between the first and second sub-support layers 203-1 and 203-2, the third protrusions 2053 contacting the upper surface of the first sub-support layer 203-1 and the lower surface of the second sub-support layer 203-2.
The supporting layer of the multilayer structure is embedded into the first electrode layer with the plurality of layers of protrusions, so that the capacitor is stronger in supporting performance, and the performance of the capacitor is improved.
With reference to fig. 2B, in a direction perpendicular to the substrate 201, the thickness of the first protrusion 2051, the second protrusion 2052, or the third protrusion 2053 may range from 2 to 5 nanometers, and the thickness of the middle supporting layer 203 may range from 10 to 40 nanometers. The ratio of the sum of the thicknesses of the first protrusion 2051, the second protrusion 2052, or the third protrusion 2053 to the thickness of the middle support layer 203 in a direction perpendicular to the substrate 201 may range from 1: 1 to 1: 10 in any ratio between.
In some embodiments, the first electrode layer 205 may be provided with protrusions on the bottom support layer 202, or may be provided with protrusions on the top support layer 204, or may be provided with protrusions on both the bottom support layer 202 and the top support layer 204 to improve the support of the capacitor.
Fig. 2C is a schematic structural diagram of the first electrode layer 205 provided with a protrusion on the bottom support layer 202 according to an embodiment of the present disclosure, as shown in fig. 2C, a sidewall of the first electrode layer 205 includes a fourth protrusion 2054 protruding toward the bottom support layer 202 along a direction parallel to the substrate 201, and the fourth protrusion 2054 is in contact with an upper surface of the bottom support layer 202 along a direction perpendicular to the substrate 201.
Fig. 2D is a schematic structural diagram of the first electrode layer 205 provided with protrusions on the top support layer 204 and the bottom support layer 202 simultaneously, based on fig. 2C, as shown in fig. 2D, the sidewall of the first electrode layer 205 includes a fifth protrusion 2055 protruding toward the top support layer 204 in a direction parallel to the substrate 201, and the fifth protrusion 2055 is in contact with the lower surface of the top support layer 204 in a direction perpendicular to the substrate 201.
The first electrode layer in the embodiment of the application is provided with the protrusion through the position of at least one of the top supporting layer and the bottom supporting layer, so that the top, the middle and the bottom of the first electrode layer can be effectively supported, the capacitor is not easy to collapse in the manufacturing and using processes, and the yield of the capacitor is improved.
In some embodiments, the materials of the bottom support layer 202, the middle support layer 203, and the top support layer 204 may comprise at least one of: silicon oxide; silicon nitride; silicon carbonitride; silicon oxynitride.
In some embodiments, the material of the first electrode layer 205 may include: metal nitrides and/or metal silicides; the material of the second electrode layer 206 includes: metal nitrides and/or metal silicides; the material of dielectric layer 207 includes at least one of: zirconium oxide, hafnium oxide, zirconium titanium oxide, ruthenium oxide, antimony oxide, and aluminum oxide.
In some embodiments, the capacitor structure provided by the embodiments of the present application may be suitable for a double-layer capacitor and also suitable for a single-layer capacitor. The following describes a method for forming a capacitor provided in an embodiment of the present application, taking a double-layer capacitor as an example.
An embodiment of the present application provides a method for forming a capacitor, and fig. 3 is a schematic flowchart of the method for forming a capacitor provided in the embodiment of the present application, and as shown in fig. 3, the capacitor may be formed through the following steps:
step S301, a substrate is provided.
Step S302, sequentially forming a laminated structure which covers the substrate and is provided with a bottom supporting layer, a first sacrificial layer, a middle supporting layer, a second sacrificial layer and a top supporting layer; and a first support layer interlayer is formed between the first sacrificial layer and the middle support layer, and/or a second support layer interlayer is formed between the middle support layer and the second sacrificial layer.
Step S303, forming a through hole penetrating through the laminated structure to expose the substrate; wherein, in a direction parallel to the substrate, the sidewall of the through-hole includes a first protrusion protruding toward the first support layer interlayer, and/or the sidewall of the through-hole includes a second protrusion protruding toward the second support layer interlayer.
And step S304, forming a first electrode layer covering the inner wall of the through hole.
Step S305, sequentially forming a dielectric layer and a second electrode layer covering the first electrode layer along the radial direction of the through hole to form the capacitor.
Next, referring to fig. 4A to 4H, a method for forming a capacitor provided in an embodiment of the present application will be described in detail.
As shown in fig. 4A, step S301 and step S302 are performed, a substrate 401 is provided, and a stacked structure 402 having a bottom support layer 4021, a first sacrificial layer 4022, an intermediate support layer 4023, a second sacrificial layer 4024, and a top support layer 4025 is formed in this order to cover the substrate 401 on the substrate 401.
In the embodiment of the present application, a first support layer interlayer 403 is formed between the first sacrificial layer 4022 and the middle support layer 4023, and a second support layer interlayer 404 is formed between the middle support layer 4023 and the second sacrificial layer 4024.
In some embodiments, only one of the first support interlayer 403 and the second support interlayer 404 may be formed in the stacked structure 402, but the embodiments of the present application describe the technical solutions provided by the embodiments of the present application in detail by using both the first support interlayer 403 and the second support interlayer 404.
In some embodiments, the substrate 401 in the semiconductor structure may be made of a semiconductor material, such as one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.
In the embodiment of the present application, the stacked structure 402 covering the substrate 401 may be sequentially formed by means of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or atomic layer Deposition (ald) process.
Here, in order to facilitate etching of the stacked structure 402, the first sacrificial layer 4022 and the second sacrificial layer 4024 may be made of a soft material such as phosphosilicate Glass (PSG), borophosphosilicate Glass (BPSG), or fluorosilicate Glass (FSG). The constituent material of the first support layer 4021, the second support layer 4023, and the third support layer 4025 may be a nitride, such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon boronitride, or the like. The material of the first support interlayer 403 and the second support interlayer 404 may be a dielectric material such as hafnium oxide, aluminum oxide, or tantalum oxide.
In some embodiments, after forming the stacked structure 402, a patterned mask layer 405 may be formed on the surface of the stacked structure 402, as shown in fig. 4B. The material of the mask layer 405 may be an oxide, such as silicon oxide. Masking layer 405 is used to form vias during etching. The embodiment of the present application does not limit the pattern of the mask layer 405.
Referring to fig. 4C to 4E, step S303 is performed to form a via 406 penetrating the stacked structure 402 based on the mask layer 405 to expose the substrate 401. Wherein a dry etching process or a wet etching process may be employed to form the via 406.
In some embodiments, the stacked structure 402 may be etched by an etchant, where an etching rate of the etchant to the second support layer interlayer 404 and the first support layer interlayer 403 is greater than an etching rate of the etchant to the intermediate support layer 4023, so that when the stacked structure is etched to form a through hole, an area of the second support layer interlayer and an area of the first support layer interlayer are removed and are greater than an area of the intermediate support layer, and when the first electrode layer is subsequently formed, the intermediate support layer can be embedded into the first electrode layer, so as to improve a support property of the intermediate support layer to the first electrode layer.
As shown in FIG. 4C, nitrogen trifluoride (NF) may be used3) And carbon tetrafluoride (CF)4) The gas acts as an etchant to remove a portion of the top support layer 4025, the etch gas is replaced after removing a portion of the top support layer 4025, a portion of the second sacrificial layer 4024 is removed through the etched top support layer, and the replaced etch gas may be a fluorine-containing gas, such as carbon tetrafluoride (CF)4) And sulfur hexafluoride (SF)6). It is also possible to remove part of the top support layer 4025 using phosphoric acid and part of the second sacrificial layer 4024 using hydrofluoric acid.
Referring to FIG. 4D, after etching the second interlayer supporting layer 404, the middle supporting layer 4023 and the first interlayer supporting layerAt 403, nitrogen trifluoride (NF) may be used3) And carbon tetrafluoride (CF)4) The gas serves as an etchant so that the etching selectivity of the etching gas for the second supporting layer interlayer 404 and the first supporting layer interlayer 403 is higher than that of the intermediate supporting layer 4023, so that the sidewall of the through-hole 406 includes a first protrusion 4061 protruding toward the first supporting layer interlayer 403 (as indicated by a dotted line box in the figure) and a second protrusion 4062 protruding toward the second supporting layer interlayer 404 (as indicated by a dotted line box in the figure).
With continued reference to fig. 4E, after forming the first and second protrusions 4061, 4062 of the through hole 406, the etching gas may be replaced to etch the first sacrificial layer 4022 and the bottom supporting layer 4021, for example, carbon tetrafluoride (CF)4) And sulfur hexafluoride (SF)6) The etching gas is used to remove a part of the first sacrificial layer 4022 by nitrogen trifluoride (NF)3) And carbon tetrafluoride (CF)4) The gas acts as an etchant to remove portions of the bottom support layer 4021 to form the vias 406, and the vias 406 reveal the substrate 401.
Next, referring to fig. 4F, step S304 is performed to form a first electrode layer 407 covering the inner wall of the through hole 406.
As shown in fig. 4F, an initial electrode layer 407' covering the mask layer 405 and the inner wall of the via hole 406 may be formed first by means of a physical vapor deposition, a chemical vapor deposition, or an atomic layer deposition process.
Referring to fig. 4G, after the initial electrode layer 407' is formed, the mask layer 405 and a portion of the initial electrode layer 407' on the surface of the mask layer 405 are removed, the top supporting layer 4025 is exposed, and the remaining initial electrode layer 407' forms the first electrode layer 407.
Here, the mask layer 405 and a portion of the first electrode layer 407' of the surface of the mask layer 405 may be dry etched or wet etched. In some embodiments, the material of the first electrode layer 407 comprises at least one of: metal nitrides and metal silicides, such as titanium nitride (TiN).
In the present embodiment, since the bump structure is formed when the through-hole 406 is formed, when the first electrode layer 407 covering the inner wall of the through-hole 406 is formed, the first electrode layer 407 fills the bumps in the through-hole 406 so that the first electrode layer 407 has the first bumps 4071 protruding toward the first supporting layer interlayer 403 and the second bumps 4072 protruding toward the second supporting layer interlayer 404.
Next, referring to fig. 4H, step S305 is performed to sequentially form a dielectric layer 408 and a second electrode layer 409 covering the first electrode layer 407 along the radial direction of the through hole 306 to form a capacitor.
In some embodiments, the dielectric layer 408 and the second electrode layer 409 may be formed by a physical vapor deposition, chemical vapor deposition, or atomic layer deposition process. The material of dielectric layer 408 may include at least one of: zirconium oxide, hafnium oxide, zirconium titanium oxide, ruthenium oxide, antimony oxide, and aluminum oxide; the material of the second electrode layer 409 may include at least one of: metal nitrides and metal silicides.
When forming the through hole, the through hole side wall forms the first protrusion and the second protrusion protruding towards the middle support layer, so that the support layer is embedded into the first electrode layer through the first electrode layer with the protrusions, the contact area of the support layer and the first electrode layer is increased, the support performance of the capacitor is stronger, and the capacitor structure is more stable.
In some embodiments, the middle supporting layer 4023 may include a first sub-supporting layer 4023-1 and a second sub-supporting layer 4023-2, as shown in fig. 5, and fig. 5 is a partial structural schematic diagram of a method for forming a capacitor provided in an embodiment of the present application.
Here, the formation of the middle support layer 4023 may be achieved by sequentially forming the first sub-support 4023-1, the third support layer interlayer 410, and the second sub-support layer 4023-2 covering the first support layer interlayer 403 through a physical vapor deposition, chemical vapor deposition, or atomic layer deposition process.
In this embodiment, when the intermediate support layer 4023 has a multi-layer structure, the side walls of the through holes 406 form protrusions protruding toward the third support layer interlayer 410 when the through holes 406 are formed, and thus, when the first electrode layer 407 is formed, the first electrode layer 407 fills the protrusions protruding toward the third support layer interlayer 410 to form the third protrusions 4073 of the first electrode layer 407.
In some embodiments, the top support layer 4025 and the bottom support layer 4021 may also be a multilayer structure, which is not shown in this application embodiment.
According to the capacitor, the supporting layer of the multilayer structure is embedded into the first electrode layer with the multilayer protruding structure, the supporting performance of the capacitor is improved, and the performance of the capacitor is enhanced.
In some embodiments, before the first sacrificial layer 4022 is formed, a fourth supporting layer interlayer 411 covering the bottom supporting layer 4021 may be formed, as shown in fig. 6, where fig. 6 is a partial structural schematic diagram of a method for forming a capacitor provided in this embodiment of the present application. Since the sidewall of the through hole 406 forms a protrusion protruding toward the fourth supporting layer interlayer 411 when the through hole 406 is formed, the first electrode layer 407 fills the protrusion protruding toward the fourth supporting layer interlayer 411 to form the fourth protrusion 4074 of the first electrode layer 407 when the first electrode layer 407 is formed.
In some embodiments, the support layer interlayer may also be formed before the top support layer 4025 is formed, such that the first electrode layer 407 forms protrusions (not shown in the figures) protruding towards the top support layer 4025.
In the capacitor forming method provided by the embodiment of the application, the first electrode layer can form a protrusion on at least one of the bottom support layer, the middle support layer or the top support layer, so that the support layer of the capacitor is embedded into the electrode layer, and the support stability of the capacitor is improved.
Referring to fig. 7A and 7B, after forming the first electrode layer 407, the method for forming a capacitor according to the embodiment of the present disclosure further includes the following steps:
as shown in fig. 7A, a portion of the top support layer 4025 is removed to form a first opening 412, wherein the first opening 412 exposes the second sacrificial layer 4024. Here, a wet etch or dry etch process may be used to remove a portion of the top support layer 4025.
Through the first opening 412, the remaining second sacrificial layer 4024 and the second supporting layer interlayer 404 may be removed by dry etching or wet etching, and part of the middle supporting layer 4023 is removed to form a second opening 413, and through the second opening 413, the remaining first supporting layer interlayer 403 and the first sacrificial layer 4022 are removed to expose the bottom supporting layer 4021 to form a void.
In some embodiments, when wet etching is used to remove the remaining second sacrificial layer 4024 and the second supporting layer interlayer 404 after etching, the wet etching solution may be a solution including diluted hydrofluoric acid (DHF) and ammonia (NH)4OH), or a mixed solution containing diluted hydrofluoric acid (DHF) and tetramethylammonium hydroxide (TMAH).
With reference to fig. 7B, after the first sacrificial layer 4022 and the second sacrificial layer 4024 are removed, a dielectric layer 408 and a second electrode layer 409 covering the first electrode layer 407, the remaining bottom supporting layer 4021, the remaining middle supporting layer 4023, and the remaining top supporting layer 4025 may be sequentially formed in the gap by a physical vapor deposition, a chemical vapor deposition, or an atomic layer deposition process while the dielectric layer 408 and the second electrode layer 409 covering the first electrode layer 407 are sequentially formed.
In some embodiments, the material of dielectric layer 408 includes at least one of: zirconium oxide, hafnium oxide, zirconium titanium oxide, ruthenium oxide, antimony oxide, and aluminum oxide.
In some embodiments, the material of the second electrode layer 409 comprises at least one of: metal nitrides and metal silicides.
The first electrode layer that can imbed the supporting layer through the formation for the phenomenon that the supporting layer can not break away from with first electrode layer can not take place at the in-process supporting layer of preparation to the condenser, has increased the area of contact of supporting layer and first electrode layer, makes the electric capacity structure more stable.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (16)

1. A semiconductor device, characterized in that the semiconductor device comprises at least: a substrate and a capacitor; the capacitor includes:
a bottom supporting layer, a middle supporting layer and a top supporting layer which are arranged in parallel to the substrate in sequence;
a first electrode layer disposed perpendicular to the substrate and penetrating the bottom support layer, the middle support layer, and the top support layer;
wherein the intermediate support layer has an upper surface and a lower surface in a direction perpendicular to the substrate; in a direction parallel to the substrate, the side wall of the first electrode layer includes a first protrusion and a second protrusion protruding toward the middle support layer, the first protrusion being in contact with a lower surface of the middle support layer, the second protrusion being in contact with an upper surface of the middle support layer;
the dielectric layer covers the surface of the first electrode layer;
and the second electrode layer covers the surface of the dielectric layer.
2. The semiconductor device of claim 1, wherein the intermediate support layer comprises: a first sub-support layer and a second sub-support layer;
wherein, along a direction parallel to the substrate, the sidewall of the first electrode layer includes a third protrusion protruding toward the first sub-support layer and the second sub-support layer, the third protrusion is located between the first sub-support layer and the second sub-support layer, and the third protrusion is in contact with an upper surface of the first sub-support layer and a lower surface of the second sub-support layer.
3. The semiconductor device according to claim 2,
the thickness of the first protrusion, the second protrusion or the third protrusion in a direction perpendicular to the substrate is in a range of 2 to 5 nm, and the thickness of the middle support layer is in a range of 10 to 40 nm;
in a direction perpendicular to the substrate, a ratio of a sum of thicknesses of the first protrusion, the second protrusion, and the third protrusion to a thickness of the intermediate support layer ranges from 1: 1 to 1: 10.
4. the semiconductor device according to claim 1, wherein in a direction parallel to the substrate, a sidewall of the first electrode layer includes a fourth bump protruding toward the bottom support layer, the fourth bump being in contact with an upper surface of the bottom support layer in a direction perpendicular to the substrate; and/or the presence of a gas in the gas,
the sidewalls of the first electrode layer include fifth protrusions protruding toward the top support layer in a direction parallel to the substrate, the fifth protrusions being in contact with a lower surface of the top support layer in a direction perpendicular to the substrate.
5. The semiconductor device of claim 1, wherein the material of the bottom support layer, the middle support layer, and the top support layer comprises at least one of: silicon oxide; silicon nitride; silicon carbonitride; silicon oxynitride.
6. The semiconductor device according to claim 1,
the material of the first electrode layer includes: metal nitrides and/or metal silicides;
the material of the second electrode layer includes: metal nitrides and/or metal silicides;
the material of the dielectric layer comprises at least one of the following materials: zirconium oxide; hafnium oxide; zirconium titanium oxide; ruthenium oxide; antimony oxide; alumina.
7. A method of forming a capacitor, the method comprising:
providing a substrate;
sequentially forming a laminated structure which covers the substrate and is provided with a bottom supporting layer, a first sacrificial layer, a middle supporting layer, a second sacrificial layer and a top supporting layer; a first support layer interlayer is formed between the first sacrificial layer and the middle support layer, and/or a second support layer interlayer is formed between the middle support layer and the second sacrificial layer;
forming a through hole penetrating through the laminated structure to expose the substrate; wherein, in a direction parallel to the substrate, the sidewalls of the through-hole comprise first protrusions protruding towards the first support layer interlayer and/or the sidewalls of the through-hole comprise second protrusions protruding towards the second support layer interlayer;
forming a first electrode layer covering the inner wall of the through hole;
and sequentially forming a dielectric layer and a second electrode layer which cover the first electrode layer along the radial direction of the through hole so as to form the capacitor.
8. The method of claim 7, wherein the laminate structure comprises the first support layer interlayer and the second support layer interlayer;
forming the intermediate support layer, comprising:
sequentially forming a first sub-supporting layer, a third supporting layer interlayer and a second sub-supporting layer which cover the first supporting layer interlayer;
the forming a via through the stacked structure includes:
forming the through holes sequentially penetrating through a top supporting layer, the second sacrificial layer, the second supporting layer interlayer, the second sub-supporting layer, the third supporting layer interlayer, the first sub-supporting layer, the first supporting layer interlayer, the first sacrificial layer, and the bottom supporting layer; wherein the through hole sidewall further includes a third protrusion protruding toward the third supporting layer interlayer.
9. The method of claim 7, wherein prior to forming the first sacrificial layer, the method further comprises:
forming a fourth support layer interlayer overlying the bottom support layer;
the forming a via through the stacked structure includes:
forming the through-holes sequentially penetrating the top support layer, the second sacrificial layer, the second support layer interlayer, the middle support layer, the first support layer interlayer, the first sacrificial layer, the fourth support layer interlayer, and the bottom support layer; wherein the through hole sidewall further includes a fourth protrusion protruding toward the fourth supporting layer interlayer.
10. The method of claim 7, wherein prior to forming the top support layer, the method further comprises:
forming a fifth support layer interlayer overlying the second sacrificial layer;
the forming a via through the stacked structure includes:
forming the through holes sequentially penetrating the top support layer, the fifth support layer interlayer, the second sacrificial layer, the second support layer interlayer, the middle support layer, the first support layer interlayer, the first sacrificial layer, and the bottom support layer; wherein the through hole includes a fifth protrusion toward the fifth supporting layer interlayer.
11. The method of claim 7, wherein after forming the top support layer, the method further comprises:
forming a patterned mask layer covering the top supporting layer; the mask layer is used for forming the through hole during etching.
12. The method of claim 11, wherein the forming a first electrode layer covering an inner wall of the through-hole comprises:
forming an initial electrode layer covering the mask layer and the inner wall of the through hole;
removing the mask layer and the initial electrode layer covering the mask layer, and exposing the top supporting layer; wherein the remaining initial electrode layer forms the first electrode layer.
13. The method of claim 12, wherein after forming the first electrode layer, the method further comprises:
removing part of the top supporting layer to form a first opening; the first opening exposes the second sacrificial layer;
removing the remaining second sacrificial layer and the second supporting layer interlayer through the first opening, exposing the first electrode layer, and removing part of the middle supporting layer to form a second opening;
and removing the rest of the first support layer interlayer and the first sacrificial layer through the second opening to expose the bottom support layer to form a gap.
14. The method of claim 13, wherein sequentially forming a dielectric layer and a second electrode layer covering the first electrode layer along a radial direction of the through hole to form the capacitor comprises:
and sequentially forming the dielectric layer and the second electrode layer which cover the first electrode layer, the rest of the bottom supporting layer, the rest of the middle supporting layer and the rest of the top supporting layer in the gap.
15. The method of claim 7, wherein the forming a via through the stacked structure comprises:
etching the laminated structure by an etchant to form the through hole;
wherein the etching rate of the etchant to the second supporting layer interlayer and the first supporting layer interlayer is greater than the etching rate of the etchant to the middle supporting layer.
16. The method of claim 7, wherein the material of the first and second support layer interlayers comprises at least one of: hafnium oxide; alumina; tantalum oxide.
CN202111209099.2A 2021-10-18 2021-10-18 Semiconductor device and capacitor forming method Granted CN113964128A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117500365A (en) * 2023-12-29 2024-02-02 长鑫新桥存储技术有限公司 Method for manufacturing capacitor

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030178728A1 (en) * 2002-03-21 2003-09-25 Byung-Jun Park Methods of forming integrated circuit devices including cylindrical capacitors having supporters between lower electrodes and integrated circuit devices formed thereby
KR20080000274A (en) * 2006-06-27 2008-01-02 주식회사 하이닉스반도체 Capacitor in a semiconductor device and method of manufacturing the same
KR20100034629A (en) * 2008-09-24 2010-04-01 주식회사 하이닉스반도체 Method for fabricating capacitor
CN108231771A (en) * 2016-12-09 2018-06-29 三星电子株式会社 Semiconductor devices
CN108346661A (en) * 2017-01-24 2018-07-31 三星电子株式会社 Semiconductor devices
CN110752202A (en) * 2018-07-23 2020-02-04 三星电子株式会社 Semiconductor device with a plurality of transistors
US20210242209A1 (en) * 2020-02-03 2021-08-05 Winbond Electronics Corp. Dynamic random access memory device and manufacturing method thereof
CN113299829A (en) * 2021-05-12 2021-08-24 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
CN113345896A (en) * 2020-03-03 2021-09-03 华邦电子股份有限公司 Dynamic random access memory device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410179A (en) * 2020-03-16 2021-09-17 长鑫存储技术有限公司 Semiconductor structure forming method and semiconductor structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030178728A1 (en) * 2002-03-21 2003-09-25 Byung-Jun Park Methods of forming integrated circuit devices including cylindrical capacitors having supporters between lower electrodes and integrated circuit devices formed thereby
KR20080000274A (en) * 2006-06-27 2008-01-02 주식회사 하이닉스반도체 Capacitor in a semiconductor device and method of manufacturing the same
KR20100034629A (en) * 2008-09-24 2010-04-01 주식회사 하이닉스반도체 Method for fabricating capacitor
CN108231771A (en) * 2016-12-09 2018-06-29 三星电子株式会社 Semiconductor devices
CN108346661A (en) * 2017-01-24 2018-07-31 三星电子株式会社 Semiconductor devices
CN110752202A (en) * 2018-07-23 2020-02-04 三星电子株式会社 Semiconductor device with a plurality of transistors
US20210242209A1 (en) * 2020-02-03 2021-08-05 Winbond Electronics Corp. Dynamic random access memory device and manufacturing method thereof
CN113345896A (en) * 2020-03-03 2021-09-03 华邦电子股份有限公司 Dynamic random access memory device and manufacturing method thereof
CN113299829A (en) * 2021-05-12 2021-08-24 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117500365A (en) * 2023-12-29 2024-02-02 长鑫新桥存储技术有限公司 Method for manufacturing capacitor
CN117500365B (en) * 2023-12-29 2024-05-10 长鑫新桥存储技术有限公司 Method for manufacturing capacitor

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