KR0144323B1 - Semiconductor Memory Device Manufacturing Method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, wherein a gate electrode, a source, and a drain are formed on a semiconductor substrate in order to improve the mechanical strength concentrated in the lower layer of the laminated film and improve the aspect ratio of the contact flow. Forming a memory cell transistor comprising a region, forming an insulating film on the memory cell transistor, forming an etch stop film on the insulating film, and alternately forming a temporary film and a conductive layer on the etch stop film Forming a multilayer film having a multilayer structure in which the uppermost layer becomes a temporary film, selectively removing the laminated film by a dry etching process so that the insulating film is exposed, and forming a predetermined laminated film pattern; Forming sidewalls and using the conductive sidewalls as a mask; Selectively etching the insulating film to form a contact flow exposing a source (or drain) region of the memory cell transistor, forming an upper conductive film on an inner surface of the contact flow, the conductive side wall, and the laminated structure film; And patterning the upper conductive layer and the stacked layer into a capacitor storage node pattern, and removing the temporary layer from the stacked layer.

Description

Semiconductor Memory Device Manufacturing Method

1 is a process flowchart showing a capacitor manufacturing method of a semiconductor memory device according to the prior art.

2 is a process flowchart showing a capacitor manufacturing method of a semiconductor memory device according to the prior art.

3 is a process flowchart showing a method of manufacturing a capacitor of a semiconductor memory device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a capacitor structure of a semiconductor memory device according to an embodiment of the present invention.

5 is an enlarged view of a part of the process flow chart of FIG.

* Explanation of symbols for main parts of the drawings

100: semiconductor substrate 31: field oxide film

32: source and drain region 33: gate electrode

34: insulating film 35: etch stop film

36: first temporary film 37: first conductive layer

38: second temporary film 39, 41, 43: photoresist pattern

40: conductive side wall 42: upper conductive film

44: capacitor storage node 45: capacitor dielectric film

46: capacitor plate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor having a storage node having a multilayered stacked structure. BACKGROUND With the development of semiconductor devices, work of integrating many devices with a high degree of integration on one semiconductor chip has been actively performed. In particular, in memory cells of DRAM (Dynamic Random Access Memory), various various cell structures have been proposed to minimize device size. In view of minimizing the area occupied on the chip for high integration, the memory cell is preferably composed of one transistor and one capacitor. As described above, in a memory cell composed of one transistor and one capacitor, signal charges are stored in a storage node of a capacitor connected to a transistor (switching transistor). Therefore, when the memory cell size is reduced due to the high integration of the semiconductor memory device, the capacitor size is also reduced, thereby reducing the number of signal charges that can be stored in the storage node. Therefore, in order to deliver a desired signal without malfunctioning, the signal is transmitted. The capacitor storage node of the memory cell must have a surface area above a certain value to secure the required capacitor capacity. Therefore, in order to reduce the size of the memory cell, the storage node of the capacitor must have a relatively large surface area within a limited area on the semiconductor substrate. As described above, among the various memory cell structures proposed to increase the surface area of the capacitor storage node, the stack capacitor is advantageous in that it is advantageous for high integration and has the advantage of being less susceptible to soft errors. In addition, memory cells with stacked capacitors have the advantage of being suitable for mass production and relatively easy to process. As one of the stacked capacitor structures for increasing the capacitor capacity, Ema et al. Describe the fin structure capacitors published in [IEDM pp.592-595,1988] with reference to FIG. First, as shown in FIG. 1A, a memory cell transistor including a gate electrode 1, a source, and a drain 2 is formed on a semiconductor substrate 100, and then shown in FIG. 1B. As described above, the nitride film 3 is coated on the memory cell transistor, and the first oxide film 4, the first polysilicon layer 5, and the second oxide film 6 are continued as shown in FIG. ) Is formed sequentially, and then the contact oxide is formed by selectively etching the second oxide film 6, the first polysilicon layer 5, and the first oxide film 4. Next, as shown in FIG. 1 (b), the second polysilicon layer 7 is deposited on the entire surface of the resultant, and then the second polysilicon layer 7 as shown in FIG. 1 (e), A pinned capacitor storage node is formed by selectively etching the second oxide film 6 and the first polysilicon layer 5. Next, as shown in FIG. 1 (f), the second oxide film and the first oxide film are formed. After removal by wet etching, a capacitor dielectric film 8 is formed on the entire surface of the formed capacitor storage node as shown in FIG. 1 (g), and then a capacitor plate is formed on the entire surface of the capacitor dielectric film 8. The capacitor 9 of the semiconductor memory device is completed by forming the electrode 9. In the capacitor having the storage node of the above-described fin structure, as the number of stacked pins increases, the mechanical strength of the polysilicon layer in the center, which is connected to and supports each stacked layer, becomes weak, and thus the possibility of defects increases. In addition, as the number of stacked pins increases, the aspect ratio of contact gaps for connecting the memory cell transistors and capacitors increases, so that the coating property of the polysilicon support layer, which is the uppermost conductive layer of the capacitor storage node of the stacked structure, is deteriorated. . In order to solve this problem, H. Gotou et al. Formed a conductive base layer connected to the source and drain of a memory cell transistor and connected the pinned laminate films to the conductive side walls from one edge thereof to support the stacked films by the sidewalls. We devised a technique to help. (US Pat. No. 5,126,810) The technique is described with reference to FIG. 2 as follows. First, as shown in FIG. 2A, a memory cell transistor including a gate electrode 11, a source and a drain region 12 is formed on a semiconductor substrate 100 by a general MOS transistor manufacturing process. The interlayer insulating film 13, the etch stop film 14, and the buffer layer 15 are sequentially formed on the entire surface of the substrate on which the memory cell transistor is formed by using a chemical vapor deposition (CVD) method. Subsequently, the buffer layer 15, the etch stop layer 14, and the interlayer insulating layer 13 are selectively etched to form a contact flow so that the source (or drain) region 12 of the transistor is exposed, and then over the entire surface of the resultant. The multilayer polysilicon layers 16, 18 and 20 and the multilayer oxide films 17, 19 and 21 are alternately stacked. Subsequently, as shown in FIG. 2 (b), a predetermined pattern is selectively etched by selectively etching the multilayer polysilicon layers 16, 18 and 20 and the multilayer oxide layers 17, 19 and 21 that are alternately stacked. Form. Next, as shown in FIG. 2 (c), a polysilicon layer is deposited on the entire surface of the resultant and then anisotropically etched to form a polysilicon sidewall 22. The polysilicon side wall 22 formed as described above supports the multi-layered polysilicon layers 16, 18, and 20 via the multi-layer oxide layers 17, 19, and 21, and serves as an electrical passage. . Subsequently, as shown in FIG. 2 (d), the photoresist 23 is applied to the entire surface of the resultant, and then patterned through a conventional photolithography process to expose one side of the formed polysilicon side wall 22. The exposed polysilicon sidewall 22 is etched. Next, as shown in FIG. 2E, when the photoresist pattern is removed, the buffer layer 15 is removed, and the multilayer oxide layers 17, 19, 21 are removed by wet etching, the multilayer poly A capacitor storage node consisting of the silicon layers 16, 18, and 20 and the polysilicon sidewalls 22 supporting it is completed. Subsequently, as shown in FIG. 2 (f), after the capacitor dielectric layer 24 is formed on the entire surface of the capacitor storage node, a conductive material is deposited on the entire surface of the dielectric layer 24, and then patterned. Form 26 to complete the capacitor. In the prior art, since the load is concentrated on the sidewall of the conductive base layer (polysilicon layer 16) directly above the contact hole for connecting the transistor and the capacitor, the mechanical strength of the stacked storage node also tends to be weak. In addition, the etching degree of the anisotropic etching for forming the polysilicon side wall has to be precisely adjusted to prevent the upper layer layer from being etched. The invention is to solve the above-mentioned problems, and its object is to improve the mechanical strength and the step coverage of the uppermost layer of the stacked structure in the capacitor storage node of the stacked structure. A semiconductor memory device manufacturing method of the present invention for achieving the above object comprises the steps of forming a memory cell transistor consisting of a gate electrode, a source and a drain region on a semiconductor substrate, forming an insulating film on the memory cell transistor; Forming an etch stop layer on the insulating layer, alternately stacking a temporary film and a conductive layer on the etch stop layer, forming a multilayer film having a multi-layer structure in which a top layer becomes a temporary film, and dry etching to expose the insulating film Selectively removing the laminated film to form a predetermined laminated film pattern, forming a conductive side wall on the side of the laminated film pattern, and selectively etching the insulating film using the conductive side wall as a mask to form the memory cell. Forming a contact hole exposing the source (or drain) region of the transistor; Forming an upper conductive film on the inner surface of the contact layer, the conductive side wall, and the laminated structure film, patterning the upper conductive film and the laminated film with a capacitor storage node pattern, and removing the temporary film from the laminated film. Characterized in that it comprises a step. Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; 4 illustrates a stacked capacitor structure of a semiconductor memory device according to an embodiment of the present invention. A semiconductor memory device according to an embodiment of the present invention has a contact channel formed on a source (or drain) 32 of a memory cell transistor for electrical connection between a capacitor and a memory cell transistor as shown in FIG. An insulating film 34 is included on the memory cell transistor, and a conductive side wall 40 formed on the insulating film 34 of the upper edge portion of the contact hole. And a conductive layer 37 connected to the side surface of the conductive side wall 40 and extending horizontally in a direction outside the contact hole, and formed along the inner side surface of the contact flow and the conductive side wall. An upper conductive film 42 connected to the upper and lower conductive films 42 is formed, and the storage node is formed by the conductive side wall 40, the conductive layer 37, and the upper conductive film 42. The conductive layer 37 connected to the side surface of the conductive side wall is composed of a single layer in the embodiment shown in FIG. 4, but may be formed in multiple layers to increase the capacitor capacity. As described above, the capacitor storage node of the semiconductor memory device of the present invention supports the conductive laminated film by the conductive side wall 40 and the upper conductive film 42 to improve the mechanical strength of the storage node around the contact hole where the load of the stacked film is concentrated. You can do it. Next, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 3A, the gate electrode 33, the source, and the semiconductor substrate 100 are separated by the field oxide film 31 into the active region and the device isolation region. The drain region 32 is formed to complete the transistor. Subsequently, an oxide film is formed as a first insulating film 34 on the semiconductor substrate on which the transistor is formed, and then the etch stop film 35, the first temporary film 36, the first conductive layer 37, and the second film are disposed thereon. The temporary film 38 is formed in sequence. As the etch stop layer 35, for example, a nitride film is formed to a thickness of 500 to 1000 mm by using a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced CVD (PICVD) method. As the first and second temporary films 36 and 38, an organic insulating film such as polyimide or an inorganic insulating film such as spin on glass (SOG) or silicon oxide film is used. The organic insulating film or SOG is formed by a rotation coating method and is inorganic. The insulating film is formed by chemical vapor deposition. The first and second temporary films 36 and 38 are formed to have a thickness of 500 to 1500 kPa. The first conductive layer 37 is formed of a silicon film such as an amorphous silicon film or a polysilicon film with a thickness of 500 to 1500 kPa at 540 to 620 ° C by LPCVD using a mixed gas of SIH4, Si2H6 and PH3. In the embodiment of the present invention, the laminate structure of the temporary films 36 and 38 and the conductive layer 37 is formed as a single layer, but the laminate structure may be formed in multiple layers. Capacitor capacity can be obtained. Next, as shown in FIG. 3B, a photoresist is applied on the second temporary film 38, and then patterned through a conventional photolithography process to form a photoresist pattern 39 having a predetermined pattern. do. The second temporary film 38, the first conductive layer 37, the first temporary film 36, and the etch stop layer 35 are sequentially removed by using the formed photoresist pattern 39 as a mask. do. At this time, by using a gas containing F, such as CF4 or CHF3 and a gas containing Cl, such as HCI or Cl2, the etching gas is etched by a method such as Reactive Iout Etching (RIE). Subsequently, after removing the photoresist pattern as shown in FIG. A conductive side wall 40 is formed on the side of the film. Next, as shown in FIG. 3 (d), the photoresist pattern 41 is formed again using the mask used in FIG. 3 (b), and the photoresist pattern 41 and the formed conductive side wall 40 are formed. The oxide layer, which is the first insulating layer 34, is selectively etched using the mask as a mask to form a contact hole to expose the transistor source (or drain) region. At this time, when the second temporary film 38, which is the top layer film of the laminated structure film, is an oxide film system such as SOG or CVD oxide film, a photoresist pattern is formed as described above, and the photoresist pattern and the conductive side wall are used as a mask. The oxide film 34 is etched to form a contact hole. However, when the second temporary film 38 is an organic insulating film, the oxide film 34 is etched using the conductive side wall 40 as a mask without forming a photoresist pattern. You can do it. On the other hand, as another embodiment of the present invention, it is also possible to form a laminated structure formed by stacking the temporary film and the conductive layer so that the uppermost layer becomes the conductive layer. The first insulating layer 34 is selectively etched using the uppermost conductive layer and the conductive side wall as a mask to form a contact hole. Subsequently, as shown in FIG. 3E, a conductive silicon film is formed to a thickness of 500-1500 Å as the second conductive layer 42 on the entire surface of the contact hole formed therein, so that the source of the conductive side wall 40 and the memory cell transistors are formed. (Or drain) is electrically connected. Next, as shown in FIG. 3 (f), the second conductive layer 42 and the second temporary film are formed using the photoresist pattern 43 formed by patterning a predetermined capacitor storage node pattern forming mask. (38) and selectively etch the first conductive layer 37 to expose the first temporary film 36. Subsequently, after removing the photoresist pattern as shown in FIG. 3 (g), the first conductive layer 37 and the conductive side wall 40 are removed by wet etching the second and first temporary films. And a capacitor storage node 44 formed of the second conductive layer 42. In this case, when the temporary film is an oxide film system, an aqueous solution containing F, such as HF, is used, and when the temporary film is an organic insulating film, it is removed by wet etching using a developer or a mixture of hydrazine hydrate and polyylamine. A capacitor dielectric film 45, for example, a silicon nitride film and an oxide film, is formed on the entire surface of the capacitor storage node having the multilayer structure formed as described above, and then a conductive silicon film is formed on the front surface thereof at a thickness of about 2000 kPa at 540 to 620 캜. The capacitor plate electrode 46 is formed by evaporation to complete the capacitor of the semiconductor memory device. As described above, the present invention can improve the mechanical strength of the conductive layer around the contact flow concentrated in the lower layer of the laminated film by supporting the conductive laminated film of the capacitor storage node by the conductive side wall and the upper conductive film connected to the conductive side wall. As the aspect ratio of the contact hole is improved through the conductive side wall, the coating property of the conductive film is improved. In addition, as shown in FIG. 4, which is an enlarged view of part I of FIG. 3 (e), vertical misalignment between the upper temporary film (second temporary film) and the conductive side wall is caused by excessive etch back when the conductive side wall is formed. Even if this occurs, it is connected by the upper conductive film, so that a margin in the process is secured and the implementation thereof is easy.

Claims (8)

Forming a memory cell transistor including a gate electrode, a source and a drain region on a semiconductor substrate, forming an insulating film on the memory cell transistor, forming an etch stop film on the insulating film, and forming the etch stop film; Alternately stacking a temporary film and a conductive layer on the film; forming a multilayer film having a multilayer structure in which the uppermost layer becomes a temporary film; and selectively removing the laminated film by a dry etching process to expose the insulating film to form a predetermined laminated film pattern. And forming a conductive side wall on the sidewall of the stacked layer pattern, and selectively forming an insulating layer using the conductive side wall as a mask to expose a source (or drain) region of the memory cell transistor. And an inner surface of the contact hole, the conductive side wall, and the laminated structure. Forming on the upper conductive film and the upper conductive film and a method of manufacturing a semiconductor memory device comprising the steps and the step of removing the laminated film temporarily film patterned in the stacked film capacitor storage node pattern. The method of claim 1, wherein the etch stop layer is formed of a nitride layer. The method of manufacturing a semiconductor memory device according to claim 1, wherein the temporary film is formed of an organic insulating film such as polyamide or an inorganic insulating film such as SOG or oxide film. The method of claim 1, wherein the conductive layer is formed of conductive amorphous silicon or conductive polysilicon. The method of claim 1, wherein the conductive side wall is formed by forming a conductive film on the entire surface of the semiconductor substrate on which the laminated film pattern is formed and then etching back the conductive film. The method of claim 1, wherein in the forming of the contact hole, the insulating layer is selectively etched using a predetermined photoresist pattern together with the conductive side wall as a mask. The method of claim 6, wherein the photoresist pattern is formed by using a mask at the time of forming the laminated film pattern. The semiconductor memory device according to claim 1, further comprising, after removing the temporary film, forming a capacitor dielectric film on the entire surface of the resultant, and forming a capacitor plate electrode on the entire surface of the capacitor dielectric film. Manufacturing method.