JP3447792B2 - Method for manufacturing semiconductor memory - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a manufacturing <br/> method for producing a semiconductor memory equipment, a method of manufacturing a Capacity data in particular with a strike ridge nodes a multilayer laminated structure.

[0002]

2. Description of the Related Art With the development of semiconductor devices, the work of integrating a large number of elements on one semiconductor chip with a high degree of integration is actively underway. In particular, in a DRAM memory cell, various cell structures have been proposed to minimize the size of the device.

For high integration, it is desirable that the memory cell is composed of one transistor and one capacitor in order to minimize the area occupied on the chip. As described above, in the memory cell including one transistor and one capacitor, the signal charge is stored in the storage node of the capacitor connected to the transistor (switching transistor).
stored in the node). Therefore, when the size of the memory cell becomes smaller due to the higher integration of the semiconductor memory device, the size of the capacitor becomes smaller, and the number of signal charges that can be stored in the storage node also decreases. Therefore, in order to transmit a desired signal without malfunctioning, the capacitor storage node of the memory cell must have a surface area larger than an arbitrary set value in order to secure the capacitance of the capacitor required for signal transmission. I have to. Therefore, it is necessary to secure a relatively large surface area even if the capacitor storage node is limited on the semiconductor substrate due to the size reduction of the memory cell.

As described above, among the various memory cell structures proposed to increase the surface area of the capacitor storage node, the stacked capacitor has a small influence of soft error while achieving high integration. It is a capacitor structure that has the advantage of receiving. In addition, a memory cell having a stack-structured capacitor is advantageous in mass production and has an advantage that the process is easy.

As one of the structures of stack capacitors for increasing the capacitance of capacitors, Ema et al.
M pp. A capacitor having a fin structure disclosed in "592-595, 1988" will be described with reference to FIGS. As shown in FIG. 1, after a memory cell transistor including a gate electrode 1 and a source / drain 2 is formed on a semiconductor substrate 100, a nitride film 3 is formed on the memory cell transistor as shown in FIG. And sequentially forming a first oxide film 4, a first polysilicon layer 5 and a second oxide film 6 as shown in FIG. 3, then, the second oxide film 6, the first polysilicon layer 5, the A contact hole is formed by selectively etching the first oxide film 4.

As shown in FIG. 4, after depositing a second polysilicon layer 7 over the entire surface of the product obtained in the above process, the process shown in FIG.
As shown in FIG. 5, the fin-shaped capacitor storage node is formed by selectively etching the second polysilicon layer 7, the second oxide film 6, and the first polysilicon layer 5. After removing the second oxide film 6 and the first oxide film 4 by wet etching as shown in FIG. 6, a capacitor dielectric film is formed on the entire surface of the formed capacitor storage node as shown in FIG. 8 is formed, a capacitor plate electrode 9 is formed on the entire surface of the capacitor dielectric film 8 to complete the capacitor of the semiconductor memory device.

In the above-described capacitor having a fin-structured storage node, as the number of stacked fins increases, the mechanical strength of the polysilicon layer in the central portion connected to each stacked film and holding them increases. There is a possibility that the strength becomes weak and defects occur. Also, as the number of stacked fins increases, the aspect ratio of the contact hole for connecting the memory cell transistor and the capacitor increases, so that the storage node of the stacked capacitor is formed. The adherence of the polysilicon support film, which is the uppermost conductive layer, is deteriorated.

In order to solve the above problems, H.264. Got
ou et al. forms a conductive base layer connected to the source / drain of a memory cell transistor and connects the fin-shaped laminated film to the conductive sidewall from one corner of the conductive base layer, so that the sidewall supports the laminated film. A technique has been proposed (US Pat. No. 5,126,810).

The above technique will be described with reference to FIGS. As shown in FIG.
After the memory cell transistor including the gate electrode 11 and the source / drain region 12 is formed by the OS transistor manufacturing process, the interlayer insulating film 13 and the etching stop film 1 are formed on the entire surface of the substrate on which the memory cell transistor is formed.
4 and the buffer layer 15 are sequentially formed using the CVD method. The buffer layer 15, the etch stop layer 14 and the interlayer insulating layer 13 are selectively etched to form a contact hole so that the source (or drain) region 12 of the transistor is exposed, and then a polysilicon layer is formed on the entire surface of the contact hole. 16, 18, 20 and oxide films 17, 19, 2
1 and 1 are alternately laminated in multiple layers.

As shown in FIG. 9, the multi-layered polysilicon layers 16, 18, 21 and the oxide film 17, which are alternately laminated, are formed.
19 and 21 are selectively etched to form a predetermined pattern. As shown in FIG. 10, after polysilicon is deposited on the entire surface, anisotropic etching is performed to form polysilicon sidewalls 22. The polysilicon side wall 22 formed in this manner has the multi-layered polysilicon layers 16, 18 and 21 laminated via the multi-layered oxide films 17, 19 and 21.
It also serves as an electrical passage while supporting the.

As shown in FIG. 11, a photoresist 23 is applied to the entire surface of the product obtained in the above step and then patterned by a normal photo-etching process to expose one side of the formed polysilicon side wall 22. After that, the exposed polysilicon side wall 22 is etched. As shown in FIG. 12, after removing the photoresist pattern, removing the buffer layer 15, and removing the multilayer oxide films 17, 19 and 21 by wet etching, the multilayer polysilicon layers 16, 18 and A capacitor storage node consisting of 21 and a polysilicon sidewall 22 supporting it is completed.

As shown in FIG. 13, after forming a capacitor dielectric film 24 on the entire surface of the capacitor storage node, a dielectric material is deposited on the entire surface of the dielectric film 24 and patterned to form a capacitor plate. The capacitor is completed by forming the electrode 26.

[0013]

However, in such a conventional technique, the load is concentrated on the side wall of the conductive base layer (polysilicon layer) 16 on the contact hole for connecting the transistor and the capacitor. , The mechanical strength of the storage node of the laminated structure also tends to be weak, and the etching degree at the time of anisotropic etching for forming the polysilicon side wall is precisely adjusted so that the upper portion of the laminated film is not etched. There were some difficulties in the process, such as having to adjust. An object of the present invention is to improve mechanical strength in a capacitor storage node having a laminated structure and adhesion of a step of a conductive layer which is the uppermost layer of the laminated structure.

[0014]

In order to achieve the above object, according to the present invention, a semiconductor substrate 100, a gate electrode 33 formed on the semiconductor substrate 100, and a source / source electrode.
A memory cell transistor including a drain region 32,
Source / drain region 3 of the memory cell transistor
2, a contact hole exposing a certain portion, an insulating film 34 formed on the memory cell transistor, a conductive side wall 40 formed on the insulating film above the contact hole, and a side surface of the conductive side wall 40. And a multi-layered conductive laminated film 37 that is horizontally extended outside the contact hole and is formed along the inner side and the conductive side wall of the contact hole to form the source (or drain) of the transistor. And a capacitor storage node composed of the upper conductive film 42 connected to.

A method of manufacturing a semiconductor memory device according to the present invention to achieve the above object comprises the steps of forming a memory cell transistor composed of a gate electrode 33 and a source / drain region 32 on a semiconductor substrate 100, and the memory. A multilayer structure in which an insulating film 34 is formed above the cell transistor, an etching stop film 35 is formed on the insulating film 34, and a temporary film and a conductive layer are alternately stacked on the etching stop film 35. Forming a laminated film, forming a predetermined laminated film pattern by selectively etching the formed laminated film, forming a conductive side wall 40 on a side surface of the laminated film pattern, and forming the conductive film. A step of selectively etching the insulating film 34 using the sidewall 40 as a mask to expose the source (or drain) region of the memory cell transistor. Forming an upper conductive film 42 on the inner surface of the formed contact hole, the conductive sidewall, and the laminated structure film; patterning the upper conductive film 42 and the laminated film with a capacitor storage node pattern; Removing the temporary film of the laminated film.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device of the present invention will be described in detail below with reference to the drawings. FIG. 21 shows a stacked capacitor structure of a semiconductor memory device according to an embodiment of the present invention. As shown in FIG. 21, a semiconductor memory device according to an exemplary embodiment of the present invention includes a contact hole formed on a source (drain) 32 of a memory cell transistor for electrical connection between the capacitor and the memory cell transistor. An insulating film 34 is provided on the memory cell transistor, and the insulating film 3 at the edge portion above the contact hole is provided.
4 is provided with a conductive side wall 40. Further, a conductive layer 37 connected to a side surface of the conductive side wall 40 and extending horizontally outside the contact hole, and a source of the transistor formed along the inner surface of the contact hole and the conductive side wall 40. Alternatively, an upper conductive film 42 connected to the drain) is formed, and the conductive sidewall 40, the conductive layer 37, and the upper conductive film 42 form a storage node. The conductive layer 37 connected to the side surface of the conductive sidewall is formed of a single layer in the embodiment shown in FIG. 21, but may be formed of multiple layers to increase the capacitance of the capacitor.

As described above, since the capacitor storage node of the semiconductor memory device of the present invention supports the conductive laminated film by the conductive side wall 40 and the upper conductive film 42, the load of the laminated film is concentrated in the contact hole. The mechanical strength of the surrounding storage node portion can be improved.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS.
First, as shown in FIG. 14, a semiconductor substrate 1 separated into an active region and a blocking isolation region by a field oxide film 31.
00, a gate electrode 33 and a source / drain region 32 are formed by a general MOS transistor manufacturing process to complete the transistor. After forming a first insulating film 34, for example, an oxide film, on the semiconductor substrate having the transistor formed thereon, an etching stopper film 35 and a first temporary film (D
isposable film) 36, first conductive layer 3
7 and the second temporary film 38 are sequentially formed.

The etching stop film 35 is, for example, a nitride film formed by a low pressure chemical vapor deposition (LPCVD) method or a plasma chemical vapor deposition (PECVD) method from 500Å to 1000.
The first temporary film 36 and the second temporary film 38 are formed to have a thickness of Å. The first temporary film 36 and the second temporary film 38 are made of an organic insulating film such as polyimide or SOG (Spin on Glass).
s), an inorganic insulating film such as a silicon nitride film is used.
This is formed by an organic insulating film or SOG (spin coating) method, and the inorganic insulating film is formed by chemical vapor deposition (C
VD) method. The first temporary film 36 and the second temporary film 38 are formed to a thickness of 500Å to 1500Å.

As the first conductive layer 37, a silicon film such as an amorphous silicon film or a polysilicon film is formed by SiH ₄ or S.
It is formed at a thickness of 500 to 1500Å at 540 ° C. to 620 ° C. by the LPCVD method using a mixed gas of i ₂ H ₆ and PH ₃ .

In one embodiment of the present invention, the temporary film 36,
38 and the conductive layer 37 are formed as a single layer,
The laminated structure may be formed in multiple layers, and when formed in multiple layers, a larger capacitor capacitance can be obtained. As shown in FIG. 15, a photoresist is coated on the second temporary film 38 and then patterned by a normal photo-etching process to form a photoresist pattern 39 having a predetermined pattern. Using the photoresist pattern 39 formed in this way as a mask, the second temporary film 38,
The first conductive layer 37, the first temporary film 36, and the etching stop film 35 are sequentially etched and removed. At this time, a gas containing F such as CF ₄ or CHF ₃ and a gas containing Cl such as HCl or Cl ₂ are used as etching gas, and etching is performed by a method such as RIE.

As shown in FIG. 16, after removing the photoresist pattern, a conductive silicon film is formed on the entire surface by LPCVD at 540 ° C. to 620 ° C. for 200 to 2 ° C.
The conductive sidewall 40 is formed on the side surface of the laminated structure film by etching back with a thickness of 000Å.

As shown in FIG. 17, a photoresist pattern 41 is re-formed using the mask used in FIG. 15, and the photoresist pattern 41 and the formed conductive sidewall 40 are used as a mask for the first insulation. Membrane 34
The oxide film is selectively etched to form a contact hole so that the source (or drain) region of the transistor is exposed. At this time, when the second temporary film 38, which is the uppermost layer film of the laminated structure film, is an oxide film system such as SOG or CVD oxide film, a photoresist pattern is formed as described above and the photoresist is formed. The oxide film 34 is etched using the pattern and the conductive sidewall as a mask to form a contact hole.
When the temporary film 38 is an organic insulating film, the photoresist pattern may not be formed, and the oxide film 34 may be etched by using the conductive sidewall 40 as a mask.

On the other hand, as another embodiment of the present invention, it is also possible to form a laminated structure in which the temporary film and the conductive layer are laminated so that the uppermost layer is the conductive layer. In this case, there is no need for a separate photoresist mask when forming the contact hole, and the first conductive layer as the uppermost layer of the laminated structure and the conductive sidewall are used as a mask for the first photoresist layer.
The insulating film 34 is selectively etched to form a contact hole. As shown in FIG. 18, as a second conductive layer 42, a conductive silicon film having a thickness of 500Å to 1500Å is formed on the entire surface where the contact hole is formed, and the conductive sidewall 40 and the source of the memory cell transistor ( Or the drain) 32 is electrically connected.

Next, as shown in FIG. 19, the second conductive layer 42, the second temporary film 38, and the second temporary film 38 are formed by using the photoresist pattern 43 formed by patterning by applying a predetermined capacitor storage node pattern forming mask. First conductive film 37 is selectively etched to expose first temporary film 36. As shown in FIG. 20, after the photoresist pattern is removed, the first and second provisional films are removed by wet etching to form the first conductive layer 37, the conductive sidewall 40, and the second conductive layer 42. A capacitor storage node 44 is formed. At this time, when the temporary film is an oxide film system, an aqueous solution containing F such as HF is used, and when the temporary film is an organic insulating film, a developing solution (Developepe) is used.
r) or wet etching using a mixed solution of hydrazine hydrate and polyamine or the like.

A capacitor dielectric film 45, for example, a laminated film of a silicon nitride film and an oxide film is formed on the entire surface of the multilayer capacitor storage node formed as described above, and then a conductive silicon film is formed on the entire surface. Is deposited at a thickness of 2000Å at 540 ° C. to 620 ° C. by the LPCVD method to form the capacitor plate electrode 46, thereby completing the capacitor of the semiconductor memory device.

[0027]

As described above, according to the present invention,
Since the conductive stacked film of the capacitor storage node is supported by the conductive side wall and the upper conductive film connected to the conductive side wall, the mechanical structure of the conductive layer around the contact hole concentrated in the lower layer of the stacked film is reduced. The strength can be improved, the aspect ratio of the contact hole is improved through the conductive side wall, and the adherence of the upper conductive film is improved. Further, as shown in an enlarged sectional view (FIG. 22) of the portion I of FIG. 18,
Even if misalignment occurs between the upper temporary film (second temporary film) and the conductive sidewall due to too much etching back during the formation of the conductive sidewall, the upper conductive film 42 still connects them.
A process margin is secured, which facilitates implementation.

[Brief description of drawings]

FIG. 1 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 2 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 3 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 4 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 5 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 6 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 7 is a process diagram showing a method of manufacturing a capacitor of a semiconductor memory device according to a conventional technique.

FIG. 8 is a process drawing showing a manufacturing method according to another conventional technique.

FIG. 9 is a process drawing showing a manufacturing method according to another conventional technique.

FIG. 10 is a process drawing showing a manufacturing method according to another conventional technique.

FIG. 11 is a process chart showing a manufacturing method according to another conventional technique.

FIG. 12 is a process drawing showing a manufacturing method according to another conventional technique.

FIG. 13 is a process drawing showing a manufacturing method according to another conventional technique.

FIG. 14 is a process diagram showing a method of manufacturing a capacitor of a memory device according to an embodiment of the present invention.

FIG. 15 is a process diagram showing a method of manufacturing a capacitor of a memory device according to an embodiment of the present invention.

FIG. 16 is a process diagram showing a method of manufacturing a capacitor of a memory device according to an embodiment of the present invention.

FIG. 17 is a process diagram showing a method of manufacturing a capacitor of a memory device according to an embodiment of the present invention.

FIG. 18 is a process diagram showing a method of manufacturing a capacitor of a memory device according to an embodiment of the present invention.

FIG. 19 is a process diagram showing a method of manufacturing a capacitor of a memory device according to an embodiment of the present invention.

FIG. 20 is a process diagram showing a method of manufacturing a capacitor in a memory device according to an embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating a capacitor of a memory device according to an exemplary embodiment of the present invention.

FIG. 22 is an enlarged view of the main part.

[Explanation of symbols]

100 semiconductor substrate 31 Field oxide film 32 Source / Drain area 33 Gate electrode 34 Insulating film 35 Etching stop film 36 First temporary film 37 First Conductive Layer 38 Second temporary film 39,41,43 Photoresist pattern 40 conductive sidewall 42 upper conductive film 44 Capacitor storage node 45 Capacitor dielectric film 46 Capacitor plate electrode

─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-6-244377 (JP, A) JP-A-4-158569 (JP, A) JP-A-5-243491 (JP, A) JP-A-5- 235292 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/822 H01L 27/04 H01L 27/108

Claims (9)

(57) [Claims] 1. A step of forming a memory cell transistor including a gate electrode (33) and a source / drain region (32) on a semiconductor substrate (100), and an insulating film (which is an oxide film) above the memory cell transistor. 34), a step of forming an etching stop film (35) on the insulating film (34), and a temporary film that is an oxide-based inorganic insulating film on the etching stop film (35). Forming a laminated film having a multilayer structure by alternately laminating conductive layers; forming a predetermined laminated film pattern by selectively etching the formed laminated film; and a side surface of the laminated film pattern. Forming conductive sidewalls (40) on the insulating film (3) using the conductive sidewalls (40) as a mask.
4) Selectively etching to expose the source / drain regions of the memory cell transistor to form a contact hole; and an upper conductive layer on the inner surface of the formed contact hole, the conductive sidewall, and the laminated film. Forming a film (42); patterning the upper conductive film (42) and the laminated film with a capacitor storage node pattern to form a capacitor storage node; and And a step of removing it by wet etching using an aqueous solution containing. Wherein said etch stop layer, a method of manufacturing a semiconductor memory device of claim 1 wherein characterized by forming a nitride layer. Wherein the conductive layer, a method of manufacturing a semiconductor memory device of claim 1 wherein characterized by forming an amorphous silicon film or a conductive polysilicon. 4. The conductive sidewall has a conductive film formed on the entire surface of the semiconductor substrate having the laminated film pattern formed thereon,
The method of manufacturing a semiconductor memory device according to claim 1 , wherein the step of etching back this is performed. In 5. A step of forming the contact hole, wherein the first term, characterized by selectively etching the insulating film as a mask a predetermined photoresist pattern (41) together with said conductive sidewall Of manufacturing a semiconductor memory device of. 6. Before notated O DOO resist pattern manufacturing method of the fifth term semiconductor memory device, wherein the forming by using a mask in forming the laminated film pattern. 7. The step of removing the temporary film after the step of removing the temporary film .
Inside surface of the contact hole of the trig node
Forming a capacitor dielectric film (45) on the surface of all the hands, except for the surface, and forming a capacitor plate electrode (46) on the entire surface of the capacitor dielectric film (45),
The method of manufacturing a semiconductor memory device according to claim 1 , further comprising: 8. The semiconductor memory device according to claim 1 , wherein the stacking step is performed such that the uppermost layer of the stacked film formed by alternately stacking the temporary film and the conductive layer becomes the temporary film. Manufacturing method. 9. The semiconductor memory device according to claim 1 , wherein the stacking step is performed so that the uppermost layer of the stacked film formed by alternately stacking the temporary film and the conductive layer becomes the conductive layer. Manufacturing method.