CN117500365A

CN117500365A - Method for manufacturing capacitor

Info

Publication number: CN117500365A
Application number: CN202311849598.7A
Authority: CN
Inventors: 宛伟
Original assignee: Changxin Xinqiao Storage Technology Co ltd
Current assignee: Changxin Xinqiao Storage Technology Co ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-02-02
Anticipated expiration: 2043-12-29
Also published as: CN117500365B

Abstract

The embodiment of the disclosure relates to a preparation method of a capacitor, which comprises the following steps: providing a substrate comprising a first region and a second region; forming a bottom supporting layer, a first sacrificial layer, an intermediate supporting layer, a second sacrificial layer and a top supporting layer on a substrate, wherein the intermediate supporting layer on the second area comprises a first sub-layer and a second sub-layer, the material of the first sub-layer is the same as that of the intermediate supporting layer on the first area, the thickness of the first sub-layer is smaller than that of the intermediate supporting layer on the first area, and the etching selection ratio of the second sub-layer to the first sub-layer is larger than 1; forming a plurality of capacitor holes penetrating the bottom support layer, the first sacrificial layer, the middle support layer, the second sacrificial layer and the top support layer; forming a lower electrode in the plurality of capacitor holes; forming openings penetrating the top support layer in the plurality of second regions, respectively, the openings exposing at least three lower electrodes; removing the second sacrificial layer, the intermediate support layer on the second region and the first sacrificial layer along the opening; a dielectric layer and an upper electrode are sequentially formed on the surface of the lower electrode.

Description

Method for manufacturing capacitor

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a preparation method of a capacitor.

Background

The memory generally includes a capacitor and a transistor, a drain of the transistor is connected to a bit line structure, a source of the transistor is connected to the capacitor, and a channel region of the transistor is opened to enable reading data information stored in the capacitor through the bit line structure or writing data information into the capacitor through the bit line structure for storage.

With the increase of the integration level of the memory, the size of the memory is smaller, but the number of the capacitors in the memory is larger, so that in order to support the capacitors, the risk of collapse of the capacitors is avoided, and a support layer for supporting the capacitors is prepared.

However, the performance of the capacitor prepared by the current preparation process is poor.

Disclosure of Invention

The embodiment of the disclosure provides a preparation method of a capacitor, which is at least beneficial to improving the performance of the prepared capacitor.

The embodiment of the disclosure provides a preparation method of a capacitor, which comprises the following steps: providing a substrate comprising a first region and a plurality of second regions, the first region being located between adjacent second regions; sequentially forming a stacked bottom supporting layer, a first sacrificial layer, an intermediate supporting layer, a second sacrificial layer and a top supporting layer on the substrate, wherein the intermediate supporting layer on the second area comprises a stacked first sub-layer and a second sub-layer, the material of the first sub-layer is the same as that of the intermediate supporting layer on the first area, the thickness of the first sub-layer is smaller than that of the intermediate supporting layer on the first area, and the etching selection ratio of the second sub-layer to the first sub-layer is larger than 1; forming a plurality of capacitor holes through the bottom support layer, the first sacrificial layer, the intermediate support layer, the second sacrificial layer, and the top support layer; forming a lower electrode in each of the plurality of capacitor holes; forming openings penetrating through the top support layer in the top support layer on the second areas respectively, wherein each opening at least exposes three adjacent lower electrodes; removing the second sacrificial layer, the middle supporting layer on the second area and the first sacrificial layer along the opening, and supporting the lower electrode by the rest of the bottom supporting layer, the middle supporting layer and the top supporting layer; forming a dielectric layer on the surface of the lower electrode; and forming an upper electrode on the dielectric layer.

In some embodiments, a first sub-layer is formed on top of the second sub-layer, the second sub-layer being in contact with the first sacrificial layer.

In some embodiments, the method of forming the intermediate support layer includes: forming an initial intermediate support layer on top of the first region and the second region; etching the initial intermediate support layer on the second region to form a plurality of spaced first through holes exposing a portion of the top surface of the first sacrificial layer; forming a second sub-layer filling the first through hole; and forming a first material layer on the top surface of the second sub-layer and the top surface of the rest initial intermediate support layer, wherein the first material layer positioned on the top surface of the second sub-layer is used as the first sub-layer, and the rest first material layer and the rest initial intermediate support layer form the intermediate support layer on the first area.

In some embodiments, the material of the second sub-layer is the same as the material of the first sacrificial layer.

In some embodiments, a second sub-layer is located on top of the first sub-layer, in contact with the second sacrificial layer, and the material of the second sub-layer is the same as the material of the second sacrificial layer.

In some embodiments, the method of forming the intermediate support layer includes: forming an initial intermediate support layer over the first region and the second region; etching the initial intermediate support layer on the second region to form a plurality of first through holes at intervals, wherein part of the top surface of the first sacrificial layer is exposed out of the bottom of each first through hole; forming a first sub-layer filled in part of the first through hole, wherein the first sub-layer is in contact with the first sacrificial layer; and forming the second sub-layer filled with the rest of the first through holes.

In some embodiments, the intermediate support layer on the first region includes a stacked third sub-layer and a fourth sub-layer, the material of the first sub-layer is the same as the material of the fourth sub-layer, and the etch selectivity of the fourth sub-layer to the third sub-layer is greater than 1.

In some embodiments, the intermediate support layer further includes a fifth sub-layer continuously located on the first region and the second region, an etching selectivity of the second sub-layer to the fifth sub-layer is greater than 1, the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer are all located on top of the fifth sub-layer, and the fifth sub-layer is in contact with the first sacrificial layer.

In some embodiments, the method of forming the intermediate support layer includes: forming a fifth sub-layer and a second material layer which are sequentially stacked on the first region and the second region; etching the second material layer on the second region to form a plurality of second through holes at intervals, wherein part of the top surface of the fifth sub-layer is exposed by the second through holes, and the second material layer on the first region forms the third sub-layer; forming a second sub-layer filling the second through hole; and forming a third material layer on the top surface of the second sub-layer and the top surface of the third sub-layer, wherein the third material layer on the top surface of the second sub-layer is used as the first sub-layer, and the third material layer on the top surface of the third sub-layer is used as the fourth sub-layer.

In some embodiments, the thickness of the second sub-layer is greater than the thickness of the first sub-layer and greater than the thickness of the fifth sub-layer.

In the technical scheme of the preparation method of the capacitor provided by the embodiment of the disclosure, the opening is opposite to the second area, so that only the middle supporting layer and the first sacrificial layer on the second area can be removed along the opening, part of the side wall of the lower electrode is exposed, and the rest of the middle supporting layer on the first area supports the lower electrode. The intermediate support layer on the second region comprises a first sub-layer and a second sub-layer which are stacked, and the etching selectivity ratio of the second sub-layer to the first sub-layer is greater than 1, namely the second sub-layer is easier to etch compared with the first sub-layer. The material of the first sub-layer is the same as that of the intermediate support layer on the first region, and the thickness is smaller, so that the intermediate support layer on the second region is easier to etch than the intermediate support layer on the first region, the etching time of the intermediate support layer on the second region is reduced, the problem that the exposed lower electrode side wall is damaged due to excessive etching time of the intermediate support layer on the second region in an etching process is avoided, and the performance of the formed capacitor is improved.

The material of the first sub-layer is the same as that of the intermediate support layer on the first region, and is more difficult to etch than the second sub-layer, so that the first sub-layer has better support capability. In the process of removing the top supporting layer, the second sacrificial layer and the middle supporting layer, the first sub-layer can play a good supporting role on the first sacrificial layer and the top supporting layer, and collapse of the capacitor holes is avoided. The thickness of the first sub-layer is smaller than that of the middle supporting layer on the first area, so that the problem that the middle supporting layer on the second area is difficult to etch due to the fact that the thickness of the first sub-layer is too large can be avoided. That is, in the step of forming the intermediate support layer, the first sub-layer and the second sub-layer are formed on the second area, so that the two properties of strong supporting capability and high etching rate of the intermediate support layer on the second area in the etching process can be considered, the phenomena that the intermediate support layer is too thin, the capacitor column is easy to bend and collapse and the like are avoided, the intermediate support layer is too thick, the situation that the intermediate support layer is not etched to the bottom at the moment of opening the intermediate support layer for the second time, or the electrode is damaged due to overlong etching are avoided.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic top view structure corresponding to a step of providing a substrate in a method for manufacturing a capacitor according to an embodiment of the disclosure;

FIG. 2 is a schematic cross-sectional view of the AA' direction in FIG. 1;

fig. 3 is a schematic cross-sectional structure diagram corresponding to a step of forming a top support layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 4 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial intermediate support layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 5 is a schematic cross-sectional structure diagram corresponding to a step of forming a first mask layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 6 is a schematic cross-sectional structure corresponding to a step of forming a first through hole in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 7 is a schematic cross-sectional structure diagram corresponding to a step of forming a first sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 8 is a schematic cross-sectional structure corresponding to a step of forming a second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 9 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial second sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure;

Fig. 10 is a schematic cross-sectional structure diagram corresponding to a step of forming a second sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 11 is a schematic cross-sectional structure corresponding to a step of forming a first material layer in another method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 12 is a schematic cross-sectional structure diagram corresponding to a step of forming a fifth sub-layer and a second material layer in a method for manufacturing a capacitor according to another embodiment of the disclosure;

fig. 13 is a schematic cross-sectional structure corresponding to a step of forming a second mask layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 14 is a schematic cross-sectional structure corresponding to a step of forming a second through hole in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 15 is a schematic cross-sectional structure corresponding to a step of forming an initial second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 16 is a schematic cross-sectional structure corresponding to a step of forming a second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 17 is a schematic cross-sectional structure corresponding to a step of forming a third material layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

Fig. 18 is a schematic cross-sectional structure corresponding to a step of forming a second through hole in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 19 is a schematic cross-sectional structure corresponding to a step of forming a second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 20 is a schematic cross-sectional structure corresponding to a step of forming a third material layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 21 is a schematic cross-sectional structure corresponding to a step of forming a capacitor hole in a method for manufacturing a capacitor according to an embodiment of the disclosure;

FIG. 22 is a top view of a top surface of a substrate in a method of fabricating a capacitor according to one embodiment of the present disclosure;

FIG. 23 is a schematic cross-sectional view of a capacitor according to an embodiment of the present disclosure;

fig. 24 is a schematic cross-sectional structure corresponding to a step of forming a fifth mask opening in a method for manufacturing a capacitor according to an embodiment of the disclosure;

FIG. 25 is another top view of a top surface of a substrate in a method of fabricating a capacitor according to one embodiment of the present disclosure;

Fig. 26 is a schematic cross-sectional structure corresponding to a step of forming an opening in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 27 is a schematic cross-sectional structure diagram corresponding to a step of removing the second sacrificial layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 28 is a schematic cross-sectional structure diagram corresponding to a step of removing a first sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 29 is a schematic cross-sectional structure corresponding to a step of removing the second sacrificial layer in another method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 30 is a schematic cross-sectional structure diagram corresponding to a step of removing a first sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 31 is a schematic cross-sectional structure diagram corresponding to a step of removing a second sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure;

FIG. 32 is a schematic cross-sectional view illustrating a step of removing the second sacrificial layer in a method for manufacturing a capacitor according to an embodiment of the present disclosure;

fig. 33 is a schematic cross-sectional structure diagram corresponding to a step of removing a first sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

Fig. 34 is a schematic cross-sectional structure diagram corresponding to a step of removing the second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 35 is a schematic cross-sectional structure corresponding to a step of removing a fifth sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 36 is a schematic cross-sectional structure diagram corresponding to a step of removing the first sacrificial layer in a method for manufacturing a capacitor according to an embodiment of the disclosure;

fig. 37 is a schematic cross-sectional view of a capacitor according to an embodiment of the present disclosure, where the step of forming the dielectric layer and the upper electrode corresponds to the step of forming the upper electrode.

Detailed Description

In order to support the capacitor, a supporting layer is generally formed, and when the capacitor structure is manufactured, three supporting layers and a sacrificial layer between the three supporting layers may be formed first. Then, a plurality of capacitance holes penetrating through the three support layers and the sacrificial layer are formed, and a lower electrode is formed in the capacitance holes. And etching part of the top supporting layer by adopting a photoetching process to expose part of the surface of the sacrificial layer, and etching the exposed surface of the sacrificial layer to remove the sacrificial layer between the top supporting layer and the middle supporting layer and expose the outer side surface of the lower electrode and the surface of the middle supporting layer. Then, the exposed intermediate support layer is etched. In this step, only a portion of the intermediate support layer is etched to expose the sacrificial layer between the intermediate support layer and the bottom support layer, and the remaining portion of the intermediate support layer needs to remain to support the final formed capacitor. However, since the outer side surface of the lower electrode is exposed in the first etching step, if the thickness of the intermediate support layer is large, the etching time is too long, and damage is caused to the outer side surface of the lower electrode. If the thickness of the intermediate support layer is smaller, the support force of the intermediate support layer is insufficient, and the capacitor is easy to collapse in the etching process, so that the performance of the formed capacitor is poor.

The embodiment of the disclosure provides a method for manufacturing a capacitor, wherein an intermediate support layer on a second region comprises a first sub-layer and a second sub-layer which are stacked, the etching selection ratio of the second sub-layer to the first sub-layer is greater than 1, namely, compared with the first sub-layer, the second sub-layer is easier to etch, so that the whole etching of the intermediate support layer on the second region is easier, and the problem that the etching process etches the intermediate support layer on the second region for too much time to cause process damage to the exposed side wall of a lower electrode is avoided. The first sub-layer is more difficult to etch than the second sub-layer, and the material of the first sub-layer is the same as that of the intermediate support layer on the first region, so that the first sub-layer has better support capability. In the process of removing the top supporting layer, the second sacrificial layer and the middle supporting layer, the first sub-layer can play a good supporting role on the first sacrificial layer and the top supporting layer, and collapse of the capacitor holes is avoided. The thickness of the first sub-layer is smaller than that of the middle supporting layer on the first area, the problem that the middle supporting layer on the second area is difficult to etch due to the fact that the thickness of the first sub-layer is too large can be avoided, the etching rate is fast when the supporting force is good is guaranteed, the phenomenon that the middle supporting layer is too thin, a capacitor column is easy to bend and collapse and the like is avoided, the situation that the middle supporting layer is too thick, the middle supporting layer is not etched to the bottom when being opened for the second time, or the electrode is damaged due to overlong etching is avoided.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Referring to fig. 1 to 37, the method of manufacturing the capacitor includes the following steps.

First, a substrate 100 including a first region 1 and a plurality of second regions 2 is provided, the first region 1 being located between adjacent second regions 2.

Next, a stacked bottom support layer 101, a first sacrificial layer 102, an intermediate support layer, a second sacrificial layer 104, and a top support layer 105 are sequentially formed on the substrate 100, the intermediate support layer on the second region 2 includes a stacked first sub-layer 111 and second sub-layer 112, wherein the material of the first sub-layer 111 is the same as the material of the intermediate support layer 103 on the first region 1, the thickness is smaller than the thickness of the intermediate support layer 103 on the first region 1, and the etching selection ratio of the second sub-layer 112 to the first sub-layer 111 is greater than 1. I.e. the second sub-layer 112 is easier to etch than the first sub-layer 111. The material of the first sub-layer 111 is the same as that of the intermediate support layer 103 on the first region 1, and the thickness of the first sub-layer 111 is smaller than that of the intermediate support layer 103 on the first region 1, so that the intermediate support layer on the second region 2 is easier to etch than that of the intermediate support layer 103 on the first region 1.

Next, a plurality of capacitor holes 10 penetrating the bottom support layer 101, the first sacrificial layer 102, the intermediate support layer, the second sacrificial layer 104, and the top support layer 105 are formed.

Next, the lower electrodes 121 are formed in the plurality of capacitor holes 10, respectively. The outer sidewall of the lower electrode 121 is covered by the bottom support layer 101, the first sacrificial layer 102, the intermediate support layer, the second sacrificial layer 104, and the top support layer 105.

Next, in order to expose the outer sidewalls of the lower electrodes 121, openings 46 penetrating the top support layer 105 are formed in the top support layer 105 on the plurality of second regions 2, respectively, and each opening 46 exposes at least three adjacent lower electrodes 121. It will be appreciated that in a subsequent step, the second sacrificial layer 104, the intermediate support layer on the second region 2, and the first sacrificial layer 102, which are opposite the opening 46, can be removed more cleanly. The openings 46 are configured to expose at least the adjacent three lower electrodes 121, i.e. the top supporting layer 105 contacting the three lower electrodes 121 is partially removed, so that the second sacrificial layer 104 contacting the adjacent three lower electrodes 121, the middle supporting layer on the second region 2 and the first sacrificial layer 102 can be removed as cleanly as possible along the openings 46, and the surfaces of the three lower electrodes 121 are exposed, so that the contact area between the dielectric layer formed later and the outer side wall of the lower electrode 121 is larger.

Next, the second sacrificial layer 104, the intermediate support layer on the second region 2, and the first sacrificial layer 102 are removed along the opening 46 to expose the outer sidewall and the inner sidewall of the lower electrode 121, and the remaining bottom support layer 101, intermediate support layer, and top support layer 105 support the lower electrode 121. The outer side wall referred to in this disclosure is the side wall of the lower electrode 121 far from the center of the capacitor hole 10, and the inner side wall is the side wall of the lower electrode 121 facing the center of the capacitor hole 10.

Finally, a dielectric layer 123 is formed on the surface of the lower electrode 121; and, an upper electrode 122 is formed on the dielectric layer 123, and the lower electrode 121, the dielectric layer 123, and the upper electrode 122 constitute a capacitor.

Compared with the material of the middle supporting layer on the first area 1 and the material of the middle supporting layer on the second area 2 are the same, the middle supporting layer on the second area 2 is easier to etch compared with the middle supporting layer 103 on the first area 1, so that the etching time of the middle supporting layer on the second area 2 is reduced, the problem that the exposed side wall of the lower electrode 121 is damaged due to excessive etching time of the middle supporting layer on the second area 2 in an etching process is avoided, the performance of the formed capacitor is improved finally, and meanwhile, the middle supporting layer 103 on the first area 1 has a good supporting effect on the capacitor is guaranteed.

The material of the first sub-layer 111 is the same as that of the intermediate support layer 103 on the first region 1, and is more difficult to etch than the second sub-layer 112, so that the first sub-layer 111 has better support capability. In the etching process, the first sub-layer 111 can play a better supporting role on the first sacrificial layer 102 and the top supporting layer 105, so as to avoid collapse of the capacitor hole 10. The thickness of the first sub-layer 111 is smaller than that of the intermediate support layer 103 on the first region 1, so that the problem that the intermediate support layer on the second region 2 is difficult to etch due to the excessive thickness of the first sub-layer 111 can be avoided. That is, in the step of forming the intermediate support layer, the first sub-layer 111 and the second sub-layer 112 are formed on the second region 2, so that the two properties of strong support capability and fast etching rate of the intermediate support layer on the second region 2 in the etching process can be considered, damage to the exposed side wall of the first electrode layer is not easy to occur, and finally the performance of the formed capacitor is improved.

The steps of the method for manufacturing a capacitor and specific details thereof provided in the embodiments of the present disclosure are described in detail below.

Fig. 1 is a schematic top view structure corresponding to a step of providing a substrate in a method for manufacturing a capacitor according to an embodiment of the disclosure; FIG. 2 is a schematic cross-sectional view of the AA' direction in FIG. 1; fig. 3 is a schematic cross-sectional structure corresponding to a step of forming a top support layer in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 1 and 2, in some embodiments, the material of the substrate 100 is a semiconductor material. In some embodiments, the material of the substrate 100 is silicon. In some embodiments, the substrate 100 may also be germanium, silicon germanium, or silicon on insulator.

In some embodiments, the substrate 100 includes a plurality of active regions therein, each active region including: the transistor comprises a channel region, source and drain regions positioned on two sides of the channel region, wherein the channel region and the source and drain regions are used for forming the transistor. The capacitor is electrically connected with the active region, and in particular, can be electrically connected with one of the source and drain regions on both sides of the channel region.

Referring to fig. 3, in some embodiments, a plurality of capacitive contact structures 20 are also formed on the substrate 100, one capacitive contact structure 20 being electrically connected to one of the active regions, specifically one of the source and drain regions on either side of the channel region.

In some embodiments, an insulating layer is also formed on the substrate 100, and the capacitive contact structures 20 are located in the insulating layer, with adjacent capacitive contact structures 20 being separated by the insulating layer. In a specific example, the material of the insulating layer may include silicon nitride, and the material of the capacitor contact structure 20 may include a metal material, such as tungsten.

Referring to fig. 3, a bottom support layer 101, a first sacrificial layer 102, an intermediate support layer, a second sacrificial layer 104, and a top support layer 105 are formed on a side of the capacitor contact structure 20 remote from the substrate 100 such that a bottom of each capacitor hole is formed exposing one capacitor contact structure. In this way, the lower electrode formed in the capacitor hole is electrically contacted with the capacitor contact structure 20.

Referring to fig. 1 and 2, each of the plurality of second regions 2 extends from the top surface of the substrate 100 along the bottom surface of the substrate 100, and in the substrate 100, the regions other than the second regions 2 are the first regions 1.

Referring to fig. 1, in some embodiments, the plurality of second regions 2 may be arranged in an array, wherein two adjacent rows of the second regions 2 are staggered, and two adjacent columns of the second regions 2 are staggered. In a specific example, the cross-sectional shape of the second region 2 in the direction parallel to the top surface of the substrate 100 may be any one of a circle or an ellipse.

Referring to fig. 3, a bottom support layer 101, a first sacrificial layer 102, an intermediate support layer, a second sacrificial layer 104, and a top support layer 105 are sequentially formed on the top surface of the capacitor contact structure 20. In some embodiments, a deposition process may be used to sequentially form the bottom support layer 101 and the first sacrificial layer 102 on the insulating layer and the top surface of the capacitor contact structure 20.

In some embodiments, the material of the bottom support layer 101 is different from the material of the first sacrificial layer 102. Specifically, the etching selectivity of the material of the first sacrificial layer 102 and the bottom support layer 101 may be greater than 1, and thus, the bottom support layer 101 can be maintained using the etching selectivity in the step of removing the first sacrificial layer 102. In a specific example, the material of the first sacrificial layer 102 may be any one of borophosphosilicate glass or silicon oxide, and the material of the bottom support layer 101 may be silicon nitride. The first sacrificial layer 102 and the bottom support layer 101 may be formed using a plasma enhanced chemical vapor deposition method.

After the first sacrificial layer 102 is formed, an intermediate support layer is formed, and the intermediate support layer on the second region 2 includes a stacked first sub-layer and second sub-layer, and an etching selection ratio of the second sub-layer to the first sub-layer is greater than 1. The material of the first sub-layer is the same as the material of the intermediate support layer 103 on the first area 1, and the thickness of the first sub-layer is smaller than the thickness of the intermediate support layer 103 on the first area 1. Therefore, the middle supporting layer 103 on the first area 1 is more difficult to etch than the middle supporting layer on the second area 2, the supporting capability of the middle supporting layer 103 on the first area 1 is ensured, the time for removing the middle supporting layer on the second area 2 is shorter, the process damage to the exposed side wall of the lower electrode in the dry etching process is reduced, and the problem of bending and collapsing of the capacitor is avoided. The etch selectivity of the second sub-layer to the first sub-layer being greater than 1 means that the etch rate of the second sub-layer is greater than the etch rate of the first sub-layer under the same etch environment, and in some embodiments, the etch selectivity of the second sub-layer to the first sub-layer is greater than 2, greater than 3, or greater than 5, for example.

In some embodiments, the thickness of the second sub-layer is greater than the thickness of the first sub-layer. That is, for the intermediate support layer on the second region 2, the volume ratio of the second sub-layer that is more easily etched is larger than the volume ratio of the first sub-layer 111 that is more difficult to etch, so that the entire intermediate support layer on the second region 2 is more easily etched.

The step of forming the intermediate support layer will be described in detail below.

Fig. 4 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial intermediate support layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 5 is a schematic cross-sectional structure diagram corresponding to a step of forming a first mask layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 6 is a schematic cross-sectional structure corresponding to a step of forming a first through hole in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 7 is a schematic cross-sectional structure diagram corresponding to a step of forming a first sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 8 is a schematic cross-sectional structure corresponding to a step of forming a second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 4-8, in some embodiments, second sub-layer 112 is located on top of first sub-layer 111, in contact with second sacrificial layer 104, and the material of second sub-layer 112 is the same as the material of second sacrificial layer 104. In this manner, in the step of removing second sacrificial layer 104, second sub-layer 112 may be removed simultaneously, further shortening the process time for removing the intermediate support layer of second region 2.

In some embodiments, a method of forming an intermediate support layer includes the following steps.

Referring to fig. 4, an initial intermediate support layer 40 is formed on the top surface of the first sacrificial layer 102, and in particular, the initial intermediate support layer 40 is formed on the top surface of the first sacrificial layer 102 on the first region 1 (refer to fig. 1) and the second region 2 (refer to fig. 1). In some embodiments, the material of the initial intermediate support layer 40 is different from the material of the first sacrificial layer 102. In a specific example, the material of the initial intermediate support layer 40 may include any one of silicon carbonitride or silicon nitride, and the material of the first sacrificial layer 102 may include any one of borophosphosilicate glass or silicon oxide.

Referring to fig. 5 to 6, the initial intermediate support layer 40 on the second region 2 (refer to fig. 1) is etched to form a plurality of spaced first through holes 41, and the bottoms of the first through holes 41 expose a portion of the top surface of the first sacrificial layer 102.

In some embodiments, the method of forming the first via 41 may include the following steps.

Referring to fig. 5, first, a first mask layer 50 is formed on the top surface of the initial intermediate support layer 40, and the material of the first mask layer 50 may be photoresist. Next, a plurality of first mask openings 51 are formed in the first mask layer 50, the first mask openings 51 being opposite to the second regions 2. Specifically, the first mask opening 51 may be formed using a photolithography process.

Referring to fig. 6, the initial intermediate support layer 40 is etched along the first mask opening 51 (refer to fig. 5) to form the first via 41 in the initial intermediate support layer 40. The remaining initial intermediate support layer 40 is located in the first region 1, forming the intermediate support layer 103 on the first region 1, that is, the intermediate support layer 103 on the first region 1 is a continuous film layer.

Referring to fig. 7, a first sub-layer 111 is formed to fill a portion of the first via 41 (refer to fig. 6), the first sub-layer 111 being in contact with the first sacrificial layer 102. The first sub-layer 111 is only located in part of the first via 41, contacts the sidewall of the first via 41, and the thickness of the first sub-layer 111 is smaller than the height of the first via 41. In some embodiments, the first sub-layer 111 may be formed using a deposition process, for example, the first sub-layer 111 may be formed using an atomic layer deposition process. The material of the first sub-layer 111 is the same as that of the initial intermediate support layer 40, and is silicon nitride or silicon carbonitride.

Referring to fig. 8, a second sub-layer 112 is formed to fill the remaining first via 41.

With continued reference to fig. 8, in some embodiments, a deposition process may be employed to form the second sub-layer 112 in the first via 41. Since the material of the second sub-layer 112 is the same as that of the second sacrificial layer 104, in a specific example, the second sub-layer 112 and the second sacrificial layer 104 may be formed in the same process step, so that the process steps and the process flows can be saved. In some embodiments, the material of the second sub-layer 112 may be silicon oxide.

Fig. 9 is a schematic cross-sectional structure diagram corresponding to a step of forming an initial second sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 10 is a schematic cross-sectional structure diagram corresponding to a step of forming a second sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 11 is a schematic cross-sectional structure corresponding to a step of forming a first material layer in another method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 9-11, in some embodiments, a first sub-layer is formed on top of a second sub-layer 112, the second sub-layer 112 being in contact with the first sacrificial layer 102.

Referring to fig. 4, an initial intermediate support layer 40 is formed on the top surface of the first sacrificial layer 102, and in particular, the initial intermediate support layer 40 is formed on the top surface of the first sacrificial layer 102 on the first region 1 and the second region 2. In some embodiments, the material of the initial intermediate support layer 40 is different from the material of the first sacrificial layer 102. The initial intermediate support layer 40 is subsequently formed into the support structure of the capacitor, and therefore, the initial intermediate support layer 40 has a hardness greater than that of the first sacrificial layer 102. In a specific example, the material of the initial intermediate support layer 40 may include any one of silicon carbonitride or silicon nitride, and the material of the first sacrificial layer 102 may include any one of borophosphosilicate glass or silicon oxide.

Referring to fig. 6, the initial intermediate support layer 40 on the second region 2 is etched to form a plurality of spaced first through holes 41, the first through holes 41 exposing a portion of the top surface of the first sacrificial layer 102. The first through holes 41 are in one-to-one correspondence with the second areas 2, and each first through hole 41 is opposite to one second area 2. The method for forming the first through hole 41 may refer to the above description of the step of forming the first through hole 41, and will not be repeated.

Referring to fig. 9 to 10, a second sub-layer 112 filling the first via 41 is formed.

In some embodiments, the method of forming the second sub-layer 112 may include the following steps.

Referring to fig. 9, an initial second sub-layer 42 is formed in the first via 41 using a deposition process, the initial second sub-layer 42 being formed further higher than the top opening of the first via 41, the initial second sub-layer 42 higher than the top opening of the first via 41 being located on the top surface of the remaining initial intermediate support layer 40.

Referring to fig. 10, a planarization process is performed on the initial second sub-layer 42, removing the initial second sub-layer 42 higher than the top of the opening of the first via hole 41 and the initial second sub-layer 42 located on the top surface of the remaining initial intermediate support layer 40. Specifically, the planarization process may include a chemical mechanical polishing process.

Referring to fig. 11, a first material layer 43 is formed on the top surface of the second sub-layer 112 and the top surface of the remaining portion of the initial intermediate support layer 40, the first material layer 43 located on the top surface of the second sub-layer 112 is used as the first sub-layer, and the remaining portion of the first material layer 43 and the remaining portion of the initial intermediate support layer 40 form the intermediate support layer on the first region 1. The remaining portion of the first material layer 43 and the remaining portion of the initial intermediate support layer 40 are both located on the first region 1.

It is not difficult to find that, in the intermediate support layer formed by the above method, the overall thickness of the first sub-layer 111 and the second sub-layer 112 is the same as that of the intermediate support layer 103 on the first region 1, and the material of the first sub-layer 111 is the same as that of the first material layer 43 on the first region 1 for constituting the intermediate support layer.

In some embodiments, the material of the second sub-layer 112 may include silicon oxide, and the material of the first material layer 43 may include any of silicon nitride or silicon carbonitride, so that the hardness of the second sub-layer 112 is smaller than that of the first sub-layer 111, and the second sub-layer 112 can be etched more easily than the first sub-layer 111, while ensuring better supporting effect of the first sub-layer 111 and the intermediate supporting layer 103 on the first region 1.

In some embodiments, the material of the first material layer 43 may be the same as the material of the initial intermediate support layer 40. That is, the overall material of the intermediate support layer 103 on the first region 1 is the same as that of the first sub-layer 111. In this way, the etching selectivity ratio of the second sub-layer 112 to the intermediate support layer 103 on the first region 1 is greater than 1, so that the etching of the intermediate support layer on the second region 2 is easier than the etching of the intermediate support layer 103 on the first region 1, the etching time of the intermediate support layer on the second region 2 is reduced, and the process damage to the exposed lower electrode 121 caused by overlong etching is avoided. Specifically, the materials of the first material layer 43 and the initial intermediate support layer 40 may be silicon nitride or silicon carbonitride.

In some embodiments, the material of the first material layer 43 may also be different from the material of the initial intermediate support layer 40. For example, the initial intermediate support layer 40 may be made of a harder material than the first material layer 43, so as to ensure a better support performance of the intermediate support layer 103 on the first area 1. Specifically, the material of the first material layer 43 may be silicon nitride, and the material of the initial intermediate support layer 40 may be silicon carbonitride.

In some embodiments, the material of the second sub-layer 112 may be the same as the material of the first sacrificial layer 102. In this way, the second sub-layer 112 and the first sacrificial layer 102 can be removed in the same step, and the second sub-layer 112 and the first sacrificial layer 102 are not required to be removed by using different etching processes and etching process parameters, thereby saving the process flow.

In some embodiments, the material of the second sub-layer 112 may also be different from the material of the first sacrificial layer 102.

Fig. 12 is a schematic cross-sectional structure diagram corresponding to a step of forming a fifth sub-layer and a second material layer in a method for manufacturing a capacitor according to another embodiment of the disclosure; fig. 13 is a schematic cross-sectional structure corresponding to a step of forming a second mask layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 14 is a schematic cross-sectional structure corresponding to a step of forming a second through hole in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 15 is a schematic cross-sectional structure corresponding to a step of forming an initial second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 16 is a schematic cross-sectional structure corresponding to a step of forming a second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 17 is a schematic cross-sectional structure corresponding to a step of forming a third material layer in a method for manufacturing a capacitor according to another embodiment of the disclosure.

Referring to fig. 12 to 17, in some embodiments, the intermediate support layer 103 on the first region 1 includes a stacked third sub-layer and a fourth sub-layer, the material of the first sub-layer is the same as that of the fourth sub-layer, and the etching selectivity ratio of the fourth sub-layer to the third sub-layer is greater than 1.

That is, the intermediate support layer 103 on the first region 1 may have a laminated structure. The third sub-layer is more difficult to etch than the fourth sub-layer, and the material of the fourth sub-layer is the same as that of the first sub-layer, so the third sub-layer is also more difficult to etch than the first sub-layer. Also, the first sub-layer is more difficult to etch than the second sub-layer 112, making the third sub-layer more difficult to etch than the second sub-layer 112. In other words, the hardness of the third sub-layer may be greater than the hardness of the fourth sub-layer and the first sub-layer, so that the supporting ability of the intermediate supporting layer 103 on the first area 1 is further enhanced, which is advantageous for enhancing the supporting effect of the intermediate supporting layer 103 on the first area 1 on the capacitor.

In some embodiments, the intermediate support layer further includes a fifth sub-layer continuously disposed on the first region 1 and the second region 2, the etching selectivity of the second sub-layer 112 to the fifth sub-layer is greater than 1, the first sub-layer, the second sub-layer 112, the third sub-layer, and the fourth sub-layer are disposed on top of the fifth sub-layer, and the fifth sub-layer is in contact with the first sacrificial layer 102.

That is, the intermediate support layer has a three-layer structure, wherein the intermediate support layer located on the second region 2 includes a fifth sub-layer, a second sub-layer 112, and a first sub-layer. The intermediate support layer 103 located on the first region 1 includes a fifth sub-layer, a third sub-layer, and a fourth sub-layer stacked in this order in a direction away from the substrate 100.

It is not difficult to find that, in the intermediate support layer, only the third sub-layer in the intermediate support layer 103 on the first area 1 is different from the second sub-layer 112 in the intermediate support layer on the second area 2, and the second sub-layer 112 is easier to etch than the third sub-layer, so that the whole intermediate support layer on the second area 2 is easier to etch than the intermediate support layer 103 on the first area 1, and further the process duration of removing the intermediate support layer on the second area 2 is shortened.

The etching selectivity ratio of the second sub-layer 112 to the fifth sub-layer is greater than 1, that is, compared with the second sub-layer 112, the etching rate of the fifth sub-layer is smaller, that is, the etching is more difficult, so that the supporting force of the middle supporting layer of the second region 2 can be further improved while the middle supporting layer of the second region 2 is ensured to be etched more easily, so that the supporting force of the middle supporting layer in the process of etching the top supporting layer 105, the second sacrificial layer 104 and the middle supporting layer is improved, and the problem that the capacitor hole 10 collapses in the etching process is avoided.

In some embodiments, the thickness of the second sub-layer 112 is greater than the thickness of the first sub-layer, and greater than the thickness of the fifth sub-layer. In this way, in the middle supporting layer on the second area 2, the volume ratio of the second sub-layer 112 is larger than that of the first sub-layer 111 and the fifth sub-layer, so that the whole middle supporting layer on the second area 2 is easy to etch and remove.

In some embodiments, the thickness of the fifth sub-layer may be the same as the thickness of the first sub-layer.

In some embodiments, the material of the fifth sub-layer may be the same as the material of the first sub-layer, for example, may be silicon nitride. The material of the third sub-layer may be silicon carbonitride. The material of the second sub-layer 112 may be silicon oxide.

In some embodiments, a method of forming an intermediate support layer includes the steps of:

referring to fig. 12, a fifth sub-layer 113 and a second material layer 62 stacked in sequence are formed on the top surface of the first sacrificial layer 102, specifically, the fifth sub-layer 113 and the second material layer 62 stacked in sequence are formed on the top surface of the first sacrificial layer 102 on the first region 1 and the second region 2. In some embodiments, the fifth sub-layer 113 and the second material layer 62 may be sequentially formed using a deposition process, for example, a deposition process.

Referring to fig. 13 to 14, the second material layer 62 on the second region 2 is etched to form a plurality of spaced second through holes 44, the second through holes 44 expose a portion of the top surface of the fifth sub-layer 113, and the second material layer 62 (refer to fig. 13) on the first region 1 (refer to fig. 1) constitutes a third sub-layer 131 (refer to fig. 14). The second through holes 44 are in one-to-one correspondence with the second areas 2 (refer to fig. 1), and each second through hole 44 is opposite to one second area 2. That is, the second material layer 62 on the second region 2 is removed, and the remaining second material layer 62 constitutes the third sub-layer 131.

In some embodiments, the method of forming the second via 44 may include the following steps.

Referring to fig. 13, a second mask layer 70 is first formed on the top surface of the second material layer 62, and the material of the second mask layer 70 may be photoresist. Then, the process is carried out. A plurality of second mask openings 71 are formed in the second mask layer 70, the second mask openings 71 being opposite to the second regions 2. Specifically, the second mask opening 71 may be formed using a photolithography process.

Referring to fig. 14, the second material layer 62 (refer to fig. 13) is etched along the second mask opening 71 to form the second via 44 in the second material layer 62.

Referring to fig. 15 to 16, a second sub-layer 112 is formed to fill the second via 44. The second sub-layer 112 is in contact with the top surface of the fifth sub-layer 113 exposed by the second via 44.

In some embodiments, the method of forming the second sub-layer 112 may include the steps of:

referring to fig. 15, an initial second sub-layer 42 is formed in the second via 44 using a deposition process, the initial second sub-layer 42 being formed further above the top opening of the second via 44, the initial second sub-layer 42 being located above the top opening of the second via 44 on top of the third sub-layer 131.

Referring to fig. 16, a planarization process is performed on the initial second sub-layer 42, removing the initial second sub-layer 42 higher than the top of the opening of the second via hole 44 and the initial second sub-layer 42 located on the top surface of the third sub-layer 131, and the remaining initial second sub-layers form the second sub-layer 112. Specifically, the planarization process may include a chemical mechanical polishing process.

Referring to fig. 17, a third material layer 45 is formed on the top surface of the second sub-layer 112 and the top surface of the third sub-layer 131, the third material layer 45 on the top surface of the second sub-layer 112 serves as a first sub-layer, and the third material layer 45 on the top surface of the third sub-layer 131 serves as a fourth sub-layer.

It is not difficult to find that, in the intermediate support layer formed by the above method, the overall thickness of the first sub-layer, the second sub-layer 112, and the fifth sub-layer 113 is the same as that of the intermediate support layer on the first region 1.

Fig. 18 is a schematic cross-sectional structure corresponding to a step of forming a second through hole in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 19 is a schematic cross-sectional structure corresponding to a step of forming a second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 20 is a schematic cross-sectional structure corresponding to a step of forming a third material layer in a method for manufacturing a capacitor according to an embodiment of the disclosure.

In other embodiments, in the step of forming the second via hole 44, the second material layer 62 (refer to fig. 13) and the fifth sub-layer 113 may also be removed along the second mask opening 71, so as to expose the top surface of the first sacrificial layer 102, as shown in fig. 18.

Referring to fig. 19, the second via 44 is then filled with a second sub-layer 112, the second sub-layer 112 being in contact with the top surface of the first sacrificial layer 102.

Referring to fig. 20, finally, a third material layer 45 is formed on the top surface of the second sub-layer 112 and the top surface of the third sub-layer 131. The third material layer 45 on top of the second sub-layer 112 serves as a first sub-layer and the third material layer 45 on top of the third sub-layer 131 serves as a fourth sub-layer. That is, the intermediate support layer on the second region 2 may also include only the second sub-layer 112 and the first sub-layer, and the intermediate support layer 103 on the first region 1 may include the fifth sub-layer 113, the third sub-layer 131, and the fourth sub-layer.

Referring to fig. 3, after forming the intermediate support layer, a second sacrificial layer 104 and a top support layer 105 are sequentially formed on the top surface of the intermediate support layer. In some embodiments, the material of second sacrificial layer 104 may be any of silicon oxide or borophosphosilicate glass, and the material of top support layer 105 may be any of silicon nitride or silicon carbonitride.

Fig. 21 is a schematic cross-sectional structure corresponding to a step of forming a capacitor hole in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 21, after the top support layer 105 is formed, the capacitor hole 10 is formed. Each capacitor hole 10 extends through a portion of the top support layer 105, a portion of the second sacrificial layer 104, a portion of the intermediate support layer 103 over the first region 1, a portion of the first sacrificial layer 102, and a portion of the bottom support layer 101.

In some embodiments, the method of forming the capacitive aperture 10 may include the steps of:

first, a third mask layer is formed on the top surface of the top support layer 105, and a patterning process is performed on the third mask layer to form a plurality of third mask openings. In some embodiments, a photolithography process may be used to form a third mask opening that defines the opening shape of the capacitor hole 10.

Next, the top support layer 105, the second sacrificial layer 104, the middle support layer, the second sacrificial layer 104 and the bottom support layer 101 are etched in sequence along the third mask opening, so as to form a capacitor hole 10, and the bottom of the capacitor hole 10 exposes the top surface of the capacitor contact structure 20.

In some embodiments, the orthographic projection of the third mask opening on the top surface of the substrate 100 is located on the first region 1 and intersects a portion of the second region 2. Specifically, one second region 2 may intersect the orthographic projections of the adjacent three third mask openings on the top surface of the substrate 100. Thus, in the step of etching the intermediate support layer along the third mask opening, not only part of the first region 1 but also part of the second region 2 is etched.

Referring specifically to fig. 22, fig. 22 is a top view of a top surface of a substrate in a method for manufacturing a capacitor according to an embodiment of the present disclosure, and an orthographic projection of a capacitor hole 10 on the top surface of the substrate is denoted by 10a. On the top surface of the substrate, the orthographic projections 10a of the adjacent 3 capacitive holes on the top surface of the substrate are all partially intersected by a second area 2.

With continued reference to fig. 21, after the capacitor hole 10 is formed, a lower electrode 121 is further formed to cover the sidewall and bottom of the capacitor hole 10, and the lower electrode 121 is electrically contacted with the capacitor contact structure 20. In some embodiments, the lower electrode 121 may be formed using a deposition process, and the material of the lower electrode 121 may include titanium nitride.

FIG. 23 is a schematic cross-sectional view of a capacitor according to an embodiment of the present disclosure; fig. 24 is a schematic cross-sectional structure corresponding to a step of forming a fifth mask opening in a method for manufacturing a capacitor according to an embodiment of the disclosure; FIG. 25 is another top view of a top surface of a substrate in a method of fabricating a capacitor according to one embodiment of the present disclosure; fig. 26 is a schematic cross-sectional structure corresponding to a step of forming an opening in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 23 to 26, after forming the lower electrodes 121, openings 46 penetrating the top support layer 105 are formed in the top support layer 105 on the plurality of second regions 2, respectively, and each opening 46 exposes at least three adjacent lower electrodes 121.

In some embodiments, each opening 46 may expose the outer sidewalls of adjacent three lower electrodes 121. In some embodiments, each opening 46 may also expose the inner sidewalls of the adjacent three lower electrodes 121.

Specifically, the method of forming the opening 46 includes the steps of:

referring to fig. 23, a hard mask layer and a photoresist layer 33 are formed on the surface of the top support layer 105 and on top of the capacitor holes 10. The hard mask layer includes a carbon layer 31 and a silicon oxynitride layer 32 stacked in a direction away from the substrate 100. The photoresist layer 33 has a fourth mask opening for defining the shape of the opening 46.

Referring to fig. 24, the hard mask layer is etched along the fourth mask opening to form a fifth mask opening 34 in the hard mask layer, the fifth mask opening 34 exposing a portion of the top support layer 105, the shape of the fifth mask opening 34 being the same as the shape of the opening 46.

Referring to fig. 26, top support layer 105 is etched along fifth mask opening 34 (referring to fig. 24) to form opening 46.

Referring to fig. 25, fifth mask opening 34 is marked 34a in orthographic projection on the top surface of the substrate. In some embodiments, the front projection 34a of the fifth mask opening on the top surface of the substrate coincides with the second region 2, and the front projection 34a of the fifth mask opening on the top surface of the substrate may coincide with the front projection 10a of the adjacent three capacitor holes on the top surface of the substrate, so that in the subsequent step of etching the top support layer 105 along the fifth mask opening 34, a portion of the bottom electrode 121 is also etched, exposing the inner sidewall of the bottom electrode 121.

In some embodiments, the orthographic projection of the fifth mask opening 34 on the top surface of the substrate 100 coincides with the second region 2 and may be tangential to the orthographic projection of the adjacent capacitor hole 10 on the top surface of the substrate 100, so that, in the subsequent step of etching the top support layer 105 along the fifth mask opening 34, the top support layer 105 located on the outer side wall of the lower electrode 121 is etched away, exposing a portion of the outer side wall of the lower electrode 121.

Fig. 27 is a schematic cross-sectional structure diagram corresponding to a step of removing the second sacrificial layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 29 is a schematic cross-sectional structure corresponding to a step of removing the second sacrificial layer in another method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 32 is a schematic cross-sectional structure corresponding to a step of removing the second sacrificial layer in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 27, 29 and 32, second sacrificial layer 104 is etched along opening 46 to remove all of second sacrificial layer 104, exposing a portion of the outer sidewall of lower electrode 121. In some embodiments, second sacrificial layer 104 exposed by opening 46 may be wet etched using a wet etching process, gradually etching away all of second sacrificial layer 104.

Fig. 28 is a schematic cross-sectional structure diagram corresponding to a step of removing a first sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 30 is a schematic cross-sectional structure diagram corresponding to a step of removing a first sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 31 is a schematic cross-sectional structure diagram corresponding to a step of removing a second sub-layer in another method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 33 is a schematic cross-sectional structure diagram corresponding to a step of removing a first sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 34 is a schematic cross-sectional structure diagram corresponding to a step of removing the second sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure; fig. 35 is a schematic cross-sectional structure corresponding to a step of removing a fifth sub-layer in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 28, 30, 31, 33, 34 and 35, the intermediate support layer on the second region 2 is etched along the opening 46 (refer to fig. 26). In some embodiments, a dry etching process may be used to etch the intermediate support layer opposite to the opening 46, so that etching the intermediate support layer 103 on the first region 1 may be avoided, so that the intermediate support layer 103 on the first region 1 is preserved and is ultimately used to support the capacitor.

Specifically, in some embodiments, second sub-layer 112 is located on top of first sub-layer 111, in contact with second sacrificial layer 104, and the material of second sub-layer 112 is the same as the material of second sacrificial layer 104.

Then referring to fig. 26-27, second sub-layer 112 may be removed simultaneously in the step of removing second sacrificial layer 104.

Referring to fig. 27 to 28, in the step of removing the intermediate support layer on the second region 2, only the first sub-layer 111 is removed, and the thickness of the first sub-layer 111 is smaller than that of the intermediate support layer 103 on the first region 1, so that the etching time is shorter, and the process damage to the exposed lower electrode 121 caused by the excessive etching time is avoided.

In some embodiments, the first sub-layer 111 is formed on the top surface of the second sub-layer 112, the second sub-layer 112 contacts the first sacrificial layer 102, and the intermediate support layer on the first region 1 includes the stacked third sub-layer 131 and fourth sub-layer 132, and the method for removing the intermediate support layer may include the following steps.

Referring to fig. 29 and 30, first, the first sub-layer 111 is etched away.

Referring to fig. 31, the second sub-layer 112 is removed by etching, and compared with the case where the intermediate support layer on the second region 2 is formed by the first sub-layer 111, the etching selectivity of the second sub-layer 112 to the first sub-layer 111 is greater than 1, i.e. the second sub-layer 112 is easier to etch, so that the time taken for removing the intermediate support layer on the second region 2 is shorter, and further, the process damage to the exposed lower electrode 121 caused by the overlong etching time is avoided, which is beneficial to ensuring the better electrical performance of the lower electrode 121, and further ensuring the better electrical performance of the capacitor.

Referring to fig. 32, in some embodiments, the intermediate support layer on the first region 1 includes a stacked third sub-layer 131 and fourth sub-layer 132, the material of the first sub-layer 111 is the same as the material of the fourth sub-layer 132, and the intermediate support layer further includes a fifth sub-layer 113 continuously located on the first region 1 and the second region 2. The step of removing the intermediate support layer is as follows:

referring to fig. 32 to 33, first, the first sub-layer 111 is etched away.

Referring to fig. 34, the second sub-layer 112 is then etched away. In the middle supporting layer, only the third sub-layer 131 in the middle supporting layer on the first area 1 is different from the second sub-layer 112 in the middle supporting layer on the second area 2, and the second sub-layer 112 is easier to etch than the third sub-layer 131, so that the whole middle supporting layer on the second area 2 is easier to etch than the middle supporting layer on the first area 1, and the process time for removing the middle supporting layer on the second area 2 is shortened.

Referring to fig. 35, the fifth sub-layer 113 on the second region is finally removed. The etching selection ratio of the second sub-layer 112 to the fifth sub-layer 113 is greater than 1, that is, compared with the second sub-layer 112, the fifth sub-layer 113 is more difficult to etch, so that the supporting force of the middle supporting layer of the second region 2 can be further improved while the middle supporting layer of the second region 2 is ensured to be easier to etch, so that the supporting force of the middle supporting layer in the process of etching the top supporting layer 105, the second sacrificial layer 104 and the middle supporting layer is improved, and the problem that the capacitor hole 10 collapses in the etching process is avoided.

Fig. 36 is a schematic cross-sectional structure diagram corresponding to a step of removing the first sacrificial layer in a method for manufacturing a capacitor according to an embodiment of the disclosure.

Referring to fig. 36, after the intermediate support layer on the second region 2 is removed, the first sacrificial layer 102 is removed along the opening 46 (refer to fig. 26). In some embodiments, a wet etching process may be used to perform a wet etching process on the first sacrificial layer 102 exposed by the opening 46, and gradually etch away all of the first sacrificial layer 102, exposing the outer sidewall of the lower electrode 121.

Referring to fig. 37, a dielectric layer 123 is formed on the surface of a lower electrode 121, and an upper electrode 122 is formed on the dielectric layer 123, the lower electrode 121, the dielectric layer 123, and the upper electrode 122 constitute a capacitor.

In some embodiments, the dielectric layer 123 and the upper electrode 122 may be formed using a deposition process. In some embodiments, the material of dielectric layer 123 may be a high-k dielectric material. In some embodiments, the material of the upper electrode 122 may be a conductive material, for example, may be titanium nitride.

In the method for manufacturing a capacitor provided in the foregoing embodiment, the intermediate support layer on the second area 2 includes the stacked first sub-layer 111 and second sub-layer 112, and the etching selectivity of the second sub-layer 112 to the first sub-layer 111 is greater than 1. Compared with the first sub-layer 111, the second sub-layer 112 is easier to etch, so that the overall etching of the intermediate support layer on the second region 2 is easier, and the problem of process damage to the exposed sidewall of the lower electrode 121 caused by excessive etching time of the intermediate support layer on the second region 2 by the etching process is avoided. The first sub-layer 111 is more difficult to etch than the second sub-layer 112, and the material of the first sub-layer 111 is the same as the material of the intermediate support layer 103 on the first region 1, so that the first sub-layer 111 has better support capability. The method has the advantages that the supporting force is better, the etching rate is faster, the exposed side wall of the first electrode layer is not easy to damage, and finally the performance of the formed capacitor is improved.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A method of manufacturing a capacitor, comprising:

providing a substrate comprising a first region and a plurality of second regions, the first region being located between adjacent second regions;

sequentially forming a stacked bottom supporting layer, a first sacrificial layer, an intermediate supporting layer, a second sacrificial layer and a top supporting layer on the substrate, wherein the intermediate supporting layer on the second area comprises a stacked first sub-layer and a second sub-layer, the material of the first sub-layer is the same as that of the intermediate supporting layer on the first area, the thickness of the first sub-layer is smaller than that of the intermediate supporting layer on the first area, and the etching selection ratio of the second sub-layer to the first sub-layer is larger than 1;

forming a plurality of capacitor holes through the bottom support layer, the first sacrificial layer, the intermediate support layer, the second sacrificial layer, and the top support layer;

Forming a lower electrode in each of the plurality of capacitor holes;

forming openings penetrating through the top support layer in the top support layer on the second areas respectively, wherein each opening at least exposes three adjacent lower electrodes;

removing the second sacrificial layer, the middle supporting layer on the second area and the first sacrificial layer along the opening, and supporting the lower electrode by the rest of the bottom supporting layer, the middle supporting layer and the top supporting layer;

forming a dielectric layer on the surface of the lower electrode; the method comprises the steps of,

an upper electrode is formed on the dielectric layer.

2. The method of claim 1, wherein the first sub-layer is formed on top of the second sub-layer, and the second sub-layer is in contact with the first sacrificial layer.

3. The method of manufacturing a capacitor according to claim 2, wherein the method of forming the intermediate support layer comprises:

forming an initial intermediate support layer over the first region and the second region;

etching the initial intermediate support layer on the second region to form a plurality of spaced first through holes exposing a portion of the top surface of the first sacrificial layer;

Forming a second sub-layer filling the first through hole;

and forming a first material layer on the top surface of the second sub-layer and the top surface of the rest initial intermediate support layer, wherein the first material layer positioned on the top surface of the second sub-layer is used as the first sub-layer, and the rest first material layer and the rest initial intermediate support layer form the intermediate support layer on the first area.

4. A method of manufacturing a capacitor according to claim 3, wherein the material of the second sub-layer is the same as the material of the first sacrificial layer.

5. The method of claim 1, wherein the second sub-layer is located on the top surface of the first sub-layer, contacts the second sacrificial layer, and the material of the second sub-layer is the same as the material of the second sacrificial layer.

6. The method of manufacturing a capacitor according to claim 5, wherein the method of forming the intermediate support layer comprises:

etching the initial intermediate support layer on the second region to form a plurality of first through holes at intervals, wherein part of the top surface of the first sacrificial layer is exposed out of the bottom of each first through hole;

Forming a first sub-layer filled in part of the first through hole, wherein the first sub-layer is in contact with the first sacrificial layer;

and forming the second sub-layer filled with the rest of the first through holes.

7. The method for manufacturing a capacitor according to any one of claims 1 to 6, wherein the intermediate support layer on the first region includes a third sub-layer and a fourth sub-layer stacked, the material of the first sub-layer is the same as the material of the fourth sub-layer, and the etching selectivity of the fourth sub-layer to the third sub-layer is greater than 1.

8. The method of claim 7, wherein the intermediate support layer further comprises a fifth sub-layer disposed continuously over the first region and the second region, wherein an etch selectivity of the second sub-layer to the fifth sub-layer is greater than 1, wherein the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer are disposed on top of the fifth sub-layer, and wherein the fifth sub-layer is in contact with the first sacrificial layer.

9. The method of manufacturing a capacitor according to claim 8, wherein the method of forming the intermediate support layer comprises:

forming a fifth sub-layer and a second material layer which are sequentially stacked on the first region and the second region;

Etching the second material layer on the second region to form a plurality of second through holes at intervals, wherein part of the top surface of the fifth sub-layer is exposed by the second through holes, and the second material layer on the first region forms the third sub-layer;

forming a second sub-layer filling the second through hole;

and forming a third material layer on the top surface of the second sub-layer and the top surface of the third sub-layer, wherein the third material layer on the top surface of the second sub-layer is used as the first sub-layer, and the third material layer on the top surface of the third sub-layer is used as the fourth sub-layer.

10. The method of manufacturing a capacitor of claim 8, wherein the second sub-layer has a thickness greater than the thickness of the first sub-layer and greater than the thickness of the fifth sub-layer.