CN113964034B - Silicon-based AlGaN/GaN HEMT based on GeSnSi epitaxial layer on back surface of substrate and preparation method - Google Patents

Silicon-based AlGaN/GaN HEMT based on GeSnSi epitaxial layer on back surface of substrate and preparation method Download PDF

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CN113964034B
CN113964034B CN202111006450.8A CN202111006450A CN113964034B CN 113964034 B CN113964034 B CN 113964034B CN 202111006450 A CN202111006450 A CN 202111006450A CN 113964034 B CN113964034 B CN 113964034B
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gesnsi
algan
epitaxial layer
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CN113964034A (en
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张雅超
马金榜
李一帆
姚一昕
张进成
马佩军
马晓华
郝跃
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Xidian University
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Abstract

The invention relates to a silicon-based AlGaN/GaNHEMT based on a GeSnSi epitaxial layer on the back of a substrate and a preparation method thereof, wherein the preparation method comprises the following steps: s1, growing at least one GeSnSi epitaxial layer on the back surface of a Si substrate; s2, sequentially growing an AlN nucleating layer, an AlGaN step-changing layer, a GaN buffer layer and an AlGaN barrier layer on the front surface of the Si substrate to form a silicon-based AlGaN/GaN HEMT device; s3, cooling the silicon-based AlGaN/GaN HEMT device. According to the preparation method, at least one GeSnSi epitaxial layer is arranged on the back surface of the Si substrate, the thermal expansion coefficient of GeSnSi is larger than that of Si, and certain compressive stress is introduced into the substrate due to the fact that the thermal expansion coefficient of GeSnSi is larger in the process of cooling the AlGaN/GaN HEMT device after growth, and a certain counteracting effect is achieved on tensile stress in the silicon-based AlGaN/GaNHEMT device, so that the purpose of reducing warping is achieved, and the yield of materials is improved.

Description

Silicon-based AlGaN/GaN HEMT based on GeSnSi epitaxial layer on back surface of substrate and preparation method
Technical Field
The invention belongs to the technical field of semiconductor materials, and particularly relates to a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back of a substrate and a preparation method thereof.
Background
GaN, which is a typical representation of the third generation of wide bandgap semiconductor materials, is widely used in radio frequency devices, light emitting diodes and power electronics due to its large bandgap (3.4 ev), large breakdown field strength, strong radiation resistance, etc. AlGaN/GaN high electron mobility transistors (High Electron Mobility Transistor, HEMT) are used as common GaN structures, are widely applied to a plurality of fields of emerging 5G communication, radar, space exploration and the like due to high two-dimensional electron gas mobility and two-dimensional electron gas density, and have high requirements on the radio frequency performance of AlGaN/GaN HEMT devices.
Conventional AlGaN/GaN HENT heteroepitaxial substrates are composed of SiC, sapphire and Si substrates. Although SiC performs best, its large-scale commercial application is limited because large-size substrates are expensive; sapphire substrates are also limited in application because of poor thermal conductivity. In contrast, si substrates are inexpensive and have higher thermal conductivity, and are compatible with Si conventional processes, receiving great attention. However, the silicon-based AlGaN/GaN HEMT can cause larger warpage due to very large thermal mismatch and lattice mismatch, and the yield of materials is affected.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate, which comprises the following steps:
s1, growing at least one GeSnSi epitaxial layer on the back surface of a Si substrate;
s2, sequentially growing an AlN nucleating layer, an AlGaN step-changing layer, a GaN buffer layer and an AlGaN barrier layer on the front surface of the Si substrate to form a silicon-based AlGaN/GaN HEMT device;
s3, cooling the silicon-based AlGaN/GaN HEMT device.
In one embodiment of the present invention, step S1 includes the steps of:
s11, growing a first GeSnSi epitaxial layer on the back surface of the Si substrate;
and S12, growing a second GeSnSi epitaxial layer on the back surface of the first GeSnSi epitaxial layer.
In one embodiment of the present invention, the mass fraction of the Ge component in the first GeSnSi epitaxial layer is less than the mass fraction of the Ge component in the second GeSnSi epitaxial layer, and the mass fraction of the Sn component in the first GeSnSi epitaxial layer is less than the mass fraction of the Sn component in the second GeSnSi epitaxial layer.
In one embodiment of the present invention, step S11 includes:
firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the Si substrate, wherein the mass fraction of Si component is 0.98, the mass fraction of Ge component is 0.015, and the mass fraction of Sn component is 0.005, thereby forming the first GeSnSi epitaxial layer.
In one embodiment of the present invention, step S12 includes:
firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the first GeSnSi epitaxial layer, wherein the mass fraction of Si component is 0.96, the mass fraction of Ge component is 0.03 and the mass fraction of Sn component is 0.01, thereby forming the second GeSnSi epitaxial layer.
In one embodiment of the present invention, step S2 includes:
and sequentially growing an AlN nucleating layer, an AlGaN step-changing layer, a GaN buffer layer and an AlGaN barrier layer on the front surface of the Si substrate by utilizing a metal organic compound chemical vapor deposition method to form the silicon-based AlGaN/GaN HEMT device.
In one embodiment of the present invention, step S3 includes:
and cooling the silicon-based AlGaN/GaN HEMT device to room temperature in metal organic compound chemical vapor deposition equipment.
In one embodiment of the present invention, the steps S1 and S2 further include the steps of:
and preparing a pre-paved aluminum layer on the front surface of the Si substrate.
In one embodiment of the present invention, the preparation conditions of the pre-laid aluminum layer are: the temperature of the reaction chamber is 1080-1090 ℃, the flow rate of trimethylaluminum is 10-30sccm, and the thickness of the prepared pre-paved aluminum is less than 10nm.
Another embodiment of the present invention provides a silicon-based AlGaN/GaN HEMT based on a substrate back side GeSnSi epitaxial layer, which is manufactured by the manufacturing method described in the above embodiment.
Compared with the prior art, the invention has the beneficial effects that:
according to the preparation method of the silicon-based AlGaN/GaN HEMT, at least one GeSnSi epitaxial layer is arranged on the back surface of the Si substrate, the thermal expansion coefficient of GeSnSi is larger than that of Si, and certain compressive stress is introduced into the substrate due to the larger thermal expansion coefficient of GeSnSi in the process of cooling the AlGaN/GaN HEMT device after growth, so that a certain counteracting effect is achieved on the tensile stress in the silicon-based AlGaN/GaN HEMT device, and the purpose of reducing warping is achieved, and the yield of materials is improved.
Drawings
Fig. 1 is a schematic flow chart of a preparation method of a silicon-based AlGaN/GaN HEMT based on a substrate back surface GeSnSi epitaxial layer according to an embodiment of the present invention;
fig. 2 a-fig. 2d are schematic process diagrams of a preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1 and fig. 2a to fig. 2d, fig. 1 is a schematic flow chart of a method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate back side GeSnSi epitaxial layer according to an embodiment of the present invention, and fig. 2a to fig. 2d are schematic flow charts of a method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate back side GeSnSi epitaxial layer according to an embodiment of the present invention.
The preparation method comprises the following steps:
s1, growing at least one GeSnSi epitaxial layer on the back surface of the Si substrate 1.
Specifically, the material of the Si substrate 1 includes P-type Si (111) with a thickness of 500-900 μm and a size of 2-6 inches, and the resistance is larger than 6000 Ω·cm, for example, the Si substrate 1 may be a P-type Si sheet with a thickness of 525 μm, a 4 inch, and a resistance larger than 6000 Ω·cm, as shown in fig. 2a. In the embodiment, the Si sheet with the crystal orientation of 111 is selected, so that the Ga surface can be grown on the substrate, and the quality of the subsequent growth material is ensured.
The Si substrate 1 is first subjected to cleaning and thermal cleaning.
The method for cleaning the Si substrate 1 comprises the following steps: soaking Si substrate in 20% HF acid solution for 60s, and then using H 2 O 2 Alcohol and acetone rinse, and finally rinse with flowing deionized water for 60s.
The method of thermally cleaning the Si substrate 1 is: placing the cleaned substrate into a low-pressure MOCVD reaction chamber, introducing hydrogen, raising the temperature to 1000 ℃, controlling the pressure of the reaction chamber to 40Torr, and carrying out heat treatment on the substrate for 3min under the hydrogen atmosphere.
Next, at least one GeSnSi epitaxial layer is grown on the back side of the Si substrate 1.
Specifically, the number of GeSnSi epitaxial layers may be 1 layer or may be multiple layers, which is not limited in this embodiment, and the purpose of reducing warpage of the material can be achieved as long as the GeSnSi epitaxial layers are grown on the back surface of the Si substrate 1.
When the number of the GeSnSi epitaxial layers is multiple, as the number of the epitaxial layers is increased, the mass fraction of Ge components and the mass fraction of Sn components in the GeSnSi epitaxial layers are increased, the mass fraction of Si components is decreased, and a gradual epitaxial layer is formed, so that the crystal quality of the GeSnSi layers can be improved by gradually reducing lattice mismatch between the Si substrate and the GeSnSi layers on the back side while larger compressive stress is kept by utilizing the multiple layers of the GeSnSi layers.
In a specific embodiment, the number of GeSnSi epitaxial layers is 2, that is, the GeSnSi epitaxial layers include a first GeSnSi epitaxial layer 71 and a second GeSnSi epitaxial layer 72, and step S1 includes:
s11, a first GeSnSi epitaxial layer 71 is grown on the back surface of the Si substrate 1, see fig. 2b.
Firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing a GeSnSi alloy with the thickness of 1.0-1.4 mu m on the back surface of a Si substrate 1, wherein the mass fraction of Si component is 0.98, the mass fraction of Ge component is 0.015, and the mass fraction of Sn component is 0.005, thereby forming a first GeSnSi epitaxial layer 71.
In one embodiment, after the thermal cleaning stage, the Si substrate 1 is taken out and put into an ultra-high vacuum vapor deposition (Ultra High Vacuum Chemical Vapor Deposition, abbreviated as UHVCVD) reaction chamber, a Si source and a Ge source are first introduced at a reaction chamber temperature of 700 ℃, then a Sn source is introduced at a reaction chamber temperature of 300 ℃, and GeSnSi with a thickness of 1.2 μm is grown on the back surface of the Si substrate 1, wherein the mass fraction of the Si component is 0.98, the mass fraction of the Ge component is 0.015, and the mass fraction of the Sn component is 0.005, to form the first GeSnSi epitaxial layer 71.
S12, a second GeSnSi epitaxial layer 72 is grown on the back of the first GeSnSi epitaxial layer 71, see fig. 2c.
By vapor deposition, firstly introducing Si source and Ge source under the condition that the temperature of the reaction chamber is 690-710 ℃, then introducing Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi alloy with the thickness of 1.0-1.4 μm on the back surface of the first GeSnSi epitaxial layer 71, wherein the mass fraction of Si component is 0.96, the mass fraction of Ge component is 0.03 and the mass fraction of Sn component is 0.01, thereby forming the second GeSnSi epitaxial layer 72.
In one embodiment, the second GeSnSi epitaxial layer 72 is formed by introducing a Si source and a Ge source at a CVD reactor temperature of 700 c, then introducing a Sn source at a reactor temperature of 300 c, and growing GeSnSi having a thickness of 1.2 μm on the back side of the first GeSnSi epitaxial layer 71, wherein the Si composition is 0.96 mass%, the Ge composition is 0.03 mass%, and the Sn composition is 0.01 mass%.
Thereafter, the sample is subjected to an annealing treatment.
In this embodiment, the first GeSnSi epitaxial layer 71 has a Si composition of 0.98 mass fraction, a ge composition of 0.015 mass fraction, a sn composition of 0.005 mass fraction, the second GeSnSi epitaxial layer 72 has a Si composition of 0.96 mass fraction, a ge composition of 0.03 mass fraction, and a sn composition of 0.01 mass fraction; that is, the mass fraction of Ge component in the first GeSnSi epitaxial layer 71 is smaller than the mass fraction of Ge component in the second GeSnSi epitaxial layer 72, and the mass fraction of Sn component in the first GeSnSi epitaxial layer 71 is smaller than the mass fraction of Sn component in the second GeSnSi epitaxial layer 72, so that the mass fraction of Si component in the first GeSnSi epitaxial layer 71 is greater than the mass fraction of Si component in the second GeSnSi epitaxial layer 72.
The GeSnSi with larger mass fraction of the Si component is firstly extended to serve as a transition layer on the back surface of the Si substrate, and then the GeSnSi with smaller mass fraction of the Si component is extended, so that lattice mismatch between the Si substrate and the GeSnSi epitaxial layer which grows subsequently can be reduced, and preparation is made for extending the high-quality GeSnSi layer.
S2, an AlN nucleation layer 3, an AlGaN step-changing layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 are sequentially grown on the front surface of the Si substrate 1 to form a silicon-based AlGaN/GaN HEMT device, see FIG. 2d.
Specifically, an AlN nucleation layer 3, an AlGaN step change layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 are sequentially grown on the front surface of a Si substrate 1 by using a metal organic compound chemical vapor deposition method, so that a silicon-based AlGaN/GaN HEMT device is formed.
The step S2 specifically comprises the steps of:
s21, epitaxially growing a first AlN nucleation layer 31 on the Si substrate 1.
Specifically, by using the MOCVD method, trimethylaluminum (TMAL) and NH are simultaneously opened 3 The gas path is used for adjusting the TMAL flow to 240-260sccm and NH 3 The low-temperature AlN nucleating layer with the flow rate of 3800-4200sccm, the growth temperature of 895-905 ℃ and the growth time of 60min is grown to be 20-40nm thick, and the first AlN nucleating layer 31 is formed.
In one embodiment, the growth conditions of the first AlN nucleation layer 31 are: TMAL flow is 260sccm, NH 3 The flow is 4000sccm, the growth temperature is 900 ℃, and the growth time is 60minThe first AlN nucleation layer 31 was formed to have a thickness of 30nm.
S22, epitaxially growing a second AlN nucleation layer 32 on the first AlN nucleation layer 31.
Specifically, the temperature of the reaction chamber is raised to 1200-1220 ℃, the TMAL flow is adjusted to 190-200sccm, the ammonia flow is adjusted to 1350-1650sccm, and a high-temperature AlN nucleation layer with the thickness of 160-180nm is grown for 60min, so that the second AlN nucleation layer 32 is formed.
In one particular embodiment, the growth conditions for second AlN nucleation layer 32 are: TMAL flow is 190sccm, NH 3 The flow rate was 1400sccm, the growth temperature was 1210 ℃, the growth time was 60min, and the thickness of the second AlN nucleation layer 32 was 170nm.
S23, the first AlGaN layer 41 is prepared on the second AlN nucleation layer 32.
Specifically, the temperature of the reaction chamber is reduced to 1140-1160 ℃, TMAL, trimethylgallium, TMGa, NH are adjusted at this time 3 AlGaN with the thickness of 340-360nm is grown with the flow rate of 190-200sccm, 10sccm and 2650-3250sccm respectively, and the first AlGaN layer 41 with the Al component mass fraction of 30-40% is formed.
In one embodiment, the growth condition of first AlGaN layer 41 is a reaction chamber temperature of 1150℃and TMAl, TMGa, NH 3 The flow rates were 190sccm, 10sccm, and 2700sccm, respectively, and the thickness of the grown first AlGaN layer 41 was 350nm and the mass fraction of the Al component was 35%.
S24, a second AlGaN layer 42 is prepared on the first AlGaN layer 41.
Specifically, the temperature of the reaction chamber is kept between 1140 and 1160 ℃, and TMAl, TMGa, NH is adjusted 3 AlGaN with the flow rate of 160-170sccm, 20sccm, 2920sccm-3580sccm and the thickness of 390-410nm is grown to form the second AlGaN layer 42 with the Al component mass fraction of 70-80%.
In one embodiment, the growth conditions of the second AlGaN layer 42 are: the temperature of the reaction chamber is 1150 ℃ and TMAl, TMGa, NH 3 The flow rates were 162sccm, 20sccm, 3000sccm, respectively, and the thickness of the grown second AlGaN layer 42 was 400nm, and the mass fraction of the Al component was 75%.
Further, the first AlGaN layer 41 and the second AlGaN layer 42 together form the graded AlGaN buffer layer 4.
And S25, growing a GaN layer 5 on the AlGaN buffer layer 3.
Specifically, the temperature of the reaction chamber is kept unchanged, a TMAL source is closed, and TMGa and NH are adjusted 3 And (3) continuously epitaxially growing a GaN layer with the thickness of 900-1100nm to form the GaN buffer layer 5, wherein the flow rates are respectively 190-200sccm and 8800-10100 sccm.
In one specific embodiment, the growth conditions of GaN buffer layer 5 are: the temperature of the reaction chamber is 1150 ℃, the TMGa flow is 192sccm, and NH 3 The flow rate was 9000sccm, and the thickness of the GaN buffer layer 5 formed was 1 μm.
S26, preparing an AlGaN barrier layer 6 on the GaN buffer layer 5.
Specifically, the temperature of the reaction chamber was raised to 1190℃and the TMAL source was turned on, at which time TMAl, TMGa, NH was adjusted 3 And depositing an AlGaN layer with the flow rate of 70-90sccm, 35-50sccm and 10000-24000sccm respectively to form an AlGaN barrier layer 6.
In one embodiment, alGaN barrier layer 6 is grown under conditions such that the reaction chamber temperature is 1190 ℃, TMAL flow is 80sccm, TMGa flow is 43sccm, NH 3 The flux was 20000sccm, and the thickness of the AlGaN barrier layer 6 was 250nm.
S3, cooling the silicon-based AlGaN/GaN HEMT device.
Specifically, the AlGaN/GaN HEMT device can be cooled to room temperature in the reaction chamber of the AlGaN/GaN HEMT, and the silicon-based AlGaN/GaN HEMT device can be placed in a room temperature environment for cooling. In this embodiment, since the silicon-based AlGaN/GaN HEMT device is prepared by using the metal organic compound chemical vapor deposition apparatus, the HEMT device is continuously cooled in the MOCVD apparatus.
In the process of cooling the HEMT device, as the thermal expansion coefficient of GeSnSi is larger than that of Si, the GeSnSi can introduce certain compressive stress into the substrate, and a certain counteracting effect is achieved on the tensile stress in the silicon-based AlGaN/GaN HEMT device, so that the purpose of reducing warpage is achieved, and the yield of materials is improved.
Referring to fig. 2d, fig. 2d is a schematic structural diagram of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention. The silicon-based AlGaN/GaN HEMT device comprises at least one GeSnSi epitaxial layer, a Si substrate 1, an AlN nucleation layer 3, an AlGaN step-change layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 which are sequentially stacked. Specific parameters of each layer in the silicon-based AlGaN/GaN HEMT device are described above, and will not be described herein.
The silicon-based AlGaN/GaN HEMT device has lower warping degree and improves the yield of materials due to the fact that the GeSnSi layer with larger thermal expansion coefficient is arranged on the back surface of the Si substrate.
Example two
On the basis of the first embodiment, the present embodiment provides another preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate, where the preparation method includes the steps of:
s1, sequentially growing at least one GeSnSi epitaxial layer on the back surface of the Si substrate 1.
S2, preparing a pre-paved aluminum layer 2 on the front surface of the Si substrate 1.
Specifically, the temperature of the reaction chamber is increased to 1080-1090 ℃, a TMAL gas path is opened, the TMAL flow is adjusted to 10-30sccm, the preparation of the pre-paved aluminum layer 2 is carried out on the front surface of the Si substrate 1, and the thickness of the formed pre-paved aluminum layer 2 is smaller than 10nm.
In one embodiment, the preparation condition of the pre-laid aluminum layer 2 is that the reaction chamber temperature is 1085 ℃ and the TMAl flow is 20sccm.
S3, sequentially growing an AlN nucleation layer 3, an AlGaN step-changing layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 on the front surface of the pre-paved aluminum layer 2 to form the silicon-based AlGaN/GaN HEMT device
S4, cooling the silicon-based AlGaN/GaN HEMT device.
Referring to fig. 3 for the structure of the fabricated device, fig. 3 is a schematic structural diagram of another silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of the substrate according to the embodiment of the present invention. The silicon-based AlGaN/GaN HEMT comprises at least one GeSnSi epitaxial layer, a Si substrate 1, a pre-laid aluminum layer 2, an AlN nucleation layer 3, an AlGaN graded layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 which are sequentially stacked.
In the embodiment, the pre-paved aluminum is arranged between the Si substrate and the AlN nucleation layer, so that the growth effect of the nucleation layer can be improved, the crystal quality of GaN can be improved, and the performance of the device can be further improved.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (8)

1. A preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate is characterized by comprising the following steps:
s1, growing at least one GeSnSi epitaxial layer on the back surface of a Si substrate (1);
the step S1 comprises the following steps: step S11 and steps S12, S11, growing a first GeSnSi epitaxial layer (71) on the back surface of the Si substrate (1);
s12, growing a second GeSnSi epitaxial layer (72) on the back surface of the first GeSnSi epitaxial layer (71); the mass fraction of the Ge component in the first GeSnSi epitaxial layer (71) is smaller than the mass fraction of the Ge component in the second GeSnSi epitaxial layer (72), and the mass fraction of the Sn component in the first GeSnSi epitaxial layer (71) is smaller than the mass fraction of the Sn component in the second GeSnSi epitaxial layer (72);
s2, sequentially growing an AlN nucleation layer (3), an AlGaN step-changing layer (4), a GaN buffer layer (5) and an AlGaN barrier layer (6) on the front surface of the Si substrate (1) to form a silicon-based AlGaN/GaN HEMT device;
s3, cooling the silicon-based AlGaN/GaN HEMT device.
2. The method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate backside GeSnSi epitaxial layer according to claim 1, wherein step S11 comprises:
firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the Si substrate (1), wherein the mass fraction of Si component is 0.98, the mass fraction of Ge component is 0.015, and the mass fraction of Sn component is 0.005, so as to form the first GeSnSi epitaxial layer (71).
3. The method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate backside GeSnSi epitaxial layer according to claim 1, wherein step S12 comprises:
firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the first GeSnSi epitaxial layer (71), wherein the mass fraction of Si component is 0.96, the mass fraction of Ge component is 0.03 and the mass fraction of Sn component is 0.01, thereby forming the second GeSnSi epitaxial layer (72).
4. The method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate backside GeSnSi epitaxial layer according to claim 1, wherein step S2 comprises:
and sequentially growing an AlN nucleation layer (3), an AlGaN step change layer (4), a GaN buffer layer (5) and an AlGaN barrier layer (6) on the front surface of the Si substrate (1) by using a metal organic compound chemical vapor deposition method to form the silicon-based AlGaN/GaN HEMT device.
5. The method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate backside GeSnSi epitaxial layer according to claim 4, wherein step S3 comprises:
and cooling the silicon-based AlGaN/GaN HEMT device to room temperature in metal organic compound chemical vapor deposition equipment.
6. The method for preparing a silicon-based AlGaN/GaN HEMT based on a substrate back surface GeSnSi epitaxial layer according to claim 1, wherein the steps between S1 and S2 further comprise the steps of:
and preparing a pre-laid aluminum layer (2) on the front surface of the Si substrate (1).
7. The preparation method of the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back surface of the substrate according to claim 6, wherein the preparation conditions of the pre-paved aluminum layer (2) are as follows: the reaction chamber temperature is 1080-1090 ℃, the trimethylaluminum flow is 10-30sccm, and the thickness of the prepared pre-paved aluminum (2) is less than 10nm.
8. A silicon-based AlGaN/GaN HEMT based on a substrate backside GeSnSi epitaxial layer, characterized by being manufactured by the manufacturing method according to any one of the preceding claims 1 to 7.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101887848A (en) * 2009-05-13 2010-11-17 硅电子股份公司 Comprise silicon monocrystalline substrate with front side and dorsal part and the production method that is deposited on the wafer of the SiGe layer on the front side
KR20170133152A (en) * 2016-05-25 2017-12-05 전북대학교산학협력단 Template epi substrates and manufacturing method thereof
CN110767766A (en) * 2018-07-26 2020-02-07 上海新微技术研发中心有限公司 Strain balance GeSn infrared photoelectric detector and manufacturing method thereof
CN210120127U (en) * 2019-08-29 2020-02-28 厦门市三安集成电路有限公司 Composite silicon substrate
CN113192820A (en) * 2021-03-12 2021-07-30 南昌大学 Preparation method of silicon substrate aluminum nitride film

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008532294A (en) * 2005-03-11 2008-08-14 アリゾナ ボード オブ リージェンツ ア ボディー コーポレート アクティング オン ビハーフ オブ アリゾナ ステイト ユニバーシティ Novel GeSiSn-based compounds, templates, and semiconductor structures
WO2011071717A2 (en) * 2009-12-11 2011-06-16 National Semiconductor Corporation Backside stress compensation for gallium nitride or other nitride-based semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101887848A (en) * 2009-05-13 2010-11-17 硅电子股份公司 Comprise silicon monocrystalline substrate with front side and dorsal part and the production method that is deposited on the wafer of the SiGe layer on the front side
KR20170133152A (en) * 2016-05-25 2017-12-05 전북대학교산학협력단 Template epi substrates and manufacturing method thereof
CN110767766A (en) * 2018-07-26 2020-02-07 上海新微技术研发中心有限公司 Strain balance GeSn infrared photoelectric detector and manufacturing method thereof
CN210120127U (en) * 2019-08-29 2020-02-28 厦门市三安集成电路有限公司 Composite silicon substrate
CN113192820A (en) * 2021-03-12 2021-07-30 南昌大学 Preparation method of silicon substrate aluminum nitride film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
High performance Al0.10Ga0.90N channel HEMTs;Ming Xiao et al;《IEEE electron device letters》;20180831;第39卷(第8期);第1149-1151页 *

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