CN113964034A - Silicon-based AlGaN/GaN HEMT based on GeSnSi epitaxial layer on back surface of substrate and preparation method - Google Patents

Silicon-based AlGaN/GaN HEMT based on GeSnSi epitaxial layer on back surface of substrate and preparation method Download PDF

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CN113964034A
CN113964034A CN202111006450.8A CN202111006450A CN113964034A CN 113964034 A CN113964034 A CN 113964034A CN 202111006450 A CN202111006450 A CN 202111006450A CN 113964034 A CN113964034 A CN 113964034A
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gesnsi
algan
epitaxial layer
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silicon
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CN113964034B (en
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张雅超
马金榜
李一帆
姚一昕
张进成
马佩军
马晓华
郝跃
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Xidian University
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Abstract

The invention relates to a silicon-based AlGaN/GaNHEMT based on a GeSnSi epitaxial layer on the back of a substrate and a preparation method thereof, wherein the preparation method comprises the following steps: s1, growing at least one GeSnSi epitaxial layer on the back of the Si substrate; s2, growing an AlN nucleating layer, an AlGaN graded layer, a GaN buffer layer and an AlGaN barrier layer on the front surface of the Si substrate in sequence to form a silicon-based AlGaN/GaN HEMT device; and S3, cooling the silicon-based AlGaN/GaN HEMT device. According to the preparation method, at least one GeSnSi epitaxial layer is arranged on the back of a Si substrate, the GeSnSi epitaxial layer has a larger thermal expansion coefficient than Si, and when the AlGaN/GaN HEMT device is cooled, a certain compressive stress can be introduced into the substrate due to the larger thermal expansion coefficient of the GeSnSi, so that the tensile stress in the silicon-based AlGaN/GaNHEMT device can be offset to a certain extent, the purpose of reducing warpage is achieved, and the yield of the material is improved.

Description

Silicon-based AlGaN/GaN HEMT based on GeSnSi epitaxial layer on back surface of substrate and preparation method
Technical Field
The invention belongs to the technical field of semiconductor materials, and particularly relates to a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back of a substrate and a preparation method thereof.
Background
GaN, as a typical representative of third-generation wide bandgap semiconductor materials, has the advantages of large bandgap (3.4ev), large breakdown field strength, and strong radiation resistance, and is widely used in radio frequency devices, light emitting diodes, and power electronic devices. An AlGaN/GaN High Electron Mobility Transistor (HEMT) is a commonly used GaN structure, and is widely used in many fields such as emerging 5G communications, radar, space exploration and the like due to its High two-dimensional Electron gas Mobility and two-dimensional Electron gas density, but it also puts High demands on the radio frequency performance of AlGaN/GaN HEMT devices.
Conventional AlGaN/GaN HENT heteroepitaxial substrates are composed of SiC, sapphire, and Si substrates. Although SiC performs best, its large-scale commercial application is limited due to the relatively expensive large-size substrates; sapphire substrates, however, have limited applications due to poor thermal conductivity. In contrast, Si substrates are inexpensive and have a higher thermal conductivity, and are compatible with Si conventional processes, gaining wide attention. However, the silicon-based AlGaN/GaN HEMT causes large warpage due to very large thermal mismatch and lattice mismatch, which affects the yield of the material.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back of a substrate and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back of a substrate, which comprises the following steps:
s1, growing at least one GeSnSi epitaxial layer on the back of the Si substrate;
s2, growing an AlN nucleating layer, an AlGaN graded layer, a GaN buffer layer and an AlGaN barrier layer on the front surface of the Si substrate in sequence to form a silicon-based AlGaN/GaN HEMT device;
and S3, cooling the silicon-based AlGaN/GaN HEMT device.
In one embodiment of the present invention, step S1 includes the steps of:
s11, growing a first GeSnSi epitaxial layer on the back of the Si substrate;
and S12, growing a second GeSnSi epitaxial layer on the back of the first GeSnSi epitaxial layer.
In one embodiment of the present invention, the mass fraction of the Ge component in the first GeSnSi epitaxial layer is smaller than the mass fraction of the Ge component in the second GeSnSi epitaxial layer, and the mass fraction of the Sn component in the first GeSnSi epitaxial layer is smaller than the mass fraction of the Sn component in the second GeSnSi epitaxial layer.
In one embodiment of the present invention, step S11 includes:
by utilizing a vapor deposition method, firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the Si substrate, wherein the mass fraction of the Si component is 0.98, the mass fraction of the Ge component is 0.015, and the mass fraction of the Sn component is 0.005 to form the first GeSnSi epitaxial layer.
In one embodiment of the present invention, step S12 includes:
by utilizing a vapor deposition method, firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the first GeSnSi epitaxial layer, wherein the mass fraction of the Si component is 0.96, the mass fraction of the Ge component is 0.03, and the mass fraction of the Sn component is 0.01 to form the second GeSnSi epitaxial layer.
In one embodiment of the present invention, step S2 includes:
and sequentially growing an AlN nucleating layer, an AlGaN step-change layer, a GaN buffer layer and an AlGaN barrier layer on the front surface of the Si substrate by using a metal organic compound chemical vapor deposition method to form the silicon-based AlGaN/GaN HEMT device.
In one embodiment of the present invention, step S3 includes:
and cooling the silicon-based AlGaN/GaN HEMT device to room temperature in metal organic compound chemical vapor deposition equipment.
In an embodiment of the present invention, the step between S1 and S2 further includes the steps of:
and preparing a pre-paved aluminum layer on the front surface of the Si substrate.
In one embodiment of the present invention, the preparation conditions of the pre-laid aluminum layer are as follows: the temperature of the reaction chamber is 1080-.
Another embodiment of the invention provides a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate, which is prepared by the preparation method described in the above embodiment.
Compared with the prior art, the invention has the beneficial effects that:
according to the preparation method of the silicon-based AlGaN/GaN HEMT, at least one GeSnSi epitaxial layer is arranged on the back surface of the Si substrate, the GeSnSi has a larger thermal expansion coefficient than Si, and when the AlGaN/GaN HEMT device is grown and cooled, a certain compressive stress can be introduced into the substrate due to the larger thermal expansion coefficient of the GeSnSi, so that a certain counteracting effect is achieved on the tensile stress in the silicon-based AlGaN/GaN HEMT device, the purpose of reducing warpage is achieved, and the yield of the material is improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention;
fig. 2a to fig. 2d are schematic process diagrams of a method for manufacturing a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on a back surface of a substrate according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1 and fig. 2a to fig. 2d, fig. 1 is a schematic flow chart of a method for manufacturing a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on a back surface of a substrate according to an embodiment of the present invention, and fig. 2a to fig. 2d are schematic process diagrams of a method for manufacturing a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on a back surface of a substrate according to an embodiment of the present invention.
The preparation method comprises the following steps:
and S1, growing at least one GeSnSi epitaxial layer on the back surface of the Si substrate 1.
Specifically, the material of the Si substrate 1 includes P-type Si (111), the thickness is 500-900 μm, the size is 2-6 inches, and the resistance is greater than 6000 Ω · cm, for example, the Si substrate 1 may be a P-type Si sheet with a large resistance, the thickness is 525 μm, 4 inches, and the resistance is greater than 6000 Ω · cm, as shown in fig. 2 a. In the embodiment, the Si sheet with the crystal direction of 111 is selected, so that the Ga surface can grow on the substrate, and the quality of a subsequent growing material is ensured.
The Si substrate 1 is first subjected to cleaning and thermal cleaning.
The method for cleaning the Si substrate 1 includes: soaking the Si substrate in 20% HF acid solution for 60s, and then soaking in H2O2Alcohol and acetone washes and finally a rinse with running deionized water for 60 s.
The method for thermally cleaning the Si substrate 1 is: and putting the cleaned substrate into a low-pressure MOCVD reaction chamber, introducing hydrogen, raising the temperature to 1000 ℃, controlling the pressure of the reaction chamber to be 40Torr, and carrying out heat treatment on the substrate in a hydrogen atmosphere for 3 min.
Next, at least one GeSnSi epitaxial layer is grown on the back surface of the Si substrate 1.
Specifically, the number of the GeSnSi epitaxial layers may be 1 or multiple, and this embodiment is not limited further, and the purpose of reducing material warpage can be achieved as long as the GeSnSi epitaxial layer is grown on the back surface of the Si substrate 1.
When the GeSnSi epitaxial layers are multilayer, the mass fraction of Ge components and the mass fraction of Sn components in the GeSnSi epitaxial layers are increased along with the increase of the number of the epitaxial layers, and the mass fraction of Si components is reduced to form a gradual epitaxial layer, so that the crystal quality of the GeSnSi layers is improved by gradually reducing the lattice mismatch between the Si substrate and the back GeSnSi layers while keeping larger compressive stress by utilizing the multiple GeSnSi layers.
In a specific embodiment, the number of the GeSnSi epitaxial layers is 2, that is, the GeSnSi epitaxial layers include the first GeSnSi epitaxial layer 71 and the second GeSnSi epitaxial layer 72, in which case, step S1 includes:
s11, growing a first GeSnSi epitaxial layer 71 on the back side of the Si substrate 1, as shown in fig. 2 b.
By utilizing a vapor deposition method, firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing a GeSnSi alloy with the thickness of 1.0-1.4 mu m on the back surface of the Si substrate 1, wherein the mass fraction of the Si component is 0.98, the mass fraction of the Ge component is 0.015, and the mass fraction of the Sn component is 0.005 to form a first GeSnSi epitaxial layer 71.
In a specific embodiment, after the thermal cleaning stage, the Si substrate 1 is taken out, and placed into an Ultra High Vacuum Vapor Deposition (UHVCVD) reaction chamber, first, a Si source and a Ge source are introduced at a temperature of 700 ℃ in the reaction chamber, then, a Sn source is introduced at a temperature of 300 ℃ in the reaction chamber, and GeSnSi with a thickness of 1.2 μm is grown on the back surface of the Si substrate 1, wherein the mass fraction of the Si component is 0.98, the mass fraction of the Ge component is 0.015, and the mass fraction of the Sn component is 0.005, so as to form the first GeSnSi epitaxial layer 71.
S12, growing a second GeSnSi epitaxial layer 72 on the back of the first GeSnSi epitaxial layer 71, as shown in fig. 2 c.
By utilizing a vapor deposition method, firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing a GeSnSi alloy with the thickness of 1.0-1.4 mu m on the back surface of the first GeSnSi epitaxial layer 71, wherein the mass fraction of the Si component is 0.96, the mass fraction of the Ge component is 0.03, and the mass fraction of the Sn component is 0.01 to form the second GeSnSi epitaxial layer 72.
In a specific embodiment, a second GeSnSi epitaxial layer 72 is formed by introducing a Si source and a Ge source at a CVD reaction chamber temperature of 700 ℃ and then introducing a Sn source at a reaction chamber temperature of 300 ℃ to grow GeSnSi with a thickness of 1.2 μm on the back surface of the first GeSnSi epitaxial layer 71, wherein the Si component mass fraction is 0.96, the Ge component mass fraction is 0.03 and the Sn component mass fraction is 0.01.
After that, the sample is subjected to annealing treatment.
In this embodiment, the mass fraction of the Si component in the first GeSnSi epitaxial layer 71 is 0.98, the mass fraction of the Ge component is 0.015, the mass fraction of the Sn component is 0.005, the mass fraction of the Si component in the second GeSnSi epitaxial layer 72 is 0.96, the mass fraction of the Ge component is 0.03, and the mass fraction of the Sn component is 0.01; that is, the mass fraction of the Ge component in the first GeSnSi epitaxial layer 71 is smaller than the mass fraction of the Ge component in the second GeSnSi epitaxial layer 72, and the mass fraction of the Sn component in the first GeSnSi epitaxial layer 71 is smaller than the mass fraction of the Sn component in the second GeSnSi epitaxial layer 72, so that the mass fraction of the Si component in the first GeSnSi epitaxial layer 71 is larger than the mass fraction of the Si component in the second GeSnSi epitaxial layer 72.
GeSnSi with larger Si component mass fraction is firstly extended on the back of the Si substrate to be used as a transition layer, and then GeSnSi with smaller Si component mass fraction is extended, so that the lattice mismatch between the Si substrate and a subsequently grown GeSnSi epitaxial layer can be reduced, and the preparation for extending the GeSnSi layer with high quality is made.
S2, sequentially growing an AlN nucleation layer 3, an AlGaN graded layer 4, a GaN buffer layer 5, and an AlGaN barrier layer 6 on the front surface of the Si substrate 1, to form a silicon-based AlGaN/GaN HEMT device, as shown in fig. 2 d.
Specifically, an AlN nucleating layer 3, an AlGaN graded layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 are sequentially grown on the front surface of a Si substrate 1 by utilizing a metal organic compound chemical vapor deposition method to form the silicon-based AlGaN/GaN HEMT device.
Step S2 specifically includes the steps of:
s21, epitaxially growing a first AlN nucleation layer 31 on the Si substrate 1.
Specifically, the MOCVD method is used to simultaneously open trimethyl aluminum (TMAl) and NH3The air passage, adjusting the flow rate of TMAl to 240-3The flow rate is 3800-.
In one particular embodiment, the growth conditions of the first AlN nucleation layer 31 are: TMAl flow rate of 260sccm, NH3The flow rate is 4000sccm, the growth temperature is 900 ℃, the growth time is 60min, and the thickness of the formed first AlN nucleation layer 31 is 30 nm.
S22, epitaxially growing a second AlN nucleation layer 32 on the first AlN nucleation layer 31.
Specifically, the temperature of the reaction chamber is raised to 1200-.
In one particular embodiment, the growth conditions for the second AlN nucleation layer 32 are: TMAl flow rate of 190sccm, NH3The flow rate is 1400sccm, the growth temperature is 1210 ℃, the growth time is 60min, and the thickness of the formed second AlN nucleation layer 32 is 170 nm.
S23, a first AlGaN layer 41 is prepared on the second AlN nucleation layer 32.
Specifically, the temperature of the reaction chamber is lowered to 1140-1160 deg.C, and TMAl, TMGa, NH are adjusted at this time3The flow rate is 190-.
In one embodiment, the first AlGaN layer 41 is grown under the conditions of a chamber temperature of 1150 ℃, TMAl, TMGa, NH3The first AlGaN layer 41 is grown to have a thickness of 190sccm, 10sccm, 2700sccm350nm and the Al component accounts for 35 percent by mass.
S24, a second AlGaN layer 42 is prepared on the first AlGaN layer 41.
Specifically, the temperature of the reaction chamber is kept at 1140-1160 ℃, and TMAl, TMGa and NH are adjusted3The flow rates are respectively 160-170sccm, 20sccm and 2920sccm-3580sccm, and AlGaN with the thickness of 390-410nm is grown to form the second AlGaN layer 42 with the Al component mass fraction of 70-80%.
In one embodiment, the growth conditions for second AlGaN layer 42 are: the temperature of the reaction chamber is 1150 ℃, TMAl, TMGa and NH3The flow rates are respectively 162sccm, 20sccm and 3000sccm, the thickness of the grown second AlGaN layer 42 is 400nm, and the mass fraction of the Al component is 75%.
Further, the first AlGaN layer 41 and the second AlGaN layer 42 together form the graded AlGaN buffer layer 4.
S25, a GaN layer 5 is grown on the AlGaN buffer layer 3.
Specifically, the temperature of the reaction chamber is kept constant, the TMAl source is closed, and TMGa and NH are adjusted3The flow rates are respectively 190-.
In a specific embodiment, the growth conditions of the GaN buffer layer 5 are: the temperature of the reaction chamber is 1150 ℃, the TMGa flow is 192sccm, NH3The flow rate was 9000sccm, and the thickness of the GaN buffer layer 5 was 1 μm.
S26, an AlGaN barrier layer 6 is formed on GaN buffer layer 5.
Specifically, the temperature of the reaction chamber is increased to 1190 ℃, the TMAl source is opened, and TMAl, TMGa and NH are adjusted at the moment3The flow rates are respectively 70-90sccm, 35-50sccm and 10000-plus-24000 sccm, and an AlGaN layer with the thickness of 200-plus-300 nm is deposited to form the AlGaN barrier layer 6.
In one embodiment, the AlGaN barrier layer 6 is grown under conditions of a chamber temperature of 1190 deg.C, TMAl flow of 80sccm, TMGa flow of 43sccm, NH3The flow rate was 20000sccm, and the AlGaN barrier layer 6 was formed to a thickness of 250 nm.
And S3, cooling the silicon-based AlGaN/GaN HEMT device.
Specifically, the AlGaN/GaN HEMT device may be cooled to room temperature in a reaction chamber of the AlGaN/GaN HEMT, or the silicon-based AlGaN/GaN HEMT device may be placed in a room temperature environment for cooling. In this embodiment, since the silicon-based AlGaN/GaN HEMT device is prepared by using the metal organic compound chemical vapor deposition apparatus, the HEMT device is continuously cooled in the MOCVD apparatus.
In the process of cooling the HEMT device, as the thermal expansion coefficient of GeSnSi is larger than that of Si, GeSnSi can introduce certain compressive stress into the substrate, and plays a certain role in counteracting the tensile stress in the silicon-based AlGaN/GaN HEMT device, thereby achieving the purpose of reducing warpage and improving the yield of materials.
Fig. 2d shows a structure of the silicon-based AlGaN/GaN HEMT device manufactured by the above manufacturing method, where fig. 2d is a schematic structural view of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention. The silicon-based AlGaN/GaN HEMT device comprises at least one GeSnSi epitaxial layer, a Si substrate 1, an AlN nucleating layer 3, an AlGaN step layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 which are sequentially stacked. For specific parameters of each layer in the silicon-based AlGaN/GaN HEMT device, reference is made to the above description, which is not repeated herein.
According to the silicon-based AlGaN/GaN HEMT device, the GeSnSi layer with a larger thermal expansion coefficient is arranged on the back surface of the Si substrate, so that the device has lower warping degree, and the yield of materials is improved.
Example two
On the basis of the first embodiment, the present embodiment provides another preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate, where the preparation method includes the steps of:
and S1, sequentially growing at least one GeSnSi epitaxial layer on the back surface of the Si substrate 1.
And S2, preparing a pre-paved aluminum layer 2 on the front surface of the Si substrate 1.
Specifically, the temperature of the reaction chamber is raised to 1080-.
In one embodiment, the pre-laid aluminum layer 2 is prepared under conditions of a chamber temperature of 1085 ℃ and a TMAl flow of 20 sccm.
S3, growing an AlN nucleating layer 3, an AlGaN graded layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 in sequence on the front surface of the pre-laid aluminum layer 2 to form the silicon-based AlGaN/GaN HEMT device
And S4, cooling the silicon-based AlGaN/GaN HEMT device.
Referring to fig. 3, fig. 3 is a schematic structural view of another silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back surface of a substrate according to an embodiment of the present invention. The silicon-based AlGaN/GaN HEMT comprises at least one GeSnSi epitaxial layer, a Si substrate 1, a pre-paved aluminum layer 2, an AlN nucleating layer 3, an AlGaN graded layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 which are sequentially stacked.
In this embodiment, pre-laid aluminum is disposed between the Si substrate and the AlN nucleation layer, which not only can improve the growth effect of the nucleation layer, but also can improve the crystal quality of GaN, thereby improving the device performance.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A preparation method of a silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back of a substrate is characterized by comprising the following steps:
s1, growing at least one GeSnSi epitaxial layer on the back of the Si substrate (1);
s2, growing an AlN nucleating layer (3), an AlGaN graded layer (4), a GaN buffer layer (5) and an AlGaN barrier layer (6) on the front surface of the Si substrate (1) in sequence to form a silicon-based AlGaN/GaN HEMT device;
and S3, cooling the silicon-based AlGaN/GaN HEMT device.
2. The method for preparing a silicon-based AlGaN/GaN HEMT with a GeSnSi epitaxial layer on the back of a substrate according to claim 1, wherein the step S1 comprises the steps of:
s11, growing a first GeSnSi epitaxial layer (71) on the back surface of the Si substrate (1);
and S12, growing a second GeSnSi epitaxial layer (72) on the back of the first GeSnSi epitaxial layer (71).
3. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate according to claim 2, wherein the mass fraction of Ge component in the first GeSnSi epitaxial layer (71) is smaller than the mass fraction of Ge component in the second GeSnSi epitaxial layer (72), and the mass fraction of Sn component in the first GeSnSi epitaxial layer (71) is smaller than the mass fraction of Sn component in the second GeSnSi epitaxial layer (72).
4. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate according to claim 2, wherein the step S11 comprises:
by utilizing a vapor deposition method, firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the Si substrate (1), wherein the mass fraction of the Si component is 0.98, the mass fraction of the Ge component is 0.015, and the mass fraction of the Sn component is 0.005 to form the first GeSnSi epitaxial layer (71).
5. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate according to claim 2, wherein the step S12 comprises:
by utilizing a vapor deposition method, firstly introducing a Si source and a Ge source under the condition that the temperature of a reaction chamber is 690-710 ℃, then introducing a Sn source under the condition that the temperature of the reaction chamber is 100-400 ℃, and growing GeSnSi with the thickness of 1.0-1.4 mu m on the back surface of the first GeSnSi epitaxial layer (71), wherein the mass fraction of the Si component is 0.96, the mass fraction of the Ge component is 0.03, and the mass fraction of the Sn component is 0.01 to form the second GeSnSi epitaxial layer (72).
6. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate according to claim 1, wherein the step S2 comprises the steps of:
and sequentially growing an AlN nucleating layer (3), an AlGaN graded layer (4), a GaN buffer layer (5) and an AlGaN barrier layer (6) on the front surface of the Si substrate (1) by utilizing a metal organic compound chemical vapor deposition method to form the silicon-based AlGaN/GaN HEMT device.
7. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate of claim 6, wherein the step S3 comprises the following steps:
and cooling the silicon-based AlGaN/GaN HEMT device to room temperature in metal organic compound chemical vapor deposition equipment.
8. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate according to claim 1, wherein the step between S1 and S2 further comprises the steps of:
and preparing a pre-laid aluminum layer (2) on the front surface of the Si substrate (1).
9. The method for preparing the silicon-based AlGaN/GaN HEMT based on the GeSnSi epitaxial layer on the back of the substrate according to claim 8, wherein the preparation conditions of the pre-laid aluminum layer (2) are as follows: the temperature of the reaction chamber is 1080-.
10. A silicon-based AlGaN/GaN HEMT based on a GeSnSi epitaxial layer on the back of a substrate is characterized by being prepared by the preparation method of any one of claims 1-9.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080187768A1 (en) * 2005-03-11 2008-08-07 The Arizona Board Of Regents Novel Gesisn-Based Compounds, Templates, and Semiconductor Structures
CN101887848A (en) * 2009-05-13 2010-11-17 硅电子股份公司 Comprise silicon monocrystalline substrate with front side and dorsal part and the production method that is deposited on the wafer of the SiGe layer on the front side
US20110140118A1 (en) * 2009-12-11 2011-06-16 National Semiconductor Corporation Backside stress compensation for gallium nitride or other nitride-based semiconductor devices
KR20170133152A (en) * 2016-05-25 2017-12-05 전북대학교산학협력단 Template epi substrates and manufacturing method thereof
CN110767766A (en) * 2018-07-26 2020-02-07 上海新微技术研发中心有限公司 Strain balance GeSn infrared photoelectric detector and manufacturing method thereof
CN210120127U (en) * 2019-08-29 2020-02-28 厦门市三安集成电路有限公司 Composite silicon substrate
CN113192820A (en) * 2021-03-12 2021-07-30 南昌大学 Preparation method of silicon substrate aluminum nitride film

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080187768A1 (en) * 2005-03-11 2008-08-07 The Arizona Board Of Regents Novel Gesisn-Based Compounds, Templates, and Semiconductor Structures
CN101887848A (en) * 2009-05-13 2010-11-17 硅电子股份公司 Comprise silicon monocrystalline substrate with front side and dorsal part and the production method that is deposited on the wafer of the SiGe layer on the front side
US20110140118A1 (en) * 2009-12-11 2011-06-16 National Semiconductor Corporation Backside stress compensation for gallium nitride or other nitride-based semiconductor devices
KR20170133152A (en) * 2016-05-25 2017-12-05 전북대학교산학협력단 Template epi substrates and manufacturing method thereof
CN110767766A (en) * 2018-07-26 2020-02-07 上海新微技术研发中心有限公司 Strain balance GeSn infrared photoelectric detector and manufacturing method thereof
CN210120127U (en) * 2019-08-29 2020-02-28 厦门市三安集成电路有限公司 Composite silicon substrate
CN113192820A (en) * 2021-03-12 2021-07-30 南昌大学 Preparation method of silicon substrate aluminum nitride film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MING XIAO ET AL: "High performance Al0.10Ga0.90N channel HEMTs", 《IEEE ELECTRON DEVICE LETTERS》, vol. 39, no. 8, 31 August 2018 (2018-08-31), pages 1149 - 1151 *

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