CN116646248B - Epitaxial wafer preparation method, epitaxial wafer thereof and high-electron mobility transistor - Google Patents

Epitaxial wafer preparation method, epitaxial wafer thereof and high-electron mobility transistor Download PDF

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CN116646248B
CN116646248B CN202310745389.1A CN202310745389A CN116646248B CN 116646248 B CN116646248 B CN 116646248B CN 202310745389 A CN202310745389 A CN 202310745389A CN 116646248 B CN116646248 B CN 116646248B
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layer
epitaxial wafer
buffer layer
silicon substrate
preparing
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CN116646248A (en
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刘春杨
吕蒙普
胡加辉
金从龙
顾伟
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

The invention provides a preparation method of an epitaxial wafer, the epitaxial wafer and a high electron mobility transistor thereof, wherein the method comprises the steps of providing a silicon substrate; taking nitrogen as carrier gas, and simultaneously introducing GeCl4 and TMAL to pretreat the silicon substrate to form a Ge-Al pre-paved layer; and sequentially growing a first buffer layer, a second buffer layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the Ge-Al pre-paved layer. The invention solves the problems of easy surface morphology deterioration, warpage and cracking of the subsequent buffer layer when the breakdown voltage of the epitaxial wafer is improved in the prior art.

Description

Epitaxial wafer preparation method, epitaxial wafer thereof and high-electron mobility transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of an epitaxial wafer, the epitaxial wafer and a high-electron-mobility transistor.
Background
As a third-generation semiconductor material, the GaN-based material has the advantages of large forbidden bandwidth, high electron saturation drift speed, good chemical stability, radiation resistance, high temperature resistance, easiness in forming heterojunction and the like, and becomes a preferred material for manufacturing a high-temperature, high-frequency, high-power and radiation resistance High Electron Mobility Transistor (HEMT) structure. The GaN-based heterostructure has high carrier concentration and electron mobility, on-resistance is small, and the advantage of forbidden band width enables the GaN-based heterostructure to bear high working voltage. Therefore, the GaN-based HEMT is suitable for application fields such as high-temperature high-frequency high-power devices, low-loss-rate switching devices and the like.
For a GaN-based HEMT power device, leakage in the off state and power output in the on state are important indicators for measuring the performance of the electronic device. In the application field of microwave power devices, when the devices work at high frequency, the energy loss is caused by the electric leakage of the devices, and the working performance of the devices is deteriorated. Low leakage in the off state can be reducedLow off-state loss of the device and can improve the working voltage of the device. Compared with the traditional Si material, the GaN material has wider forbidden bandwidth and theoretically has larger critical breakdown field strength. However, the unintentionally doped GaN film grown by MOCVD is usually N-type, and the concentration of bulk electrons is in the order of 10 17 cm -3 The prepared GaN-based HEMT material structure cannot show the high voltage-resistant advantage of the third-generation semiconductor material due to the existence of the low-resistance conducting layer. The leakage path of the HEMT device mainly vertically passes through the buffer layer in the HEMT and then horizontally passes through the silicon body material (AlN/Si interface), so that the main bottleneck for limiting the improvement of the breakdown voltage of the device is the epitaxial buffer layer, the silicon material and the interface between the epitaxial buffer layer and the epitaxial layer.
In order to improve the off-state breakdown voltage of the HEMT device, the HEMT device can be designed from two aspects of a silicon substrate and an epitaxial buffer layer. The interface processing method mainly comprises the steps of firstly introducing SiH 4 Pre-treating, then pre-paving Al, wherein Si has an anti-surfactant effect, a monoatomic layer Si-Al is easy to form on the surface, repulsive electric dipole moment is introduced, the subsequent AlN buffer layer is prevented from continuously growing on the surface, the surface appearance is deteriorated, and Si doping can also cause dislocation in an AlN material to incline in the dislocation climbing process due to the interaction between Si atoms and linear dislocation, so that tensile stress is introduced, and the AlN is warped, cracked and other problems are caused. Therefore, the prior art is easy to have the problems of surface morphology deterioration, warping and cracking of the subsequent buffer layer when the breakdown voltage of the epitaxial wafer is improved.
Disclosure of Invention
Based on the above, the invention aims to provide a preparation method of an epitaxial wafer, the epitaxial wafer and a high electron mobility transistor thereof, and aims to solve the problems that the surface morphology of a subsequent buffer layer is easy to deteriorate, warp and crack when the breakdown voltage of the epitaxial wafer is improved in the prior art.
The embodiment of the invention is realized as follows:
in one aspect, an embodiment of the present invention provides a method for preparing an epitaxial wafer, the method including;
providing a silicon substrate;
with nitrogen as carrierGas is simultaneously introduced into GeCl 4 And TMAL pre-treating the silicon substrate to form a Ge-Al pre-paved layer;
and sequentially growing a first buffer layer, a second buffer layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the Ge-Al pre-paved layer.
Further, in the epitaxial wafer preparation method, the GeCl 4 The flow rate of the gas is 200sccm to 800sccm.
Further, in the epitaxial wafer preparation method, the inflow rate of TMAL is 10 sccm-20 sccm.
Further, in the epitaxial wafer preparation method, the pretreatment time is 1-3 min.
Further, in the epitaxial wafer preparation method, the pretreatment temperature is 850-1000 ℃.
Further, in the epitaxial wafer preparation method, the pretreatment pressure is 50 mbar-100 mbar.
Further, in the epitaxial wafer preparation method, geCl is introduced simultaneously 4 And before the step of preprocessing the silicon substrate by TMAL to form the Ge-Al pre-paved layer, the method further comprises the following steps:
carrying out high-temperature treatment on the silicon substrate for a preset time under a set condition through an MOCVD system;
wherein in the set condition, the temperature of the cavity is 1000-1200 ℃ and the atmosphere is H 2 The cavity pressure is 50 mbar-150 mbar.
In another aspect, the present invention provides an epitaxial wafer, which is prepared by the method for preparing an epitaxial wafer according to any one of the above, and the epitaxial wafer includes:
and the silicon substrate is sequentially laminated with the Ge-Al pre-paved layer, the first buffer layer, the second buffer layer, the high-resistance buffer layer, the channel layer, the insertion layer, the barrier layer and the cap layer.
Further, the first buffer layer and the insertion layer are all AlN layers, the second buffer layer and the barrier layer are all AlGaN layers, and the high-resistance buffer layer, the channel layer and the cap layer are all GaN layers.
In yet another aspect, the present invention provides a high electron mobility transistor comprising the epitaxial wafer described above.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
simultaneously introducing GeCl 4 And TMAL pretreatment, which is favorable for reducing the background carrier concentration of an interface, reducing the electric leakage of a buffer layer, improving the pinch-off characteristic and the withstand voltage characteristic of a device, improving the breakdown voltage of an epitaxial wafer, and ensuring that the influence of the addition of Ge impurities on the stress of an AlN (or GaN) lattice structure is smaller than that of Si atom impurities. The problems of surface appearance deterioration caused by the continued growth of AlN (or GaN) on the surface, and warping, cracking and the like caused by the interaction between Si atoms and threading dislocation and the inclination of dislocation in the AlN (or GaN) material in the dislocation climbing process are avoided, so that tensile stress is introduced. And nitrogen is used as carrier gas, so that Ge liquid drops are prevented from being easily formed on the surface of the grown crystal, the growth of the crystal is hindered, pits are formed in the crystal, and high-quality AlN (or GaN) is obtained.
Drawings
Fig. 1 is a flowchart of a method for preparing an epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention;
the invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Aiming at the problems that the surface morphology of a subsequent buffer layer is easy to deteriorate, warp and crack when the breakdown voltage of an epitaxial wafer is improved, the embodiment of the invention provides an epitaxial wafer preparation method, an epitaxial wafer and a high electron mobility transistor thereof, wherein:
referring to fig. 1, a method for preparing an epitaxial wafer according to an embodiment of the present invention is shown, which includes steps S10 to S12.
Step S10, a silicon substrate is provided.
Specifically, in the embodiment of the present invention, the silicon substrate preferably adopts a silicon substrate with a p-type crystal orientation.
Step S11, taking nitrogen as carrier gas and simultaneously introducing GeCl 4 And TMAL pre-treating the silicon substrate to form a Ge-Al pre-paved layer.
It can be appreciated that the GeCl is introduced at the same time 4 And TMAL pretreatment, which is favorable for reducing the background carrier concentration of an interface, reducing the electric leakage of a buffer layer, improving the pinch-off characteristic and the withstand voltage characteristic of a device, improving the breakdown voltage of an epitaxial wafer, and ensuring that the influence of the addition of Ge impurities on the stress of an AlN (or GaN) lattice structure is smaller than that of Si atom impurities. The problems of surface appearance deterioration caused by the continued growth of AlN (or GaN) on the surface, and warping, cracking and the like caused by the interaction between Si atoms and threading dislocation and the inclination of dislocation in the AlN (or GaN) material in the dislocation climbing process are avoided, so that tensile stress is introduced. And nitrogen is used as carrier gas to avoid growing crystalThe bulk surface is prone to forming Ge droplets, impeding crystal growth, leading to pit formation in the crystal, and high quality AlN (or GaN) is obtained.
Specifically, geCl 4 The flow rate of the gas is 200sccm to 800sccm. The inflow rate of TMAL is 10sccm to 20sccm. The pretreatment time is 1-3 min. The pretreatment temperature is 850-1000 ℃. The pretreatment pressure is 50mbar to 100mbar.
In addition, in some optional embodiments of the present invention, in order to further enhance the processing effect of the silicon substrate, the GeCl is introduced at the same time 4 And before the step of preprocessing the silicon substrate by TMAL to form the Ge-Al pre-paved layer, the method further comprises the following steps:
carrying out high-temperature treatment on the silicon substrate for a preset time under a set condition through an MOCVD system;
wherein in the set condition, the temperature of the cavity is 1000-1200 ℃ and the atmosphere is H 2 The cavity pressure is 50 mbar-150 mbar.
And step S12, sequentially growing a first buffer layer, a second buffer layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the Ge-Al pre-paved layer.
The temperature is adjusted to 1000-1200 ℃ after the growth of the Ge-Al pre-paved layer is finished, and the first buffer layer of the AlN layer with the thickness of 150-300 nm is grown, wherein the growth pressure is 40-100 mbar.
After the growth of the first buffer layer is finished, a second buffer layer of the AlGaN layer is grown, the thickness of the second buffer layer is 1.0-3.0 microns, the growth temperature is 1000-1200 ℃, the growth pressure is 30-100 mbar, and the Al component range is 0.1-0.8.
After the second buffer layer of the AlGaN layer is grown, growing a high-resistance buffer layer of the C-doped GaN layer, wherein the thickness of the high-resistance buffer layer is 1.0-2.0 microns, the growth temperature is 950-1050 ℃, the growth pressure is 50-100 mbar, and the C doping concentration is 10 19 cm -3 ~10 20 cm -3 。
And after the growth of the high-resistance buffer layer is finished, the thickness of the channel layer of the GaN layer is 300-600 nm, the growth temperature is 1050-1150 ℃, and the pressure is 100-300 mbar.
And after the growth of the channel layer of the GaN layer is finished, an inserting layer of the AlN layer is grown, the thickness is 1 nm, the growth temperature is 1050-1150 ℃, and the pressure is 30-100 mbar.
And after the growth of the insertion layer of the AlN layer is finished, a barrier layer of the AlGaN layer grows, the thickness is 20-25 nm, the growth temperature is 1050-1150 ℃, the pressure is 30-100 mbar, and the Al component is 0.20-0.25.
And after the growth of the barrier layer of the AlGaN layer is finished, the capping layer of the GaN layer is grown, the thickness is 3-5 nm, the growth temperature is 1050-1150 ℃, and the pressure is 30-100 mbar.
After the epitaxial structure growth is completed, the temperature of the reaction chamber is reduced, and the epitaxial growth is completed after the reaction chamber is cooled to room temperature in a nitrogen atmosphere. Trimethylaluminum (TMAl), trimethylgallium, or triethylgallium (TMGa or TEGa) as a precursor of a group iii source; ammonia gas is used as a precursor of a V group source, geCl 4 And CBr 4 As dopants, nitrogen and hydrogen were used as carrier gases.
Referring to fig. 2, on the other hand, an embodiment of the present invention provides an epitaxial wafer prepared by the above-mentioned epitaxial wafer preparation method, wherein:
the epitaxial wafer comprises:
a silicon substrate 1, a Ge-Al pre-layer 2, a first buffer layer 3, a second buffer layer 54, a high-resistance buffer layer 5, a channel layer 6, an insertion layer 7, a barrier layer 8 and a cap layer 9 which are sequentially stacked on the silicon substrate 1.
In the embodiment of the present invention, the first buffer layer 3 and the insertion layer 7 may be AlN layers, the second buffer layer 4 and the barrier layer 8 may be AlGaN layers, and the high-resistance buffer layer 5, the channel layer 6, and the cap layer 9 may be GaN layers.
On the other hand, the high electron mobility transistor provided by the embodiment of the invention comprises the epitaxial wafer.
In order that the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments that are illustrated in the appended drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Example 1
The first embodiment of the invention provides a preparation method of an epitaxial wafer, which comprises the following steps:
providing a silicon substrate;
taking nitrogen as carrier gas, and simultaneously introducing GeCl4 and TMAL to pretreat the silicon substrate to form a Ge-Al pre-paved layer;
and sequentially growing a first buffer layer, a second buffer layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the Ge-Al pre-paved layer.
Wherein GeCl 4 The flow rate of TMAL was 200sccm and the flow rate of TMAL was 10 sccm.
Example two
The second embodiment of the present invention also provides a method for preparing an epitaxial wafer, which is different from the first embodiment in that:
wherein GeCl 4 The flow rate of TMAL was 500sccm and the flow rate of TMAL was 15sccm.
Example III
The third embodiment of the present invention also provides a method for preparing an epitaxial wafer, which is different from the first embodiment in that:
wherein GeCl 4 The flow rate of TMAL was 800sccm and the flow rate of TMAL was 20sccm.
For comparison with the above-described embodiments of the present invention, the following comparative examples are also presented.
Comparative example one
The first comparative example of the present invention also proposes an epitaxial wafer manufacturing method, which differs from the epitaxial wafer manufacturing method of the first example in that:
the silicon substrate is not processed.
Comparative example two
The second comparative example of the present invention also provides a method for producing an epitaxial wafer, which is different from the first comparative example in that:
si was introduced at a flow rate of 500sccm, and TMAL was introduced at a flow rate of 15.
Please refer to the following table one, which shows the parameters corresponding to the above-mentioned embodiments one to three and the comparative examples one and two.
List one
In practical application, the corresponding epitaxial wafers are prepared by adopting the preparation methods and parameters corresponding to the first embodiment to the third embodiment and the first and second comparison embodiments of the present invention, and the performance test is performed on the epitaxial wafers prepared in each embodiment and the epitaxial wafers prepared in the comparison embodiment, wherein the test data are shown in the following table two.
It should be noted that, in order to ensure the reliability of the verification result, the first embodiment to the fifth embodiment, and the first and second comparative embodiments of the present invention should be identical except for the above parameters, for example, the manufacturing process and parameters of each layer of the epitaxial wafer should be kept consistent.
Watch II
The data of the first table and the second table are combined, and the GeCl4 and the TMAL are introduced for pretreatment, so that the background carrier concentration of an interface is reduced, the electric leakage of a buffer layer is reduced, the pinch-off characteristic and the voltage-withstanding characteristic of a device are improved, and the breakdown voltage of an epitaxial wafer is improved.
In addition, as can be clearly seen by combining the first embodiment, the second embodiment and the third embodiment, the proper access flow obviously improves the breakdown voltage of the epitaxial wafer.
As is apparent from the combination of the second embodiment and the second comparative embodiment, the GeCl is introduced at the same time 4 And TMAL pretreatment not only avoids the easy existence of follow-up when the breakdown voltage of the epitaxial wafer is improvedThe buffer layer has the problems of surface appearance deterioration, warping and cracking, and the breakdown voltage of the epitaxial wafer is further improved.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (9)

1. A method of preparing an epitaxial wafer, the method comprising;
providing a silicon substrate;
nitrogen is taken as carrier gas, and GeCl is simultaneously introduced 4 And TMAL pre-treating the silicon substrate to form a Ge-Al pre-paved layer;
sequentially growing a first buffer layer, a second buffer layer, a high-resistance buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on the Ge-Al pre-paved layer;
the first buffer layer and the insertion layer are all AlN layers, the second buffer layer and the barrier layer are all AlGaN layers, and the high-resistance buffer layer, the channel layer and the cap layer are all GaN layers.
2. The method for preparing an epitaxial wafer according to claim 1, wherein the geci 4 The flow rate of the gas is 200sccm to 800sccm.
3. The method for preparing an epitaxial wafer according to claim 1, wherein the TMAl has an inflow rate of 10sccm to 20sccm.
4. The method for preparing an epitaxial wafer according to claim 1, wherein the pretreatment time is 1-3 min.
5. The method for preparing an epitaxial wafer according to claim 1, wherein the pretreatment temperature is 850 ℃ to 1000 ℃.
6. The method for producing epitaxial wafers according to claim 1, wherein the pretreatment pressure is 50mbar to 100mbar.
7. The method for preparing an epitaxial wafer according to any one of claims 1 to 6, characterized in that geci is introduced simultaneously 4 And before the step of preprocessing the silicon substrate by TMAL to form the Ge-Al pre-paved layer, the method further comprises the following steps:
carrying out high-temperature treatment on the silicon substrate for a preset time under a set condition through an MOCVD system;
wherein in the set condition, the temperature of the cavity is 1000-1200 ℃ and the atmosphere is H 2 The cavity pressure is 50 mbar-150 mbar.
8. An epitaxial wafer, characterized in that it is prepared by the epitaxial wafer preparation method according to any one of claims 1 to 7, comprising:
and the silicon substrate is sequentially laminated with the Ge-Al pre-paved layer, the first buffer layer, the second buffer layer, the high-resistance buffer layer, the channel layer, the insertion layer, the barrier layer and the cap layer.
9. A high electron mobility transistor comprising the epitaxial wafer of claim 8.
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