CN113937161B - Si-based AlGaN/GaN high electron mobility transistor with wrapping buried layer and preparation method thereof - Google Patents
Si-based AlGaN/GaN high electron mobility transistor with wrapping buried layer and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 96
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- 238000010899 nucleation Methods 0.000 claims description 60
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 19
- 229910052782 aluminium Inorganic materials 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 2
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- 125000006850 spacer group Chemical group 0.000 claims 1
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- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 12
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention relates to a Si-based AlGaN/GaN high electron mobility transistor with a wrapping buried layer and a preparation method thereof. According to the high electron mobility transistor, the N-type buried layer and the isolation layer are arranged in the Si substrate, the N-type impurities in the N-type buried layer cannot be completely masked by the isolation layer, and the N-type impurities can diffuse into the Si substrate, so that the P-type channel concentration of the Si substrate introduced by Al diffusion in an upper structure is counteracted, the substrate resistivity is improved, and the radio frequency loss of a device is reduced.
Description
Technical Field
The invention belongs to semiconductors, and particularly relates to a Si-based AlGaN/GaN high electron mobility transistor with a wrapping buried layer and a preparation method thereof.
Background
GaN, which is a typical representation of the third generation of wide bandgap semiconductor materials, is widely used in radio frequency devices, light emitting diodes and power electronics due to its large bandgap (3.4 ev), large breakdown field strength, strong radiation resistance, etc. AlGaN/GaN high electron mobility transistors (High Electron Mobility Transistor, HEMT) are used as common GaN structures, are widely applied to a plurality of fields of emerging 5G communication, radar, space exploration and the like due to high two-dimensional electron gas mobility and two-dimensional electron gas density, and have high requirements on the radio frequency performance of AlGaN/GaN HEMT devices.
Conventional AlGaN/GaN HENT heteroepitaxial substrates are composed of SiC, sapphire and Si substrates. Although SiC performs best, its large-scale commercial application is limited because large-size substrates are expensive; sapphire substrates are also limited in application because of poor thermal conductivity. In contrast, si substrates are inexpensive and have higher thermal conductivity, and are compatible with Si conventional processes, receiving great attention. However, the silicon-based AlGaN/GaN HEMT has larger radio frequency loss, wherein one source of radio frequency loss is caused by diffusion of Al into a P-type conductive channel formed by a silicon substrate, and the conductive channel can add additional radio frequency loss, so that the resistivity of the substrate is reduced, and the radio frequency loss is improved.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a Si-based AlGaN/GaN high electron mobility transistor with a wrapping buried layer and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
the embodiment of the invention provides a Si-based AlGaN/GaN high electron mobility transistor with a wrapping buried layer, which comprises a Si substrate, an AlN nucleation layer, an AlGaN graded layer, a GaN buffer layer and an AlGaN barrier layer which are sequentially laminated, wherein,
an N-type buried layer and an isolation layer are arranged in the Si substrate, and the isolation layer is arranged between the Si substrate and the N-type buried layer and wraps the N-type buried layer.
In one embodiment of the present invention, the doping elements of the N-type buried layer include P and As; when the doping element is P, the doping concentration is 10 13 -10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the When the doping element is As, the doping concentration is 10 14 -10 16 cm -3 。
In one embodiment of the invention, the material of the isolation layer comprises SiO 2 The thickness is 1.5-2nm.
In one embodiment of the present invention, the thickness of the isolation layer around the N-type buried layer is equal.
In one embodiment of the invention, the AlN nucleation layer comprises a first AlN nucleation layer and a second AlN nucleation layer, wherein the second AlN nucleation layer is positioned on the first AlN nucleation layer, and the nucleation temperature of the second AlN nucleation layer is larger than that of the first AlN nucleation layer.
In one embodiment of the present invention, the AlGaN graded layer includes a first AlGaN layer and a second AlGaN layer, wherein the second AlGaN layer is located on the first AlGaN layer, and the Al composition mass fraction of the second AlGaN layer is greater than the Al composition mass fraction of the first AlGaN layer.
In one embodiment of the invention, a pre-clad aluminum layer is further included, wherein the pre-clad aluminum layer is located between the Si substrate and the AlN nucleation layer.
In one embodiment of the invention, the pre-laid aluminum layer has a thickness of less than 10nm.
Another embodiment of the present invention provides a method for fabricating a Si-based AlGaN/GaN high electron mobility transistor with a buried encapsulation layer, comprising the steps of:
s1, preparing a first isolation sub-layer in a Si sheet;
s2, carrying out ion implantation on the surface layer of the first isolation sub-layer to form an N-type buried layer;
s3, growing a second isolation sub-layer on the first isolation sub-layer and the N-type buried layer to form an isolation layer;
s4, growing monocrystalline silicon on the Si sheet and the second isolation sub-layer to form an Si substrate;
s5, sequentially preparing an AlN nucleating layer, an AlGaN step-changing layer, a GaN buffer layer and an AlGaN barrier layer on the Si substrate.
In one embodiment of the present invention, the steps between the steps S4 and S5 further comprise the steps of:
and preparing a pre-paved aluminum layer on the Si substrate.
Compared with the prior art, the invention has the beneficial effects that:
according to the high electron mobility transistor, the N-type buried layer and the isolation layer are arranged in the Si substrate, the N-type impurities in the N-type buried layer cannot be completely masked by the isolation layer, and the N-type impurities can diffuse into the Si substrate, so that the P-type channel concentration introduced into the Si substrate by Al diffusion in an upper structure is counteracted, the substrate resistivity is improved, and the radio frequency loss of a device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a Si-based AlGaN/GaN high electron mobility transistor with a buried encapsulation layer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another Si-based AlGaN/GaN high electron mobility transistor with a buried encapsulation layer according to an embodiment of the present invention;
fig. 3a to fig. 3f are schematic process diagrams of a method for manufacturing a Si-based AlGaN/GaN high electron mobility transistor with a buried encapsulation layer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a Si-based AlGaN/GaN high electron mobility transistor with a buried layer according to an embodiment of the present invention.
The AlGaN/GaN high-electron-mobility transistor comprises a Si substrate 1, an AlN nucleation layer 3, an AlGaN graded layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 which are sequentially stacked, wherein an N-type buried layer 11 and an isolation layer 12 are arranged in the Si substrate 1, and the isolation layer 12 is arranged between the Si substrate 1 and the N-type buried layer 11 and wraps the N-type buried layer.
In this embodiment, the N-type buried layer 11 and the isolation layer 12 are both disposed in the Si substrate 1, that is, the isolation layer 12 is wrapped around the N-type buried layer 11, the Si substrate 1 is wrapped around the isolation layer 12, and the following conditions are satisfied by the arrangement of the isolation layer 12: the isolation layer 12 does not completely mask the N-type impurities in the N-type buried layer, and part of the N-type impurities can also diffuse into the Si substrate 1 through the isolation layer 12, so that the N-type impurities diffused into the Si substrate 1 can offset the P-type channel concentration of the Al diffused into the Si substrate 1 in the upper structure, thereby improving the resistivity of the substrate and reducing the radio frequency loss of the device.
Specifically, the material of the Si substrate 1 includes P-type Si (111) with a thickness of 500-900 μm and a size of 2-6 inches and a resistance of more than 6000 Ω -cm, for example, a large-resistance P-type Si sheet with a thickness of 525 μm, 4 inches and a resistance of more than 6000 Ω -cm may be selected as the Si substrate 1.
In the embodiment, the Si sheet with the crystal orientation of 111 is selected, so that the Ga surface can be grown on the substrate, and the quality of the subsequent growth material is ensured.
Specifically, the doping elements of the N-type buried layer 11 include P and As; when the doping element is P, the doping concentration is 10 13 -10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the When the doping element is As, the doping concentration is 10 14 -10 16 cm -3 。
Specifically, the material of the isolation layer 12 includes SiO 2 The thickness is 1.5-2nm.
In this embodiment, the thickness of the isolation layer 12 is too large, which may cause the N-type doping impurities to be completely masked and not enter the Si substrate, while too small may cause too much N-type doping elements to diffuse into the Si substrate, which may cause too much impurities of the Si substrate and lower resistivity. The thickness of the isolation layer is 1.5-2nm, and the isolation layer is thinner, so that N-type doping elements are not completely masked, and the N-type doping elements diffused into the Si substrate can offset a P-type channel introduced by Al diffusion, so that the resistivity of the substrate is improved, and the radio frequency loss of the device is reduced.
Further, the N-type buried layer 11 and the isolation layer 12 may be provided at an intermediate position of the Si substrate 1, may be provided at a left or right position of the Si substrate 1, or may be provided at an upper or oblique position of the Si substrate 1; the specific position setting can be determined according to the doping concentration of the N-type buried layer 11, the thickness of the Si substrate 1, the concentration of Al diffused into the substrate, and the position of the device structure above the substrate in application. Preferably, the N-type buried layer 11 and the isolation layer 12 are provided at an intermediate position of the Si substrate 1. Because Al diffusion is mostly concentrated at a few um on the surface of the substrate, the arrangement of the buried layer and the isolation layer in the middle position can ensure that doped impurities can offset parasitic P-type impurities on the surface of the substrate at a faster speed and a shorter distance.
Further, the N-type buried layer 11 may be located at any position in the isolation layer 12, preferably, the N-type buried layer 11 is disposed at the center of the isolation layer 12, and the thickness of the isolation layer 12 around the N-type buried layer 11 is equal.
In this embodiment, the thicknesses of the isolation layers 12 around the N-type buried layer 11 are all set to be equal, so that the concentrations of the N-type impurities diffused from the isolation layers into the substrate are all equal, thereby ensuring the resistivity of the substrate and improving the performance of the substrate.
In this embodiment, the doping element of the N-type buried layer 11 is As or P, and the material of the isolation layer comprises SiO 2 Due to SiO 2 For a very small diffusion coefficient of P, as, P or As is not completely impermeable to SiO 2 Therefore, siO is used 2 Masking the film so that a small portion of As or P passes through SiO 2 At the same time due to the SiO employed 2 Only 1.5-2nm, which means SiO at this time 2 The masking effect of (2) is greatly inhibited, so that the As impurities are not completely masked in the process; in addition, due to the fact that the deposition temperature of the pre-paved aluminum layer, the low-temperature AlN, the high-temperature AlN and the like is high, the diffusion of P, as impurities in the process is gradually increased, so that the increase of the concentration of a P-type channel introduced by Al diffusion is counteracted under the proper thickness of the isolation layer and the proper doping concentration of N-type impurities, the resistivity of the substrate is improved, and the radio-frequency loss is reduced.
In addition, since no excessive diffusion barrier layer is introduced between the Si substrate and the subsequent layers in the process, the material quality is not affected.
In a specific embodiment, alN nucleation layer 3 includes a first AlN nucleation layer 31 and a second AlN nucleation layer 32, wherein second AlN nucleation layer 32 is located on first AlN nucleation layer 31, and the nucleation temperature of second AlN nucleation layer 32 is greater than the nucleation temperature of first AlN nucleation layer 31.
Specifically, the first AlN nucleation layer 31 is a low-temperature AlN nucleation layer, the nucleation temperature is 895-905 ℃, and the thickness is 20-40nm; the second AlN nucleation layer 32 is a high temperature AlN nucleation layer having a nucleation temperature of 1205-1215 deg.C and a thickness of 160-180nm. For example, the nucleation temperature of the first AlN nucleation layer 31 is 900 ℃ and the thickness is 30nm; the nucleation temperature of the second AlN nucleation layer 32 was 1210℃and the thickness thereof was 170nm.
In a specific embodiment, the AlGaN graded layer 4 includes a first AlGaN layer 41 and a second AlGaN layer 42, wherein the second AlGaN layer 42 is located on the first AlGaN layer 41, and the mass fraction of the Al composition of the second AlGaN layer 42 is greater than the mass fraction of the Al composition of the first AlGaN layer 41.
Specifically, the thickness of the first AlGaN layer 41 is 340-360nm, the mass fraction of Al components is 30-40%, and the growth temperature is 1140-1160 ℃; the thickness of the second AlGaN layer 42 is 390-410nm, the mass fraction of Al component is 70-80%, and the growth temperature is 1145-1155 ℃. For example, the thickness of the first AlGaN layer 41 is 350nm, the Al composition mass fraction is 35%, and the growth temperature is 1150 ℃; the second AlGaN layer 42 has a thickness of 400nm, an Al composition mass fraction of 75%, and a growth temperature of 1150 ℃.
In one embodiment, the GaN buffer layer 5 has a thickness of 900-1100nm and a growth temperature of 1140-1160 ℃; for example, the GaN buffer layer 5 has a thickness of 1000nm and a growth temperature of 1150 ℃. The thickness of the AlGaN barrier layer 6 is 200-300nm, and the growth temperature is 1185-1195 ℃; for example, the AlGaN barrier layer 6 has a thickness of 250nm and a growth temperature of 1190 ℃.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another Si-based AlGaN/GaN high electron mobility transistor with a buried layer according to an embodiment of the present invention.
The high electron mobility transistor includes a Si substrate 1, a pre-clad aluminum layer 2, an AlN nucleation layer 3, an AlGaN graded layer 4, a GaN buffer layer 5, and an AlGaN barrier layer 6, which are laminated in this order.
Specifically, the specific structures of the Si substrate 1, the AlN nucleation layer 3, the AlGaN graded layer 4, the GaN buffer layer 5, and the AlGaN barrier layer 6 are referred to above, and will not be repeated here. The thickness of the pre-paved aluminum layer 2 is less than 10nm, and the growth temperature is 1080-1090 ℃; for example, the thickness of the pre-applied aluminum layer 2 is 5nm and the growth temperature is 1085 ℃.
According to the embodiment, the pre-paved aluminum layer is arranged between the Si substrate and the AlN nucleation layer, so that the growth effect of the nucleation layer can be improved, the crystal quality of GaN can be improved, and the performance of the high electron mobility transistor can be further improved.
In the embodiment, the N-type buried layer and the isolation layer are arranged in the Si substrate, the N-type impurities in the N-type buried layer cannot be completely masked by the isolation layer, and the N-type impurities can enter the Si substrate through diffusion of the isolation layer, so that P-type channel concentration of the Si substrate introduced by Al diffusion in an upper structure is counteracted, the resistivity of the substrate is improved, and the radio frequency loss of a device is reduced.
Example two
On the basis of the first embodiment, please refer to fig. 3 a-3 f, fig. 3 a-3 f are schematic process diagrams of a preparation method of a Si-based AlGaN/GaN high electron mobility transistor with a buried encapsulation layer according to an embodiment of the invention, the preparation method includes the steps of:
s1, a first isolation sub-layer 121 is prepared in the Si sheet 13, see fig. 3a and 3b.
Firstly, the Si sheet 13 is soaked in 20% HF acid solution for 60s, and then H is used 2 O 2 Alcohol and acetone rinse, and finally rinse with flowing deionized water for 60s.
Then, placing the cleaned substrate into a low-pressure MOCVD reaction chamber, introducing hydrogen, raising the temperature to 950-1010 ℃, controlling the pressure of the reaction chamber to 40Torr, and carrying out heat treatment on the substrate for 3min under the hydrogen atmosphere.
And then, after the heat cleaning stage is finished, the temperature of the reaction chamber is reduced to the room temperature, the Si sheet 13 is taken out, photoresist is smeared on the surface of the Si sheet 13, an etching window is photoetched, and then a groove is etched in the Si sheet 13 through the etching window.
Finally, LPCVD is used to deposit SiO with thickness of 1.5-2nm in the groove 2 As the first isolation sublayer 121 and removing the photoresist, wherein the deposition conditions are: TEOS tetraethoxysilane is used as a source, the temperature is 680-750 ℃ and the time is 19-24s. In one embodiment, the first isolation sublayer 121 is deposited at a temperature of 700℃for a period of 19s and a thickness of 1.6nm.
S2, performing ion implantation on the surface layer of the first isolation sub-layer 121 to form an N-type buried layer 11, see FIG. 3c.
First, inCoating photoresist on the surface of the first isolation sub-layer 121 and photoetching an injection window; then, ion implantation is performed in the surface layer of the first isolation sublayer 121 through the implantation window using As or P As an impurity for N-type doping, and when the doping element is P, the doping concentration is 10 13 -10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the When the doping element is As, the doping concentration is 10 14 -10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Finally, the photoresist is removed.
S3, a second isolation sub-layer 122 is grown on the first isolation sub-layer 121 and the N-type buried layer 11 to form an isolation layer 12, see FIG. 3d.
Firstly, coating photoresist on the first isolation sub-layer 121 and the N-type buried layer 11 and photoetching a growth window; then, siO with the thickness of 1.5-2nm is deposited on the first isolation sub-layer 121 and the N-type buried layer 11 through a growth window 2 Forming a second isolation sub-layer 122; the first isolation sub-layer 121 and the second isolation sub-layer 122 together form an isolation layer 12, and the thickness of the isolation layer 12 is equal to the thickness of the groove formed by etching in the step S1; finally, the photoresist is removed.
In one embodiment, the thickness of the second isolation sublayer 122 is 1.6nm.
Preferably, the width of the first isolation sub-layer 121 at two sides of the N-type buried layer 11, the thickness of the first isolation sub-layer 121 at the bottom of the N-type buried layer 11 and the thickness of the second isolation sub-layer 122 are all equal, that is, the N-type buried layer 11 is located at the center of the isolation layer 12, and the thickness of the isolation layer 12 around the N-type buried layer 11 is all equal and is 1.5-2nm.
In this embodiment, the thicknesses of the isolation layers 12 around the N-type buried layer 11 are all set to be equal, so that the concentrations of the N-type impurities diffused from the isolation layers into the substrate are all equal, thereby ensuring the resistivity of the substrate and improving the performance of the substrate.
S4, growing monocrystalline silicon 14 on the Si sheet 13 and the second isolation sub-layer 122 to form the Si substrate 1, see fig. 3e.
Specifically, siH is used 4 As a source, single crystal silicon 14 1-2 μm thick was epitaxially grown on the Si sheet 13, the second isolation sublayer 122 by MOCVD, thereby forming the Si substrate 1.
It is understood that the Si substrate 1 is formed of a Si sheet 13 and single crystal silicon 14, a first isolation sublayer 121 and a second isolation sublayer 122 are formed in the Si sheet 13, the first isolation sublayer 121 and the second isolation sublayer 122 together form an isolation layer 12, and an N-type buried layer 11 is formed in the first isolation sublayer 121.
S5, an AlN nucleation layer 3, an AlGaN graded layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 are sequentially prepared on the Si substrate 1, see FIG. 3f.
S51, the first AlN nucleation layer 31 is epitaxially grown on the Si substrate 1.
Specifically, by using the MOCVD method, trimethylaluminum (TMAL) and NH are simultaneously opened 3 The gas path is used for adjusting the TMAL flow to 240-260sccm and NH 3 The low-temperature AlN nucleating layer with the flow rate of 3800-4200sccm, the growth temperature of 895-905 ℃ and the growth time of 60min is grown to be 20-40nm thick, and the first AlN nucleating layer 31 is formed.
In one embodiment, the growth conditions of the first AlN nucleation layer 31 are: TMAL flow is 260sccm, NH 3 The flow rate was 4000sccm, the growth temperature was 900 ℃, the growth time was 60 minutes, and the thickness of the first AlN nucleation layer 31 formed was 30nm.
S52, epitaxially growing the second AlN nucleation layer 32 on the first AlN nucleation layer 31.
Specifically, the temperature of the reaction chamber is raised to 1200-1220 ℃, the TMAL flow is adjusted to 190-200sccm, the ammonia flow is adjusted to 1350-1650sccm, and a nucleation layer of high-temperature AlN with a thickness of 160-180nm is grown to form a second AlN nucleation layer 32.
In one particular embodiment, the growth conditions for second AlN nucleation layer 32 are: TMAL flow is 190sccm, NH 3 The flow rate was 1400sccm, the growth temperature was 1210 ℃, and the thickness of the second AlN nucleation layer 32 was 170nm.
S53, the first AlGaN layer 41 is prepared on the second AlN nucleation layer 32.
Specifically, the temperature of the reaction chamber is reduced to 1140-1160 ℃, and TMAL, trimethylgallium (TMGa) and NH are adjusted 3 AlGaN with the flow rate of 190-200sccm, 10sccm and 2650-3250sccm respectively grows to be 340-360nm thick to form the first AlGaN layer 41.
In one embodimentIn the example, the growth condition of the first AlGaN layer 41 is that the reaction chamber temperature is 1150 ℃ and TMAl, TMGa, NH 3 The flow rates were 190sccm, 10sccm, and 2700sccm, respectively, and the thickness of the grown first AlGaN layer 41 was 350nm.
S54, the second AlGaN layer 42 is prepared on the first AlGaN layer 41.
Specifically, the temperature of the reaction chamber is kept between 1140 and 1160 ℃, and TMAl, TMGa, NH is adjusted 3 AlGaN with the flow rate of 160-170sccm, 20sccm, 2920sccm-3580sccm and the thickness of 390-410nm is grown to form the second AlGaN layer 42.
In one embodiment, the growth conditions of the second AlGaN layer 42 are: the temperature of the reaction chamber is 1150 ℃ and TMAl, TMGa, NH 3 The flow rates were 162sccm, 20sccm, and 3000sccm, respectively, and the thickness of the grown second AlGaN layer 42 was 400nm.
S55, a GaN buffer layer 5 is prepared on the second AlGaN layer 42.
Specifically, the temperature of the reaction chamber is kept unchanged, a TMAL source is closed, and TMGa and NH are adjusted 3 And (3) continuously epitaxially growing a GaN layer with the thickness of 900-1100nm to form the GaN buffer layer 5, wherein the flow rates are respectively 190-200sccm and 8800-10100 sccm.
In one specific embodiment, the growth conditions of GaN buffer layer 5 are: the temperature of the reaction chamber is 1150 ℃, the TMGa flow is 192sccm, and NH 3 The flow rate was 9000sccm, and the thickness of the GaN buffer layer 5 formed was 1. Mu.m.
S56, an AlGaN barrier layer 6 is prepared on the GaN buffer layer 5.
Specifically, the temperature of the reaction chamber was raised to 1190℃and the TMAL source was turned on, at which time TMAl, TMGa, NH was adjusted 3 And depositing an AlGaN layer with the flow rate of 70-90sccm, 35-50sccm and 10000-24000sccm respectively to form an AlGaN barrier layer 6.
In one embodiment, alGaN barrier layer 6 is grown under conditions such that the reaction chamber temperature is 1190 ℃, TMAL flow is 80sccm, TMGa flow is 43sccm, NH 3 The flux was 20000sccm, and the thickness of the AlGaN barrier layer 6 was 250nm.
In this embodiment, the first isolation sub-layer, the N-type buried layer, and the second isolation sub-layer are sequentially prepared in the Si sheet, and single crystal silicon is continuously grown, so that the N-type buried layer and the isolation layer are formed in the Si substrate, and meanwhile, the isolation layer does not completely mask the N-type impurity in the N-type buried layer, and the N-type impurity can diffuse into the Si substrate through the isolation layer, so that the P-type channel concentration of the Si substrate introduced by Al diffusion in the upper structure is offset, the substrate resistivity is improved, and the radio frequency loss of the device is reduced.
Example III
On the basis of the second embodiment, please refer to fig. 2, another method for preparing a Si-based AlGaN/GaN high electron mobility transistor with a buried encapsulation layer is provided in this embodiment, which includes the steps of:
s1, preparing a first isolation sub-layer 121 in the Si sheet 13.
S2, performing ion implantation on the surface layer of the first isolation sub-layer 121 to form an N-type buried layer 11.
And S3, growing a second isolation sub-layer 122 on the first isolation sub-layer 121 and the N-type buried layer 11 to form an isolation layer 12.
And S4, growing monocrystalline silicon 14 on the Si sheet 13 and the second isolation sub-layer 122 to form the Si substrate 1.
S5, preparing a pre-paved aluminum layer 2 on the Si substrate 1.
Specifically, the temperature of the reaction chamber is increased to 1080-1090 ℃, a TMAL gas path is opened, the TMAL flow is adjusted to 10-30sccm, the preparation of the pre-paved aluminum layer 2 is carried out, and the thickness of the formed pre-paved aluminum layer 2 is smaller than 10nm.
In one embodiment, the preparation condition of the pre-laid aluminum layer 2 is that the reaction chamber temperature is 1085 ℃ and the TMAl flow is 20sccm.
S6, sequentially preparing an AlN nucleation layer 3, an AlGaN step-changing layer 4, a GaN buffer layer 5 and an AlGaN barrier layer 6 on the pre-paved aluminum layer 2.
For the implementation of steps S1 to S4 and S6, please refer to embodiment two, and the description of this embodiment is omitted. The structure of the device thus obtained is shown in fig. 2.
According to the embodiment, the pre-paved aluminum layer is arranged between the Si substrate and the AlN nucleation layer, so that the growth effect of the nucleation layer can be improved, the crystal quality of GaN can be improved, and the performance of the high electron mobility transistor can be further improved.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A Si-based AlGaN/GaN high electron mobility transistor with a wrapping buried layer is characterized by comprising a Si substrate (1), an AlN nucleation layer (3), an AlGaN graded layer (4), a GaN buffer layer (5) and an AlGaN barrier layer (6) which are sequentially stacked, wherein,
be provided with N type buried layer (11) and isolation layer (12) in Si substrate (1), isolation layer (12) set up Si substrate (1) with between N type buried layer (11) and wrap up around N type buried layer (11) package around isolation layer (12) Si substrate (1), part N type impurity in N type buried layer (11) can pass through isolation layer (12) diffusion get into in Si substrate (1) in order to offset the Al diffusion get into in the superstructure P type channel concentration of Si substrate (1).
2. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 1, wherein the doping elements of said N-type buried layer (11) comprise P and As; when the doping element is P, the doping concentration is 10 13 -10 14 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the When the doping element is As, the doping concentration is 10 14 -10 16 cm -3 。
3. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 1, characterised in that the material of the spacer layer (12) comprises SiO 2 The thickness is 1.5-2nm.
4. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 1, wherein the thickness of said isolation layer (12) around said N-type buried layer (11) is equal.
5. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 1, wherein said AlN nucleation layer (3) comprises a first AlN nucleation layer (31) and a second AlN nucleation layer (32), wherein said second AlN nucleation layer (32) is located on said first AlN nucleation layer (31), the nucleation temperature of said second AlN nucleation layer (32) being greater than the nucleation temperature of said first AlN nucleation layer (31).
6. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 1, wherein said AlGaN graded layer (4) comprises a first AlGaN layer (41) and a second AlGaN layer (42), wherein said second AlGaN layer (42) is located on said first AlGaN layer (41), and wherein the Al composition mass fraction of said second AlGaN layer (42) is larger than the Al composition mass fraction of said first AlGaN layer (41).
7. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 1, further comprising a pre-clad aluminium layer (2), wherein said pre-clad aluminium layer (2) is located between said Si substrate (1) and said AlN nucleation layer (3).
8. The Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 7, wherein the thickness of said pre-clad aluminium layer (2) is less than 10nm.
9. The preparation method of the Si-based AlGaN/GaN high electron mobility transistor with the wrapping buried layer is characterized by comprising the following steps:
s1, preparing a first isolation sub-layer (121) in a Si sheet (13);
s2, performing ion implantation on the middle part of the surface layer of the first isolation sub-layer (121) to form an N-type buried layer (11);
s3, growing a second isolation sub-layer (122) on the first isolation sub-layer (121) and the N-type buried layer (11) to form an isolation layer (12);
s4, growing monocrystalline silicon (14) on the Si sheet (13) and the second isolation sub-layer (122) to form an Si substrate (1), wherein the isolation layer (12) is wrapped around the N-type buried layer (11), and the Si substrate (1) is wrapped around the isolation layer (12);
s5, sequentially preparing an AlN nucleation layer (3), an AlGaN step-changing layer (4), a GaN buffer layer (5) and an AlGaN barrier layer (6) on the Si substrate (1); part of N-type impurities in the N-type buried layer (11) can diffuse into the Si substrate (1) through the isolation layer (12) so as to offset the concentration of P-type channels of Al diffused into the Si substrate (1) in the upper layer structure.
10. The method for manufacturing a Si-based AlGaN/GaN high electron mobility transistor with buried layer according to claim 9, further comprising the step of between steps S4 and S5:
a pre-applied aluminum layer (2) is produced on the Si substrate (1).
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