CN115084298B - CMOS image sensor and preparation method thereof - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 5
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- 239000004065 semiconductor Substances 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007429 general method Methods 0.000 description 2
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- 238000005468 ion implantation Methods 0.000 description 2
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H01L27/144—Devices controlled by radiation
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- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
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Abstract
The invention discloses a CMOS image sensor and a preparation method thereof, relating to the technical field of photoelectric detection; including clamp photodiodes and transfer transistors; the clamping photodiode comprises a P-type epitaxial layer and a plurality of pixel units, wherein each pixel unit comprises an N-type buried layer, a P-type clamping layer and a P-type buried layer; the P-type buried layers are wrapped in the plurality of N-type buried layers, and the P-type clamping layer is formed above the N-type buried layers; the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer and carries out structural improvement based on a traditional PPD pixel structure, the P-type buried layer is isolated by wrapping the P-type buried layer by a plurality of N-type buried layers, the depletion region width of the photodiode is increased, PN junction capacitance is improved, the quantum efficiency and the full-well capacity of a pixel unit are improved, and the P-type buried layer distributed in the N-type buried layer enables the N-type buried layer to be depleted more easily before exposure, so that reset noise is reduced.
Description
Technical Field
The invention relates to the technical field of photoelectric detection, in particular to a CMOS image sensor and a preparation method thereof.
Background
With the continuous development of CMOS process technology and the demand of high-resolution imaging systems proposed by users, the smaller and smaller pixel size of CMOS image sensors has become a new trend. However, the reduction in the pixel size means the reduction in the size of the photosensitive cell, thereby limiting the photoelectric conversion efficiency of PPD, ultimately resulting in deterioration of CMOS image sensor performance such as quantum efficiency and the like.
Therefore, in order to accommodate the small-sized pixels, it is one of the current research directions to improve the pixel structure, thereby obtaining CMOS image sensors having high quantum efficiency.
In order to increase the quantum efficiency of the CMOS image sensor, it is generally adopted to increase the depletion region width of the clamp photodiode as much as possible. There are two general methods to increase the width of the depletion region, one is to increase the gate voltage of the transfer transistor, but an excessive voltage causes inter-band tunneling leakage, which is equivalent to increasing dark current, and this voltage is difficult to generate by peripheral circuits; another is to increase the junction depth of the N-type buried layer in the clamp photodiode, this method needs to increase the energy of ion implantation to form the N-type buried layer, however, high energy implantation not only causes the peak of doping concentration of the N-type buried layer in the clamp photodiode to be far away from the transmission transistor, making photo-generated electrons difficult to transfer, but also causes free electrons in the depletion region to be difficult to be depleted, both structures are unfavorable for charge transfer of the pixel, and serious image tailing problem can be caused.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: in order to increase the quantum efficiency of the CMOS image sensor, the traditional CMOS structure is not beneficial to charge transfer of pixels, and serious image tailing problem can be caused; the invention aims to provide a CMOS image sensor and a preparation method thereof, and simultaneously solves the problems of quantum efficiency and image tailing of the CMOS image sensor.
The invention is realized by the following technical scheme:
the scheme provides a CMOS image sensor, which comprises a clamping photodiode and a transfer transistor which are positioned on a substrate;
the clamp photodiode includes a P-type epitaxial layer and a plurality of pixel cells including: an N-type buried layer, a P-type clamping layer and a P-type buried layer;
the P-type buried layer is formed by overlapping and distributing at least two P-type buried sub-layers, a plurality of N-type buried layers wrap the P-type buried layers, and a P-type clamping layer is formed above the N-type buried layers;
the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer.
The working principle of the scheme is as follows: to increase the quantum efficiency of CMOS image sensors, conventional CMOS structures increase the gate voltage of the transfer transistor, but excessive voltages can cause inter-band tunneling leakage; the other is that by increasing the junction depth of the N-type buried layer in the clamping photodiode, the method can make photo-generated electrons difficult to transfer, and can also make free electrons in a depletion region difficult to be depleted, and both schemes are unfavorable for the charge transfer of the pixel and can cause serious image tailing problem; the scheme provides a CMOS image sensor, carry out structural improvement based on traditional PPD pixel structure, wrap up P type buried layer in with P type buried layer isolation through a plurality of N type buried layers, increased photodiode's depletion region width, thereby improved PN junction capacitance, make the quantum efficiency and the full well capacity of pixel unit improve, the P type buried layer of distribution inside N type buried layer makes N type buried layer more be used up before exposing, reduce reset noise.
The further optimization scheme is that at least two P-type buried sub-layers are longitudinally overlapped and distributed to form a P-type buried layer, and the N-type buried layer is wrapped around the P-type buried layer.
The N-type buried layer comprises at least one transverse N-type buried layer and at least four longitudinal N-type buried layers, wherein the longitudinal N-type buried layers are distributed around the P-type buried layer, and the transverse N-type buried layers are distributed on the right side of the longitudinal N-type buried layers. The vertically distributed buried N layer increases charge transfer efficiency.
The further optimization scheme is that the section formed by the P-type buried layer is rectangular, the section formed by the P-type buried layer and the longitudinal N-type buried layer is rectangular, and the section formed by the P-type clamping layer, the N-type buried layer and the P-type buried layer is rectangular.
The cross sections of the N-type buried layer and the P-type buried layer are distributed in a shape of a Chinese character 'Hui', an N-type buried layer is vertically distributed on the right side of a pixel distributed in a shape of a Chinese character 'Hui', the width of a depletion region of a photodiode is increased by pixel units distributed in a shape of a Chinese character 'Hui', so that PN junction capacitance is improved, quantum efficiency and full well capacity of the pixel units are improved, the N-type buried layer is more easily depleted before exposure by the P-type buried layer distributed in a shape of the Chinese character 'Hui', and reset noise is reduced; the vertically distributed buried N layer increases charge transfer efficiency.
In addition, the fifth N-type buried sub-layer can further improve the quantum efficiency and the full-well capacity of the clamping photodiode.
The doping concentration of the P-type buried layer is larger than that of the P-type epitaxial layer;
the doping concentration of the P-type clamping layer is larger than that of the P-type buried layer;
the doping concentration of the transverse N-type buried sub-layer is larger than that of the longitudinal N-type buried sub-layer;
the doping concentration of the longitudinal N-type buried layer positioned at the top of the P-type buried layer is larger than that of the longitudinal N-type buried layers positioned at two sides of the P-type buried layer;
the doping concentration of the longitudinal N-type buried layers positioned at two sides of the P-type buried layer is equal;
the doping concentration of the longitudinal N-type buried layer positioned at the two sides of the P-type buried layer is larger than that of the longitudinal N-type buried layer positioned at the bottom of the P-type buried layer.
The further optimization scheme is that the doping concentration of the P-type clamping layer and the P-type buried layer is 1.0 x 10 11 cm -3 ～9.0*10 12 cm -3 ；
The doping concentration of the transverse N-type buried layer and the longitudinal N-type buried layer is 1.0 x 10 11 cm -3 ～1.0*10 13 cm -3 。
The N buried layer in the shape of the Chinese character 'Hui' increases the junction depth of the N buried layer of the clamping transistor diode, so that the photo-generated electrons in the clamping photodiode can be absorbed more effectively; the doping concentration of the longitudinal N-type buried sub-layer is higher than that of other N-type buried sub-layers, so that photo-generated electrons generated in the reverse-U-shaped region can obtain larger potential, and the electron potential barrier of the photo-generated electrons on the transmission path is eliminated.
The further optimization scheme is that the semiconductor device further comprises a gate dielectric layer and an isolation structure, the bottom of the P-type epitaxial layer is arranged on the substrate, the isolation structure surrounds two sides of the P-type epitaxial layer, and the gate dielectric layer covers the top of the P-type epitaxial layer and the top of the isolation structure.
In a further preferred embodiment, the transfer transistor includes: the clamping photodiode is connected with the source electrode of the transfer transistor.
The further optimization scheme is that a floating node is arranged at the joint of the gate dielectric layer and the isolation structure. The floating node is used for collecting photoelectrons generated by the clamping photodiode.
The scheme also provides a method for preparing the CMOS image sensor, which comprises the following steps:
step one: providing a P-type doped substrate;
step two: forming a clamp photodiode and a transfer transistor on a P-type doped substrate; the clamp photodiode includes a P-type epitaxial layer and a plurality of pixel cells including: an N-type buried layer, a P-type clamping layer and a P-type buried layer; the P-type buried layer is formed by overlapping and distributing at least two P-type buried sub-layers, a plurality of N-type buried layers wrap the P-type buried layers, and a P-type clamping layer is formed above the N-type buried layers; the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer;
step three: the transfer transistor is connected with the clamping photodiode, the transfer transistor comprises a gate, a drain and a source, and the source of the transfer transistor is connected with the clamping photodiode for controlling transmission of the detection signal.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the CMOS image sensor provided by the invention is structurally improved based on the traditional PPD pixel structure, the P-type buried layer is wrapped by the N-type buried layers to isolate the P-type buried layer, the depletion region width of the photodiode is increased, the PN junction capacitance is increased, the quantum efficiency and the full well capacity of a pixel unit are improved, the P-type buried layer distributed in the N-type buried layer is more easily depleted before exposure, and the reset noise is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a schematic diagram of a conventional PPD pixel structure;
fig. 2 is a schematic diagram of a CMOS image sensor.
In the drawings, the reference numerals and corresponding part names:
the semiconductor device comprises a 1-gate dielectric layer, a 2-transfer transistor, a 3-floating node, a 4-P type substrate, a 5-P type epitaxial layer, a 6-isolation structure, a 7-P type clamping layer, an 8-first N-type buried layer, a 9-second N-type buried layer, a 10-fourth N-type buried layer, an 11-fifth N-type buried layer, a 12-first P-type buried layer and a 13-second P-type buried layer.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
The conventional PPD pixel structure is shown in fig. 1, and the P-type clamping layer is directly located on the surface of the N-type buried layer, so that in order to increase the quantum efficiency of the CMOS image sensor, a method is generally adopted to increase the width of the depletion region of the clamping photodiode as much as possible. There are two general methods to increase the width of the depletion region, one is to increase the gate voltage of the transfer transistor, but an excessive voltage causes inter-band tunneling leakage, which is equivalent to increasing dark current, and this voltage is difficult to generate by peripheral circuits; another is to increase the junction depth of the N-type buried layer in the clamp photodiode, this method needs to increase the energy of ion implantation to form the N-type buried layer, however, high energy implantation not only causes the peak of doping concentration of the N-type buried layer in the clamp photodiode to be far away from the transmission transistor, making photo-generated electrons difficult to transfer, but also causes free electrons in the depletion region to be difficult to be depleted, both structures are unfavorable for charge transfer of the pixel, and serious image tailing problem can be caused.
In order to solve the above problems, the present invention provides the following embodiments:
example 1
The embodiment provides a CMOS image sensor, which comprises a clamping photodiode and a transfer transistor which are positioned on a substrate;
the clamp photodiode includes a P-type epitaxial layer and a plurality of pixel cells including: an N-type buried layer, a P-type clamping layer and a P-type buried layer;
the P-type buried layer is formed by overlapping and distributing at least two P-type buried sub-layers, a plurality of N-type buried layers wrap the P-type buried layers, and a P-type clamping layer is formed above the N-type buried layers;
the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer.
At least two P type buried layers are longitudinally overlapped and distributed to form a P type buried layer, and the N type buried layer is wrapped around the P type buried layer.
The N-type buried layer comprises at least one transverse N-type buried layer and at least four longitudinal N-type buried layers, wherein the longitudinal N-type buried layers are distributed around the P-type buried layer, and the transverse N-type buried layers are distributed on the right side of the longitudinal N-type buried layers.
The cross section that P type buried layer formed is the rectangle, and the cross section that P type buried layer and vertical N type buried layer formed is the rectangle, and the cross section that P type clamp layer, N type buried layer and P type buried layer formed is the rectangle.
In this embodiment, the N-type buried layer includes four longitudinal N-type buried sub-layers and one lateral N-type buried sub-layer, the four longitudinal N-type buried sub-layers are distributed along the longitudinal direction of the P-type epitaxial layer, and the one lateral N-type buried sub-layer is distributed along the right sides of the at least four longitudinal N-type buried sub-layers.
The transverse N-type buried sub-layer comprises a first N-type buried sub-layer, a second N-type buried sub-layer, a third N-type buried sub-layer and a fourth N-type buried sub-layer; the vertical N-type buried layer is a fifth N-type buried layer, the P-type buried layer comprises a first P-type buried layer and a second P-type buried layer, the first P-type buried layer and the second P-type buried layer are positioned in the middle of the first N-type buried layer, the second N-type buried layer, the third N-type buried layer and the fourth N-type buried layer and are in a shape of a Chinese character 'Hui', and the first P-type buried layer is positioned above the second P-type buried layer.
The doping concentration of the P-type buried layer is larger than that of the P-type epitaxial layer;
the doping concentration of the P-type clamping layer is larger than that of the P-type buried layer;
the doping concentration of the transverse N-type buried sub-layer is larger than that of the longitudinal N-type buried sub-layer;
the doping concentration of the longitudinal N-type buried layer positioned at the top of the P-type buried layer is larger than that of the longitudinal N-type buried layers positioned at two sides of the P-type buried layer;
the doping concentration of the longitudinal N-type buried layers positioned at two sides of the P-type buried layer is equal;
the doping concentration of the longitudinal N-type buried layer positioned at the two sides of the P-type buried layer is larger than that of the longitudinal N-type buried layer positioned at the bottom of the P-type buried layer.
The doping concentration of the P-type clamping layer and the P-type buried layer is 1.0X101 cm -3 ～9.0*10 12 cm -3 ；
The doping concentration of the transverse N-type buried layer and the longitudinal N-type buried layer is 1.0 x 1011cm -3 ～1.0*10 13 cm -3 。
The semiconductor device further comprises a gate dielectric layer and an isolation structure, wherein the bottom of the P-type epitaxial layer is arranged on the substrate, the isolation structure surrounds two sides of the P-type epitaxial layer, and the gate dielectric layer covers the top of the P-type epitaxial layer and the isolation structure; wherein the gate dielectric layer is made of silicon oxide.
The transfer transistor includes: the clamping photodiode is connected with the source electrode of the transfer transistor.
And a floating node is arranged at the joint of the gate dielectric layer and the isolation structure.
The P-type silicon substrate used in the above structure can be changed to clamp the structure of the photodiode to form a new device when the substrate is selected from silicon substrates of other doping types or other materials in practical application.
Example 2
The present embodiment provides a method for manufacturing the CMOS image sensor according to the previous embodiment, including the steps of:
step one: providing a P-type doped substrate;
step two: forming a clamp photodiode and a transfer transistor on a P-type doped substrate; the clamp photodiode includes a P-type epitaxial layer and a plurality of pixel cells including: an N-type buried layer, a P-type clamping layer and a P-type buried layer; the P-type buried layer is formed by overlapping and distributing at least two P-type buried sub-layers, a plurality of N-type buried layers wrap the P-type buried layers, and a P-type clamping layer is formed above the N-type buried layers; the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer;
step three: a transfer transistor is connected with the clamp photodiode, the transfer transistor including a gate, a drain, and a source, and the source of the transfer transistor is connected with the clamp photodiode.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (7)
1. A CMOS image sensor comprising a clamp photodiode and a transfer transistor on a substrate;
the clamp photodiode includes a P-type epitaxial layer and a plurality of pixel cells including: an N-type buried layer, a P-type clamping layer and a P-type buried layer;
the P-type buried layer is formed by overlapping and distributing at least two P-type buried sub-layers, a plurality of N-type buried layers wrap the P-type buried layers, and a P-type clamping layer is formed above the N-type buried layers;
the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer;
at least two P-type buried layers are longitudinally overlapped and distributed to form a P-type buried layer, and the N-type buried layer is wrapped around the P-type buried layer;
the N-type buried layer comprises at least one transverse N-type buried layer and at least four longitudinal N-type buried layers, the longitudinal N-type buried layers are distributed along the periphery of the P-type buried layer, and the transverse N-type buried layers are distributed on the right side of the longitudinal N-type buried layers;
the cross section that P type buried layer formed is the rectangle, and the cross section that P type buried layer and vertical N type buried layer formed is the rectangle, and the cross section that P type clamp layer, N type buried layer and P type buried layer formed is the rectangle.
2. A CMOS image sensor as claimed in claim 1, wherein,
the doping concentration of the P-type buried layer is larger than that of the P-type epitaxial layer;
the doping concentration of the P-type clamping layer is larger than that of the P-type buried layer;
the doping concentration of the transverse N-type buried sub-layer is larger than that of the longitudinal N-type buried sub-layer;
the doping concentration of the longitudinal N-type buried layer positioned at the top of the P-type buried layer is larger than that of the longitudinal N-type buried layers positioned at two sides of the P-type buried layer;
the doping concentration of the longitudinal N-type buried layers positioned at two sides of the P-type buried layer is equal;
the doping concentration of the longitudinal N-type buried layer positioned at the two sides of the P-type buried layer is larger than that of the longitudinal N-type buried layer positioned at the bottom of the P-type buried layer.
3. The CMOS image sensor of claim 2, wherein the P-clamp layer and the P-buried layer have a doping concentration of 1.0 x 10 11 cm -3 ~9.0×10 12 cm -3 ；
The doping concentration of the transverse N-type buried layer and the longitudinal N-type buried layer is 1.0x10 11 cm -3 ~1.0×10 13 cm -3 。
4. The CMOS image sensor of claim 1, further comprising a gate dielectric layer and an isolation structure, wherein the bottom of the P-type epitaxial layer is disposed on the substrate, the isolation structure surrounds the P-type epitaxial layer on both sides, and the gate dielectric layer covers the top of the P-type epitaxial layer and the isolation structure.
5. The CMOS image sensor according to claim 1, wherein the transfer transistor comprises: the clamping photodiode is connected with the source electrode of the transfer transistor.
6. The CMOS image sensor of claim 4, wherein a floating node is provided at a junction of the gate dielectric layer and the isolation structure.
7. A method of fabricating the CMOS image sensor of any one of claims 1-6, comprising the steps of:
step one: providing a P-type doped substrate;
step two: forming a clamping photodiode and a transfer transistor on the P-type doped substrate; the clamp photodiode includes a P-type epitaxial layer and a plurality of pixel cells including: an N-type buried layer, a P-type clamping layer and a P-type buried layer; the P-type buried layer is formed by overlapping and distributing at least two P-type buried sub-layers, a plurality of N-type buried layers wrap the P-type buried layers, and a P-type clamping layer is formed above the N-type buried layers; the P-type epitaxial layer wraps the P-type clamping layer and the N-type buried layer;
step three: a transfer transistor is connected with the clamp photodiode, the transfer transistor including a gate, a drain, and a source, and the source of the transfer transistor is connected with the clamp photodiode.
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