CN113903842A - Flip-chip light emitting diode and light emitting device - Google Patents

Flip-chip light emitting diode and light emitting device Download PDF

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Publication number
CN113903842A
CN113903842A CN202111123260.4A CN202111123260A CN113903842A CN 113903842 A CN113903842 A CN 113903842A CN 202111123260 A CN202111123260 A CN 202111123260A CN 113903842 A CN113903842 A CN 113903842A
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layer
light emitting
emitting diode
flip
width
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CN113903842B (en
Inventor
洪灵愿
夏章艮
黄敏
刘鹏
何敏游
陈功
张中英
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Priority to CN202211514280.9A priority Critical patent/CN115832143A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Abstract

The application discloses a flip-chip light emitting diode and a light emitting device, which comprise a semiconductor stacking layer consisting of a first semiconductor layer, an active layer and a second semiconductor layer, wherein the semiconductor stacking layer is provided with a table top exposing the first semiconductor layer; the conductive protective layer is formed on the table-board; the insulating layer covers the table top and the conductive protective layer; the insulating layer is provided with a first through hole with a width D1Less than the width D of the conductive protective layer2(ii) a The first pad electrode is formed in the first via hole and connected to the conductive protective layer. This application is through addding electrically conductive protective layer in the below of first through-hole to avoid the surface of first semiconductor layer to receive the damage or form high resistance material in the formation of first through-hole, and then improveFlip-chip leds are prone to voltage increases.

Description

Flip-chip light emitting diode and light emitting device
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a flip chip light emitting diode and a light emitting device.
Background
The flip-chip light emitting diode has the characteristics of high light emitting efficiency, energy conservation, environmental protection and long service life, and is widely applied to various fields such as illumination and backlight. Compared with other display technologies popular in the industry at present, the small-size flip-chip light-emitting diode backlight technology has the greatest advantages that the technology has no scientific problem in materials, and is most easy to be produced in mass and put into the market at the fastest speed.
Fig. 1 is a schematic structural diagram of a conventional flip-chip light emitting diode, in a manufacturing process of the conventional flip-chip light emitting diode, a thick metal layer is formed on a semiconductor stack layer 20 as a contact electrode 30, the contact electrode 30 does not completely cover the semiconductor stack layer 20, and a step structure is formed on the semiconductor stack layer 20; when the insulating layer 40 is formed subsequently, because the thickness of the step structure is thick, the insulating layer 40 has a corner above the step structure, so that the surface of the insulating layer 40 is uneven; when the pad electrode 50 is continuously formed on the insulating layer 40, the surface of the pad electrode 50 may also be uneven, so that the coverage of the pad electrode 50 is poor and the risk of fracture is easily caused. Due to poor coverage of the pad electrode 50, poor die bonding may be caused in the subsequent die bonding process, or the pad electrode 50 may be broken, which affects the reliability of the flip-chip light emitting diode.
The conventional method for solving the above problems is: the contact electrode 30 is removed. However, when the first via hole for forming the first pad electrode 51 is subsequently etched in the insulating layer 40, the etching medium may damage the surface of the N-type semiconductor layer 21 and form a high-resistance substance, so that the voltage of the flip-chip light emitting diode is increased, which may affect the performance of the flip-chip light emitting diode.
Disclosure of Invention
An object of this application is to provide a flip-chip emitting diode, it is through addding electrically conductive protective layer in the below of first through-hole to avoid the surface of first semiconductor layer to receive the damage or form high resistance material in the formation process of first through-hole, and then improve flip-chip emitting diode and easily appear the phenomenon that the voltage rose.
Another object is to provide a light emitting device, which employs the above flip-chip light emitting diode.
In a first aspect, the present application provides a flip chip light emitting diode comprising:
the semiconductor device comprises a semiconductor stack layer, a first semiconductor layer, a second semiconductor layer and an active layer positioned between the first semiconductor layer and the second semiconductor layer; the semiconductor stacking layer is provided with a table top exposing the first semiconductor layer;
a conductive protection layer formed on the mesa;
an insulating layer covering the mesa and the conductive protection layer; the insulating layer is provided with a first through hole with a width D1Less than the width D of the conductive protective layer2；
And a first pad electrode formed in the first via hole and connected to the conductive protective layer.
In a possible embodiment, the conductive protection layer further includes a first groove extending from the upper surface of the conductive protection layer to the inside thereof, and the depth of the first groove is 1% to 30% of the thickness of the conductive protection layer.
In a possible implementation, the first groove is located below the first through hole, and the width of the first groove is smaller than or equal to the width of the first through hole.
In one possible embodiment, the top opening width of the first groove is greater than the bottom opening width of the first groove.
In a possible embodiment, the depth of the first groove is greater than or equal to 1nm and less than or equal to 90nm, and the width of the bottom opening of the first groove is 4-12 μm.
In one possible embodiment, the wall of the first through hole forms an angle β with the upper surface of the conductive protection layer1Is 15 of(ii) at an angle of 60 °, the first via has a minimum width at its interface with the conductive protection layer; the width of the first groove is smaller than or equal to the minimum width of the first through hole.
In one possible embodiment, the material of the conductive protection layer comprises one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide and gallium phosphide, and the thickness of the conductive protection layer is 100-300 nm.
In one possible embodiment, no metal layer is included between the conductive protection layer and the insulating layer overlying the conductive protection layer.
In one possible embodiment, the conductive protection layer is a metal layer and has a thickness of 300-1000 nm.
In one possible embodiment, the sidewall of the conductive protection layer has an angle α of 5 ° to 60 ° with the mesa.
In a possible embodiment, a first current blocking layer is further included between the conductive protection layer and the mesa, and the conductive protection layer covers an upper surface and a sidewall of the first current blocking layer and contacts the mesa.
In one possible embodiment, the first current blocking layer comprises a silicon oxide layer, a silicon nitride layer or an aluminum oxide layer.
In one possible embodiment, the side length of the flip-chip light emitting diode is not more than 300 μm.
In one possible embodiment, the flip-chip light emitting diode further comprises:
a transparent conductive layer formed on the second semiconductor layer;
the insulating layer also covers the second semiconductor layer and the transparent conducting layer; the insulating layer is provided with a second through hole with a width D3Less than the width D of the transparent conductive layer4；
And a second pad electrode formed in the second via hole and connected to the transparent conductive layer.
In one possible embodiment, no metal layer is included between the transparent conductive layer and the insulating layer overlying the transparent conductive layer.
In one possible embodiment, the material of the transparent conductive layer comprises one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide and gallium phosphide, and the thickness of the transparent conductive layer is 100-300 nm.
In a possible embodiment, the transparent conductive layer further includes a second groove extending from the upper surface of the transparent conductive layer to the inside thereof, and the depth of the second groove is 1% to 30% of the thickness of the transparent conductive layer.
In a possible embodiment, the second groove is located below the second through hole, and the width of the second groove is smaller than or equal to the width of the second through hole.
In one possible embodiment, the width of the top opening of the second groove is greater than the width of the bottom opening of the second groove.
In a possible embodiment, the depth of the second groove is greater than or equal to 1nm and less than or equal to 90nm, and the width of the bottom opening of the second groove is 4-12 μm.
In a possible embodiment, the wall of the second through hole forms an angle β with the upper surface of the transparent conductive layer2Is 15 DEG to 60 DEG, the second through hole has a minimum width at the interface with the transparent conductive layer; the width of the second groove is smaller than or equal to the minimum width of the second through hole.
In one possible embodiment, a second current blocking layer is further included between the transparent conductive layer and the second semiconductor layer, and the transparent conductive layer covers the upper surface and the side wall of the second current blocking layer and is in contact with the second semiconductor layer.
In a second aspect, the present application provides a light emitting device comprising a substrate and a plurality of flip chip light emitting diodes of the above embodiments secured to the substrate.
Compared with the prior art, the application has at least the following beneficial effects:
the conductive protection layer is formed on the table top in the semiconductor stacking layer, and the conductive protection layer has smaller thickness, so that corners of the insulating layer covering the conductive protection layer can be avoided, the risk that the first pad electrode is broken is reduced, and the first pad electrode has good coverage. The first through hole is located above the conductive protection layer, and in the forming process of the first through hole, the conductive protection layer can prevent the surface of the first semiconductor layer from being damaged or forming high-resistance substances, so that the phenomenon that the voltage of the flip light-emitting diode is easily increased is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a schematic structural diagram of a conventional flip-chip LED;
fig. 2 is a schematic structural diagram of a flip-chip light emitting diode according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a flip-chip light emitting diode according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a flip-chip light emitting diode according to an embodiment of the present application;
FIG. 5 is a schematic structural view of the region I in FIGS. 2 to 4;
FIG. 6 is a schematic view of the structure of FIG. 2-4 at region I;
FIG. 7 is a schematic view of the structure of FIG. 2-4 at region II;
FIG. 8 is a schematic view of the structure of FIG. 2-4 at region II;
fig. 9 is a schematic structural view of the region III in fig. 2 to 4.
Illustration of the drawings:
10 a substrate; 20 semiconductor stacked layers; a 21N type semiconductor layer; 22 an active layer; a 23P-type semiconductor layer; 24 a table top; 30 contact electrodes; 31 a first contact electrode; 32 a second contact electrode; 40 an insulating layer; 50 pad electrodes; 51 a first pad electrode; 52 a second pad electrode; 60 a transparent conductive layer;
100 a substrate; 200 semiconductor stacked layers; 201 a first semiconductor layer; 202 an active layer; 203 a second semiconductor layer; 210 a table top; 300 a first current blocking layer; 310 a second current blocking layer; 400 a conductive protection layer; 401 a first groove; 500 a transparent conductive layer; 501 a second groove; 600 insulating layer; 601 a first via hole; 602 a second via; 700 a first pad electrode; 710 a second pad electrode.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and variations in various respects, all without departing from the spirit of the present application.
In the description of the present application, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, and are only used for convenience in describing the present application and simplifying the description, but do not indicate or imply that the devices or elements that are referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," etc. are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
According to an aspect of the present application, a flip-chip light emitting diode is provided, in particular a small-sized flip-chip light emitting diode, such as a mini-type flip-chip light emitting diode or a micro-type flip-chip light emitting diode. The mini type flip-chip LED has a size of 90000 μm2The length and width of the film are 100 to 300 μm and the height is 40 to 100 μm. The micro flip-chip light emitting diode is smaller than the mini flip-chip light emitting diode, and the length and the width of the micro flip-chip light emitting diode are 1-100 mu m.
Referring to fig. 2 and 5, the flip chip light emitting diode includes a semiconductor stack layer 200, and the semiconductor stack layer 200 includes, from bottom to top, a first semiconductor layer 201, an active layer 202, and a second semiconductor layer 203, wherein the first semiconductor layer 201 is an N-type semiconductor layer, the active layer 202 is a multi-layer quantum well layer, and the second semiconductor layer 203 is a P-type semiconductor layer. The semiconductor stack layer 200 has a mesa 210 exposing the first semiconductor layer 201, and the conductive protection layer 400 is disposed on the mesa 210.
The insulating layer 600 covers the mesa 210 and the conductive protection layer 400 on the mesa 210, the insulating layer 600 is provided with a first through hole 601, and a projection of the first through hole 601 in a projection direction perpendicular to the mesa 210 falls into a projection of the conductive protection layer 400, that is, a width D of the first through hole 6011Less than the width D of the conductive protection layer 4002. The first through hole 601 is obtained by using an Inductively Coupled Plasma (ICP) etching method.
The first pad electrode 700 is located on the insulating layer 600 and penetrates the first via hole 601 to be connected to the conductive protection layer 400.
Preferably, the material of the conductive protection layer 400 includes one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, and gallium phosphide, and the thickness of the conductive protection layer 400 is preferably 100 to 300 nm. In this embodiment, a metal layer is not included between the conductive passivation layer 400 and the insulating layer 600 covering the conductive passivation layer 400, that is, the first pad electrode 700 passes through the first via 601 and is directly connected to the conductive passivation layer 400.
Alternatively, the conductive protection layer 400 is a metal layer with a thickness of 300-1000 nm, and the metal layer includes, but is not limited to, a gold layer, an aluminum layer, a chromium layer, a platinum layer, or an alloy layer formed by at least two materials of aluminum, chromium, nickel, titanium, platinum, tin, gold, etc.
Due to the fact that the thickness of the conductive protection layer 400 is small, the insulating layer 600 can be smoothly transited to the conductive protection layer 400 from the mesa 210, and corners of the insulating layer 600 above the conductive protection layer 400 are avoided, so that the risk that the first pad electrode 700 is broken is reduced, and the first pad electrode 700 has good coverage.
The conductive protection layer 400 is located below the first through hole 601, and in the formation process of the first through hole 601, the conductive protection layer 400 can prevent the surface of the first semiconductor layer 201 from being damaged or forming a high-resistance substance, so that the phenomenon that the voltage of the flip-chip light emitting diode is easily increased is improved.
In one embodiment, referring to fig. 5 and 6, the conductive protection layer 400 further includes a first groove 401, the first groove 401 extends from the upper surface of the conductive protection layer 400 to the inside of the conductive protection layer 400, and the depth of the first groove 401 is 1% to 30% of the thickness of the conductive protection layer 400.
The first groove 401 is located below the first through hole 601, and a projection of the first groove 401 in a projection direction perpendicular to the mesa 210 falls inside a projection of the first through hole 601, that is, a width of the first groove 401 is less than or equal to a width of the first through hole 601.
As shown in fig. 5, an angle β between the wall of the first through hole 601 and the upper surface of the conductive passivation layer 400 is1And is 15 deg. to 60 deg., the first via hole 601 has a minimum width at its interface with the conductive protection layer 400, that is, the width of the first via hole 601 at the side close to the conductive protection layer 400 is the minimum width of the first via hole 601. The width of the first groove 401 is less than or equal to the minimum width of the first through hole 601.
Preferably, the top opening width of the first groove 401 is greater than the bottom opening width of the first groove 402.
Preferably, the depth of the first groove 401 is greater than or equal to 1nm and less than or equal to 90 nm. The width of the bottom opening of the first groove 401 is 4-12 μm.
Preferably, the first pad electrode 700 extends from the upper surface of the insulating layer 600 to the first recess 401, and the wall surface of the first recess 401 is a rough surface, so as to enhance the combining ability of the first pad electrode 700 and the conductive protection layer 400.
As shown in fig. 6, the walls of the first through holes 601 are perpendicular to the upper surface of the conductive protection layer 400, that is, the widths of the first through holes 601 are the same in a direction perpendicular to the upper surface of the conductive protection layer 400. The width of the first groove 401 is equal to the width of the first through hole 601. The top opening width of the first groove 401 is equal to the bottom opening width of the first groove 402. The depth of the first groove 401 is 1nm or more and 90nm or less.
In one embodiment, referring to fig. 9, an included angle α between the sidewall of the conductive protection layer 400 and the mesa 210 is preferably 5 ° to 60 °, and since the conductive protection layer 400 has an inclined sidewall having a smaller included angle with the mesa 210, the insulating layer 600 may smoothly extend from the inclined sidewall of the conductive protection layer 400 to the upper surface of the conductive protection layer 400, thereby further avoiding the insulating layer 600 located above the conductive protection layer 400 from having a corner, and thus reducing the risk of the first pad electrode 700 breaking, so that the first pad electrode 700 has good coverage.
In one embodiment, referring to fig. 3 and 4, when the material of the conductive protection layer 400 is one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, and gallium phosphide, the first current blocking layer 300 is further included between the conductive protection layer 400 and the mesa 210, and the conductive protection layer 400 covers the upper surface and the sidewall of the first current blocking layer 300 and contacts the mesa 210. The first current blocking layer 300 includes a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer.
In one embodiment, referring to fig. 2 to 4, and fig. 7, the flip chip light emitting diode further includes a transparent conductive layer 500 disposed on the second semiconductor layer 203 and a second pad electrode 710. The insulating layer 600 further covers the second semiconductor layer 203 and the transparent conductive layer 500 on the second semiconductor layer 203, the insulating layer 600 is provided with a second through hole 602, and a projection of the second through hole 602 in a projection direction perpendicular to the mesa 210 falls inside a projection of the transparent conductive layer 500, that is, a width D of the second through hole 6023Is less than the width D of the transparent conductive layer 5004. The second pad electrode 710 is disposed on the insulating layer 600 and penetrates the second via hole 602 to be connected to the transparent conductive layer 500. The second via 602 is obtained by using an Inductively Coupled Plasma (ICP) etching method.
The material of the transparent conductive layer 500 includes one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, and gallium phosphide, the thickness of the transparent conductive layer 500 is preferably 100 to 300nm, and the included angle between the sidewall of the transparent conductive layer 500 and the upper surface of the second semiconductor layer 203 is preferably 5 to 60 °. When the material of the conductive protection layer 400 is the same as the material of the transparent conductive layer 500, the transparent conductive layer 500 and the conductive protection layer 400 can be formed simultaneously in the same manufacturing process. The effect of the transparent conductive layer 500 on the second semiconductor layer 203 and the insulating layer 600 is the same as the effect of the conductive protection layer 400 on the first semiconductor layer 201 and the insulating layer 600, and thus, the description thereof is omitted. In this embodiment, a metal layer is not included between the transparent conductive layer 500 and the insulating layer 600 covering the transparent conductive layer 500, that is, the second pad electrode 710 passes through the second via 602 and is directly connected to the transparent conductive layer 500.
In one embodiment, referring to fig. 7 and 8, the transparent conductive layer 500 further includes a second groove 501, the second groove 501 extends from the upper surface of the transparent conductive layer 500 to the inside of the transparent conductive layer 500, and the depth of the second groove 501 is 1% to 30% of the thickness of the transparent conductive layer 500.
The second groove 501 is located below the second through hole 602, and a projection of the second groove 501 in a projection direction perpendicular to the table 210 falls inside a projection of the second through hole 602, that is, a width of the second groove 501 is smaller than or equal to a width of the second through hole 602.
As shown in fig. 7, an included angle β between the wall of the second through hole 602 and the upper surface of the transparent conductive layer 5002And is 15 deg. to 60 deg., the second via hole 602 has a minimum width at its interface with the transparent conductive layer 500, that is, the width of the second via hole 602 on the side close to the transparent conductive layer 500 is the minimum width of the second via hole 602. The width of the second groove 501 is less than or equal to the minimum width of the second through hole 602.
Preferably, the top opening width of the second groove 501 is greater than the bottom opening width of the second groove 501.
Preferably, the depth of the second groove 501 is greater than or equal to 1nm and less than or equal to 90 nm. The width of the bottom opening of the second groove 501 is 4-12 μm.
Preferably, the second pad electrode 710 extends from the upper surface of the insulating layer 600 into the second recess 501, and the wall surface of the second recess 501 is a rough surface, so as to enhance the combining ability of the second pad electrode 710 and the transparent conductive layer 500.
As shown in fig. 8, the walls of the second through holes 602 are perpendicular to the upper surface of the transparent conductive layer 500, that is, the widths of the second through holes 602 are the same in a direction perpendicular to the upper surface of the transparent conductive layer 500. The width of the second groove 501 is equal to the width of the second through hole 602. The top opening width of the second groove 501 is equal to the bottom opening width of the second groove 501. The depth of the second groove 501 is not less than 1nm and not more than 90 nm.
In one embodiment, referring to fig. 4, a second current blocking layer 310 is further included between the transparent conductive layer 500 and the second semiconductor layer 203, and the transparent conductive layer 500 covers the upper surface and the sidewall of the second current blocking layer 310 and is in contact with the second semiconductor layer 203. The second current blocking layer 310 includes a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer.
Preferably, the second current blocking layer 310 and the first current blocking layer 300 may be formed simultaneously in the same manufacturing process.
In one embodiment, referring to fig. 2-4, the flip-chip light emitting diode further comprises a substrate 100, wherein the substrate 100 is one of a sapphire flat-bottom substrate, a sapphire patterned substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, or a silicon substrate. In the present embodiment, substrate 100 is selected as a sapphire patterned substrate, and semiconductor stack layer 200 is formed on the upper surface of the sapphire patterned substrate.
The insulating layer 600 includes, but is not limited to, a Distributed Bragg Reflector (DBR), and the material of the insulating layer 600 is SiO2、TiO2、ZnO2、ZrO2、Cu2O3、Al2O3And the insulating layer 600 may specifically include a distributed bragg mirror made by alternately laminating two materials in a multilayer using a technique such as electron beam evaporation or ion beam sputtering. Alternatively, the insulating layer 600 has a single layer structure including, but not limited to, an aluminum oxide layer, a titanium oxide layer, a silicon oxide layer, or a silicon nitride layer.
The material of the first and second pad electrodes 700 and 710 may be a material such as aluminum, chromium, nickel, titanium, platinum, tin, gold, or an alloy composed of at least two of these materials.
According to an aspect of the present application, there is provided a light emitting device, which may be a backlight display device, such as a television, a mobile phone, a panel, or may be an RGB display screen. The light emitting device, whether a backlight display device or an RGB display screen, includes a substrate and a plurality of flip-chip light emitting diodes in the above embodiments fixed on the substrate. The flip-chip light emitting diode is integrally mounted on an application substrate or a package substrate in a number of hundreds or thousands or tens of thousands to form a light emitting source portion for backlight display or RGB display.
According to the above technical solution, the conductive protection layer 400 is formed on the mesa 210 in the semiconductor stacked layer 200, and the conductive protection layer 400 has a smaller thickness, so that the insulating layer 600 covering the conductive protection layer 400 can be prevented from turning, thereby reducing the risk of fracture of the first pad electrode 700, and enabling the first pad electrode 700 to have good coverage. The first through hole 601 is located above the conductive protection layer 400, and in the formation process of the first through hole 601, the conductive protection layer 400 can prevent the surface of the first semiconductor layer 201 from being damaged or forming a high-resistance substance, thereby improving the phenomenon that the voltage of the flip-chip light emitting diode is easily increased.
The foregoing is only a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and substitutions can be made without departing from the technical principle of the present application, and these modifications and substitutions should also be regarded as the protection scope of the present application.

Claims (23)

1. A flip chip light emitting diode comprising:
the semiconductor device comprises a semiconductor stack layer, a first semiconductor layer, a second semiconductor layer and an active layer positioned between the first semiconductor layer and the second semiconductor layer; the semiconductor stacking layer is provided with a table top exposing the first semiconductor layer;
a conductive protection layer formed on the mesa;
the insulating layer covers the table board and the conductive protective layer; the insulationThe layer is provided with a first through hole, and the width D of the first through hole1Less than the width D of the conductive protective layer2；
And the first pad electrode is formed in the first through hole and is connected with the conductive protection layer.
2. The flip chip light emitting diode of claim 1, wherein the conductive protection layer further comprises a first groove extending from the upper surface of the conductive protection layer to the inside thereof, and the depth of the first groove is 1% to 30% of the thickness of the conductive protection layer.
3. The flip-chip led of claim 2, wherein the first recess is located below the first via, and a width of the first recess is less than or equal to a width of the first via.
4. The flip chip light emitting diode of claim 3, wherein the top opening width of the first recess is greater than the bottom opening width of the first recess.
5. The flip-chip light emitting diode of claim 3, wherein the depth of the first groove is greater than or equal to 1nm and less than or equal to 90nm, and the width of the bottom opening of the first groove is 4-12 μm.
6. The flip-chip led of claim 3, wherein the angle β between the wall of the first via and the top surface of the conductive passivation layer1Is 15 DEG to 60 DEG, the first through hole has a minimum width at an interface thereof with the conductive protection layer; the width of the first groove is smaller than or equal to the minimum width of the first through hole.
7. The flip-chip light emitting diode of claim 1, wherein the material of the conductive protection layer comprises one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, and gallium phosphide, and the thickness of the conductive protection layer is 100-300 nm.
8. The flip chip light emitting diode of claim 7, wherein the conductive passivation layer does not include a metal layer between the insulating layer overlying the conductive passivation layer.
9. The flip-chip LED of claim 1, wherein the conductive protection layer is a metal layer and has a thickness of 300-1000 nm.
10. The flip-chip led of claim 1, wherein the angle α between the sidewall of the conductive passivation layer and the mesa is in the range of 5 ° to 60 °.
11. The flip chip light emitting diode of claim 7, further comprising a first current blocking layer between the conductive passivation layer and the mesa, wherein the conductive passivation layer covers an upper surface and sidewalls of the first current blocking layer and contacts the mesa.
12. The flip chip light emitting diode of claim 11, wherein the first current blocking layer comprises a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer.
13. The flip chip light emitting diode of claim 1, wherein the side length of the flip chip light emitting diode is no greater than 300 μm.
14. The flip-chip light emitting diode of any one of claims 1 to 13, further comprising:
a transparent conductive layer formed on the second semiconductor layer;
the insulating layer also covers the second semiconductor layer and the transparent conducting layer; the insulating layer is provided with a second through hole, and the second through holeWidth D of the hole3Width D less than the transparent conductive layer4；
And the second pad electrode is formed in the second through hole and is connected with the transparent conductive layer.
15. The flip chip light emitting diode of claim 14, wherein the transparent conductive layer does not include a metal layer between the insulating layer overlying the transparent conductive layer.
16. The flip-chip light emitting diode of claim 14, wherein the material of the transparent conductive layer comprises one or two of indium tin oxide, indium oxide, tin oxide, cadmium tin oxide, antimony tin oxide, zinc oxide, and gallium phosphide, and the thickness of the transparent conductive layer is 100-300 nm.
17. The flip chip light emitting diode of claim 16, wherein the transparent conductive layer further comprises a second groove extending from the upper surface of the transparent conductive layer to the inside thereof, and the depth of the second groove is 1% to 30% of the thickness of the transparent conductive layer.
18. The flip chip light emitting diode of claim 17, wherein the second recess is located below the second via, and a width of the second recess is less than or equal to a width of the second via.
19. The flip chip light emitting diode of claim 18, wherein the top opening width of the second recess is greater than the bottom opening width of the second recess.
20. The flip-chip light emitting diode of claim 18, wherein the depth of the second groove is greater than or equal to 1nm and less than or equal to 90nm, and the width of the bottom opening of the second groove is 4-12 μm.
21. The flip-chip led of claim 18, wherein the angle β between the wall of the second via and the top surface of the transparent conductive layer2Is 15 DEG to 60 DEG, the second through hole has a minimum width at its interface with the transparent conductive layer; the width of the second groove is smaller than or equal to the minimum width of the second through hole.
22. The flip chip light emitting diode of claim 16, further comprising a second current blocking layer between the transparent conductive layer and the second semiconductor layer, wherein the transparent conductive layer covers an upper surface and sidewalls of the second current blocking layer and contacts the second semiconductor layer.
23. A light emitting device comprising a substrate and a plurality of flip chip light emitting diodes according to any one of claims 1 to 22 mounted on the substrate.
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