CN113892183A - 包括超晶格和非对称沟道的半导体器件及相关方法 - Google Patents

包括超晶格和非对称沟道的半导体器件及相关方法 Download PDF

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CN113892183A
CN113892183A CN202080038793.XA CN202080038793A CN113892183A CN 113892183 A CN113892183 A CN 113892183A CN 202080038793 A CN202080038793 A CN 202080038793A CN 113892183 A CN113892183 A CN 113892183A
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superlattice
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CN113892183B (zh
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武内英树
R·伯顿
Y-H·杨
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Atomera Inc
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Abstract

一种半导体器件可以包括基板(61)和在基板中间隔开的第一(62，66)掺杂区域和第二(63)掺杂区域。第一掺杂区域可以大于第二掺杂区域以在它们之间限定非对称沟道。半导体器件还可以包括在第一掺杂区域和第二掺杂区域之间延伸以约束其中的掺杂剂的超晶格(25)。超晶格可以包括多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被约束在相邻基础半导体部分的晶格内的至少一个非半导体单层。栅极(64)可以上覆于非对称沟道。

Description

包括超晶格和非对称沟道的半导体器件及相关方法
技术领域
本公开一般而言涉及半导体器件，并且更具体地，涉及具有增强沟道结构的半导体器件及相关方法。
背景技术
已经提出了增强半导体器件的性能的结构和技术，诸如通过增强电荷载流子的迁移率。例如，授予Currie等人的美国专利申请No.2003/0057416公开了硅、硅锗和松弛硅的应变材料层，并且还包括无杂质的区(否则杂质会造成性能降级)。在上部硅层中产生的双轴应变更改了载流子迁移率，从而实现了更高速度和/或更低功率的器件。授予Fitzgerald等人的已公开美国专利申请No.2003/0034529公开了也基于类似的应变硅技术的CMOS反相器。
授予Takagi的美国专利No.6,472,685B2公开了一种半导体器件，其包括硅和夹在硅层之间的碳层，使得第二硅层的导带和价带接受拉伸应变。有效质量较小并且已经由施加到栅电极的电场感应出的电子被限制在第二硅层中，因此，断言n沟道MOSFET具有更高的迁移率。
授予Ishibashi等人的美国专利No.4,937,204公开了一种超晶格，其中交替地且外延生长其中少于八个单层并且包含分数或二元或二元化合物半导体层的多个层。主电流流动的方向垂直于超晶格的层。
授予Wang等人的美国专利No.5,357,119公开了通过减少超晶格中的合金散射而获得的具有更高迁移率的Si-Ge短周期超晶格。沿着这些思路，授予Candelaria的美国专利No.5,683,934公开了一种增强迁移率的MOSFET，该MOSFET包括沟道层，该沟道层包括以将沟道层置于拉伸应变下的百分比交替存在于硅晶格中的硅合金和第二材料。
授予Tsu的美国专利No.5,216,262公开了一种量子阱结构，其包括两个势垒区域和夹在势垒之间的外延生长的薄半导体层。每个势垒区域由交替的SiO2/Si层组成，其厚度一般在二到六个单层的范围内。在势垒层之间夹有厚得多的硅部分。
同样是Tsu于2000年9月6日在Applied Physics and Materials Science&Processing第391-402页在线发表的标题为“Phenomena in silicon nanostructuredevices”的文章公开了硅和氧的半导体原子超晶格(SAS)。公开了在硅量子和发光器件中有用的Si/O超晶格。特别地，构造并测试了绿色电致发光二极管结构。二极管结构中的电流流动是垂直的，即，垂直于SAS的层。所公开的SAS可以包括被诸如氧原子和CO分子之类的吸附物质隔开的半导体层。超出被吸附的氧单层的硅生长被描述为具有相当低缺陷密度的外延生长。一种SAS结构包括1.1nm厚的硅部分，该部分大约为八个原子硅层，而另一种结构的硅厚度是该硅厚度的两倍。发表在Physical Review Letters第89卷第7期(2002年8月12日)上的Luo等人的标题为“Chemical Design of Direct-Gap Light-Emitting Silicon”的文章进一步讨论了Tsu的发光SAS结构。
授予Wang等人的美国专利No.7,105,895公开了由薄硅和氧、碳、氮、磷、锑、砷或氢形成的势垒层构造块，由此超过四个数量级进一步减少了垂直流过晶格的电流。绝缘层/势垒层允许在绝缘层旁边沉积低缺陷外延硅。
授予Mears等人的公开的英国专利申请2,347,520公开了非周期性光子带隙(APBG)结构的原理可以适用于电子带隙工程。特别地，该申请公开了可以调整材料参数(例如，能带最小值的位置、有效质量等)，以产生具有期望带结构特点的新型非周期性材料。还公开了其它参数(诸如电导率、热导率和介电常数或磁导率)也可能被设计进该材料中。
此外，授予Wang等人的美国专利No.6,376,337公开了用于生产半导体器件的绝缘或势垒层的方法，该方法包括在硅基板上沉积硅层和至少一种附加元素，由此沉积层基本上没有缺陷，使得可以在沉积层上沉积基本上没有缺陷的外延硅。可替代地，一种或多种元素(优选地包括氧)的单层被吸收在硅基板上。夹在外延硅之间的多个绝缘层形成势垒复合物。
尽管存在此类方法，但是可能期望进一步的增强以使用先进的半导体材料和处理技术来提高半导体器件的性能。
发明内容
一种半导体器件可以包括基板和在基板中的间隔开的第一掺杂区域和第二掺杂区域。第一掺杂区域可以大于第二掺杂区域以在它们之间限定非对称沟道。半导体器件还可以包括在第一掺杂区域和第二掺杂区域之间延伸以约束其中的掺杂剂的超晶格。超晶格可以包括多个堆叠的层组，每个层组包括：限定基础半导体部分的多个堆叠的基础半导体单层，以及约束在相邻基础半导体部分的晶格内的至少一个非半导体单层。栅极可以上覆于非对称沟道。
在示例实施例中，第一区域可以包括漏极区域，并且第二区域可以包括源极区域。超晶格可以上覆于(overlie)第一掺杂区域的至少一部分。此外，在一些实施例中，非对称沟道可以至少部分地在超晶格内。在其它示例实施例中，半导体器件还可以包括在非对称沟道下方的基板中的穿通停止植入物(punch through stop implant)。
第一掺杂区域和第二掺杂区域可以具有第一导电类型，并且半导体器件还可以包括被与第二掺杂区域相邻的超晶格约束在基板内并且具有与第一导电类型不同的第二导电类型的阱植入物。更特别地，第一掺杂区域可以在栅极下方横向延伸超过非对称沟道的中心。
作为示例，栅极可以包括上覆于超晶格的栅极电介质和上覆于栅极介电层的栅电极。半导体器件还可以包括在基板上与栅极横向相邻的侧壁间隔件。作为示例，基础半导体单层可以包括硅单层，并且至少一个非半导体单层可以包括氧。
方法方面用于制造半导体器件并且可以包括：在基板中形成间隔开的第一掺杂区域和第二掺杂区域。第一掺杂区域可以大于第二掺杂区域以在它们之间限定非对称沟道。该方法还可以包括：形成在第一掺杂区域和第二掺杂区域之间延伸以约束其中的掺杂剂的超晶格。超晶格可以包括多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被约束在相邻基础半导体部分的晶格内的至少一个非半导体单层。该方法还可以包括：形成上覆于非对称沟道的栅极。
在示例实施例中，第一区域可以包括漏极区域，并且第二区域可以包括源极区域。形成超晶格可以包括形成上覆于第一掺杂区域的至少一部分的超晶格。此外，在一些实施例中，非对称沟道可以至少部分地在超晶格内。在其它示例实施例中，该方法还可以包括在非对称沟道下方的基板中形成穿通停止植入物。
第一掺杂区域和第二掺杂区域可以具有第一导电类型，并且该方法还可以包括：形成阱植入物，该阱植入物被与第二掺杂区域相邻的超晶格约束在基板内并且具有与第一导电类型不同的第二导电类型。更特别地，第一掺杂区域可以在栅极下方横向延伸超过非对称沟道的中心。
作为示例，形成栅极可以包括形成上覆于超晶格的栅极电介质，以及形成上覆于栅极介电层的栅电极。该方法还可以包括在基板上形成与栅极横向相邻的侧壁间隔件。例如，基础半导体单层可以包括硅单层，并且至少一个非半导体单层可以包括氧。
附图说明
图1是用在根据示例实施例的半导体器件中的超晶格的非常放大的示意性横截面图。
图2是图1中所示的超晶格的一部分的透视原子示意图。
图3是根据示例实施例的超晶格的另一个实施例的非常放大的示意性横截面图。
图4A是对于现有技术中的块状硅以及对于如图1-2中所示的4/1Si/O超晶格，都从伽玛点(G)计算得到的能带结构的曲线图。
图4B是对于现有技术中的块状硅以及对于如图1-2中所示的4/1Si/O超晶格，都从Z点计算得到的能带结构的曲线图。
图4C是对于现有技术中的块状硅以及对于如图3中所示的5/1/3/1Si/O超晶格，都从伽玛和Z点计算得到的能带结构的曲线图。
图5是根据示例实施例的包括提供非对称沟道的超晶格的MOSFET的示意性框图。
图6A是包括根据现有技术的具有相关联的掺杂分布的对称掺杂沟道的半导体器件的示意性框图。
图6B是图6A的半导体器件的等效示意图。
图7A是图5的包括非对称的未掺杂沟道的半导体器件的示意性框图。
图7B是图7A的半导体器件的等效示意图。
图8是图6A和图7A的半导体器件的有效场相对于迁移率的曲线图。
图9是图5的包括穿通停止植入物的半导体器件的替代实施例的示意性框图。
图10和图11是图示根据示例实施例的用于制造包括非对称沟道的半导体器件的方法的流程图。
图12是根据示例实施例的包括非对称沟道的LV-DEMOS器件的示意性框图。
图13是根据示例实施例的包括非对称沟道的DEMOS器件的示意性框图。
图14是根据示例实施例的包括非对称沟道的LDMOS器件的示意性框图。
具体实施方式
现在将在下文中参考附图更全面地描述示例实施例，在附图中示出了示例实施例。但是，实施例可以以许多不同的形式来实现，并且不应该被解释为限于本文阐述的具体示例。而是，提供这些实施例以使得本公开将是透彻和完整的。贯穿全文，相似的数字指示相似的元件，并且在不同的实施例中使用撇号和多个撇号指示相似的元件。
一般而言，本公开涉及利用增强型半导体超晶格通过准确的掺杂剂扩散控制提供非对称沟道来形成半导体器件。在本公开中，增强型半导体超晶格也称为“MST”层或“MST技术”。
更特别地，MST技术涉及先进的半导体材料，诸如以下进一步描述的超晶格25。申请人理论上不希望受限于此，认为本文所述的某些超晶格降低了电荷载流子的有效质量，并且这导致更高的电荷载流子迁移率。有效质量在文献中有各种定义。作为改善有效质量的措施，申请人使用“电导率倒数有效质量张量”，并且针对电子和空穴的
Figure BDA0003373372510000061
和
Figure BDA0003373372510000062
分别对于电子定义为：
Figure BDA0003373372510000063
并且对于空穴定位为：
Figure BDA0003373372510000064
其中f是费米-狄拉克(Fermi-Dirac)分布，EF是费米能量，T是温度，E(k,n)是处于在与波向量k和第n个能带对应的状态的电子的能量，索引i和j是指笛卡尔坐标x、y和z，积分在布里渊(Brillouin)区(B.Z.)上获取，并且总和在能量分别高于和低于费米能量的电子和空穴的能带上获取。
申请人对电导率倒数有效质量张量的定义使得，对于电导率倒数有效质量张量的对应分量的越大值，材料的电导率的张量分量越大。希望不限于此，申请人再次在理论上认为本文所述的超晶格设置电导率倒数有效质量张量的值，以增强材料的导电特性，诸如典型地对于电荷载流子运输的优选方向。适当张量元素的倒数被称为电导率有效质量。换句话说，为了表征半导体材料结构，如上所述并在预期的载流子运输方向上计算的电子/空穴的电导率有效质量被用于区分改进的材料。
申请人已经识别出用在半导体器件中的改进的材料或结构。更具体而言，申请人已经识别出具有能带结构的材料或结构，对于这些材料或结构，用于电子和/或空穴的适当电导率有效质量基本上小于针对硅的相应值。除了这些结构的增强的迁移率特点外，它们还可以以提供有利于在各种不同类型的器件中使用的压电、热电和/或铁电特性的方式被形成或使用，如将在下面进一步讨论的。
现在参考图1和2，材料或结构为超晶格25的形式，其结构被控制在原子或分子水平，并且可以使用原子或分子层沉积的已知技术来形成。超晶格25包括以堆叠关系布置的多个层组45a-45n，如通过具体参考图1的示意性横截面图可能最好地理解的。
超晶格25的每个层组45a-45n说明性地包括多个堆叠的基础半导体单层46(其限定相应的基础半导体部分46a-46n)和其上的能带改性层50。为了说明清楚，在图1中用点划线指示能带改性层50。
能带改性层50说明性地包括一个非半导体单层，该非半导体单层被约束在相邻基础半导体部分的晶格内。“约束在相邻基础半导体部分的晶格内”是指来自相对的基础半导体部分46a-46n的至少一些半导体原子通过其间的非半导体单层50化学键合在一起，如图2中所看到的。一般而言，通过控制通过原子层沉积技术沉积在半导体部分46a-46n上的非半导体材料的数量，使得并非所有(即，小于全部或100％覆盖率)可用半导体键合位点上都填充有与非半导体原子的键，使得这种构造成为可能，如下面将进一步讨论的。因此，当半导体材料的另外的单层46沉积在非半导体单层50上或上方时，新沉积的半导体原子将填充在非半导体单层下方的半导体原子的剩余的空键合位点。
在其它实施例中，有可能可以多于一个这样的非半导体单层。应该注意的是，本文中对非半导体或半导体单层的引用是指，如果用于该单层的材料以块状形成，那么它将是非半导体或半导体。即，如本领域技术人员将认识到的，材料(诸如硅)的单个单层不一定表现出与如果以块状或以相对厚的层形成时相同的特性。
希望不限于此，申请人在理论上认为能带改性层50和相邻的基础半导体部分46a-46n使得超晶格25对于在平行层方向上的电荷载流子具有比其它方式将存在的更低的适当电导率有效质量。以另一种方式考虑，这个平行方向与堆叠方向正交。能带改性层50还可以使得超晶格25具有共同的能带结构，同时还有利地用作在超晶格的垂直上方和下方的层或区域之间的绝缘体。
而且，这种超晶格结构还可以有利地充当在超晶格25的垂直上方和下方的层之间的掺杂剂和/或材料扩散的屏障。这些特性因此可以有利地允许超晶格25提供用于高K电介质的界面，该界面不仅减少高K材料向沟道区域中的扩散，而且还可以有利地减少不想要的散射效应并改善器件迁移率，如本领域技术人员将认识到的。
理论上还认为包括超晶格25的半导体器件可以基于比其它情况下将存在的更低的电导率有效质量而享有更高的电荷载流子迁移率。在一些实施例中，并且作为由本发明实现的能带设计的结果，超晶格25还可以具有基本上直接的能带隙，这对于例如光电子器件可以是特别有利的。
超晶格25还说明性地包括在上层组45n上的盖层52。盖层52可以包括多个基础半导体单层46。盖层52可以具有基础半导体的2至100个单层，并且更优选地10至50个单层。
每个基础半导体部分46a-46n可以包括选自IV族半导体、III-V族半导体和II-VI族半导体中的基础半导体。当然，如本领域技术人员将认识到的，术语“IV族半导体”还包括IV-IV族半导体。更特别地，例如，基础半导体可以包括硅和锗中的至少一种。
每个能带改性层50可以包括例如选自氧、氮、氟、碳和碳-氧中的非半导体。还期望通过沉积下一层来使非半导体热稳定，由此促进制造。在其它实施例中，非半导体可以是与给定的半导体处理兼容的另一种无机或有机元素或化合物，如本领域技术人员将认识到的。更特别地，例如，基础半导体可以包括硅和锗中的至少一种。
应该注意的是，术语单层意味着包括单个原子层以及单个分子层。还应该注意的是，由单个单层提供的能带改性层50还意味着包括其中并非所有可能的位点都被占据的单层(即，小于全部或100％的覆盖率)。例如，特别参考图2的原子图，图示了4/1重复结构，其中硅作为基础半导体材料，而氧作为能带改性材料。在所示的示例中，仅一半用于氧的可能位点被占用。
在其它实施例中和/或对于不同的材料，如本领域技术人员将认识到的那样，这种一半的占用将不一定是这种情况。实际上，即使在这个示意图中也可以看出给定单层中氧的各个原子没有沿着平坦的平面精确对准，这也是原子沉积领域的技术人员将认识到的。举例来说，优选的占用范围是可能的氧位点充满的大约八分之一至二分之一，但是在某些实施例中可以使用其它数量。
硅和氧目前广泛用在常规半导体处理中，因此，制造商将能够容易地使用本文中所述的这些材料。原子或单层沉积现在也被广泛使用。因而，如本领域技术人员将认识到的，结合根据本发明的超晶格25的半导体器件可以容易地被采用和实现。
希望不限于此，申请人在理论上认为，例如，对于超晶格(诸如Si/O超晶格)，硅单层的数量应该期望地为七个或更少，以便超晶格的能带在整个超晶格是共同的或相对均匀的，以实现期望的优点。对于Si/O，图1和2中所示的4/1重复结构已被建模为指示电子和空穴在X方向上增强的迁移率。例如，计算得出的电导率有效质量针对于电子(针对块状硅的各向同性)为0.26，并且对于X方向上的4/1SiO超晶格为0.12，导致比率为0.46。类似地，对于块状硅，对于空穴的计算得出的值为0.36，对于4/1Si/O超晶格得出的值为0.16，导致比率为0.44。
虽然在某些半导体器件中可能期望这种方向上优先的特征，但是其它器件可以从平行于层组的任何方向上的迁移率的更均匀增加中受益。如本领域技术人员将认识到的，对于电子和空穴两者或仅这些类型的电荷载流子之一具有增加的迁移率也可以是有益的。
超晶格25的4/1Si/O实施例的较低电导率有效质量可以小于以其它方式将发生的电导率有效质量的三分之二，并且这适用于电子和空穴两者。当然，也如本领域技术人员将认识到的，超晶格25还可以在其中包括至少一种类型的电导率掺杂剂。
实际上，现在附加地参考图3，现在描述具有不同特性的根据本发明的超晶格25'的另一个实施例。在这个实施例中，示出了3/1/5/1的重复图案。更特别地，最低的基础半导体部分46a'具有三个单层，并且第二最低的基础半导体部分46b'具有五个单层。这种图案在整个超晶格25'上重复。能带改性层50'可以各自包括单个单层。对于包括Si/O的这种超晶格25'，电荷载流子迁移率的增强与层在平面中的取向无关。图3中未具体提及的那些其它元件与以上参考图1讨论的那些元件相似，并且在此无需进一步讨论。
在一些器件实施例中，超晶格的所有基础半导体部分都可以是相同数量的单层那么厚。在其它实施例中，基础半导体部分中的至少一些可以是不同数量的单层那么厚。在其它实施例中，所有的基础半导体部分可以是不同数量的单层那么厚。
在图4A-4C中，呈现了使用密度泛函理论(DFT)计算的能带结构。在本领域中众所周知，DFT低估了带隙的绝对值。因此，可以通过适当的“剪刀校正”来移位间隙上方的所有能带。但是，已经知道能带的形状可靠得多。垂直能量轴应该以这个角度来解释。
图4A示出了对于块状硅(由连续线表示)和对于图1中所示的4/1Si/O超晶格25(由点线表示)两者从伽玛点(G)计算出的能带结构。方向涉及4/1Si/O结构的单元晶胞，而不是Si的常规单元晶胞，但是图中的(001)方向确实与Si的常规单元晶胞的(001)方向对应，因此示出了Si导带最小值的预期位置。图中的(100)和(010)方向与常规Si单元晶胞的(110)和(-110)方向对应。本领域技术人员将认识到的是，图上Si的能带被折叠，以针对4/1Si/O结构在适当的倒易晶格方向上表示它们。
可以看出，与块状硅(Si)相比，用于4/1Si/O结构的导带最小值位于伽玛点处，而价带最小值出现在(001)方向上布里渊区的边缘处，我们称之为Z点。还可以注意到的是，由于由附加氧层引入的扰动引起的能带分裂，与用于Si的导带最小值的曲率相比，用于4/1Si/O结构的导带最小值具有更大的曲率。
图4B示出了对于块状硅(连续线)和4/1Si/O超晶格25(点线)两者从Z点计算出的能带结构。这个图图示了价带在(100)方向上的增强曲率。
图4C示出了对于块状硅(连续线)以及对于图3的超晶格25'的5/1/3/1Si/O结构(点线)，都从伽玛和Z点两者计算得到的能带结构。由于5/1/3/1Si/O结构的对称性，在(100)和(010)方向上计算出的能带结构是等效的。因此，预期电导率有效质量和迁移率在平行于层(即，垂直于(001)堆叠方向)的平面上是各向同性的。注意的是，在5/1/3/1Si/O示例中，导带最小值和价带最大值均在Z点处或其附近。
虽然曲率增加指示有效质量减小，但是可以经由电导率倒数有效质量张量计算来进行适当的比较和判别。这导致申请人进一步在理论上认为5/1/3/1超晶格25'应当基本上是直接带隙。如本领域技术人员将理解的，用于光学跃迁的适当矩阵元素是直接带隙行为与间接带隙行为之间的区别的另一个指标。
使用上述超晶格结构，可以制造半导体器件，其中MST层被定位成小心地约束沟道区域一端上的掺杂剂以创建非对称沟道器件。一个这样的示例是现在参考图5描述的MOSFET 60。MOSFET 60说明性地包括基板61、在基板中限定其间的沟道区域的间隔开的源极区域62和漏极区域63、在源极和漏极区域之间延伸的超晶格25，以及上覆于沟道的栅极64，其中侧壁间隔件65与栅极横向相邻。在不同的实施例中可以使用各种类型的栅极64。在所示示例中，栅极64包括栅极电介质67(例如，SiO2等)和栅电极68(例如，多晶硅)，但是也可以使用诸如替代金属栅极之类的其它栅极结构。在一些实施例中，沟道可以至少部分地在超晶格25中形成或限定，但是不需要在所有实施例中这样。在一些实施例中，超晶格25也可以部分地或完全地凹入在基板21内，或者如所示示例中所示在基板的顶部上。
上述超晶格25的掺杂剂约束能力在本示例中被有利地用于约束位于与源极区域相邻的沟道左侧的延伸区域66(其可以比源极区域62掺杂得更轻)中的掺杂剂。即，仅在沟道区域的一侧植入形成延伸区域66的掺杂剂，并且超晶格25的掺杂剂约束能力有利地防止该区域中的掺杂剂在超晶格形成之后的后续处理过程中“模糊”或越过沟道向漏极63蔓延。源极区域62和延伸区域66在概念上可以被认为是比相对的漏极区域大的一个掺杂区域(这里是源极区域)。应该注意的是，在不同的实施例中，沟道掺杂剂66也可以被约束在沟道区域的相对(即，漏极)侧。
转向图6A-7B和图8的曲线图88，现在提供在具有掺杂沟道的栅极74下方包括MST层25的常规MOSFET 70与具有未掺杂沟道的MOSFET 60之间的比较。MOSFET 70说明性地包括基板71、在其间限定沟道区域的间隔开的源极和漏极区域72、73，以及上覆于沟道区域的超晶格25和栅极74。栅极说明性地包括栅极电介质77和栅电极78。侧壁间隔件75与栅极横向相邻。
在MOSFET 70中，受主掺杂剂存在于沟道中心区域中，如在沟道区域中心处达到峰值的掺杂剂分布79的形状(在MOSFET顶部转置的虚线)所示。该配置导致为MOSFET 70提供单个阈值电压Vt的单个开关80的等效电路图。
作为对照，MOSFET 60仅在靠近源极62侧的延伸区域66中而不在沟道的其余部分中包括受主掺杂剂。这导致在延伸区域达到峰值并且在沟道中心和漏极63区域中与常规的MOSFET 70相比要低得多的掺杂剂分布69。该掺杂剂分布有利地允许Vt控制以及击穿控制，同时还通过消除沟道中心区域中的受主掺杂剂来提高载流子迁移率。此外，这有利地帮助降低相同Vt下的有效场、可以提供提高的迁移率(以及相应地提高驱动电流)，并允许轻掺杂的漏极(LDD)配置以帮助保持热载流子抗扰性，如本领域技术人员人将认识到的。如上所述，MST超晶格25有利地提供准确的掺杂剂扩散控制以允许这种栅极长度缩放，以及进一步提高迁移率。图8中示出了MOSFET60(绘线89)和MOSFET 70(绘线90)的有效场对比迁移率的曲线图88。
MOSFET 60的等效电路图85在图7B中示出。更特别地，等效电路是其中受主掺杂剂定义器件Vt并保持击穿电压(BV)的第一源极侧开关，以及经由低场有利地改善驱动电流的具有相对低Vt而没有掺杂剂的在沟道中心处的第二开关的电路。更特别地，在MOSFET 60的模拟中，TCAD建模预测了适当的20％Idlin和40％Idsat短沟道改进。增加的Idlin是由于通过减少沟道中的有效场改善了迁移率。进一步的Idsat增强是由于漏极63侧的低沟道掺杂降低了体效应。
利用上述结构的5V NMOS器件的实验数据显示，在目标0.7μm栅极长度(Lg)处，与基线和未掺杂沟道控制器件相比，Jdlin/Joff明显改善，从而使Lg从0.7μm降低到～0.25μm。此外，与MOSFET70的5V NMOS基线版本相比，未掺杂的NMOS沟道器件具有25％的改进，以及更低的Joff。此外，MOSFET 60的未掺杂沟道设计在目标0.7um Lg下与基线和未掺杂沟道控制器件相比，在相同Vtlin下也展示出明显的Rsp降低(15％)。此外，除了在目标Lg＝0.7μm下Rsp降低15％外，该器件还显示出>1V的改进的BVDSS，从而允许Lg缩放。更特别地，Imax(和BVDSS，Ioff)和Joff表明可以用MOSFET 60设计实现进一步的Lg缩放以保持在基线目标MOSFET器件70的Imax/BVDSS规格内。此外，匹配的Lg 0.7um器件的Rsp降低15％可以通过MST设计的Lg缩放潜在地增加到50％，同时保持在基线目标器件70的BVDSS和Imax规范内。
根据图9中所示的MOSFET 60'的替代实施例，也可以在沟道区域下方的基板61'内掺杂穿通停止(PTS)植入物91'。现在参考图10的流程图100描述用于制造MOSFET 60和60'的示例方法。在方框101处开始，该方法开始于PTS植入和快速热退火(RTA)，在方框102处(该步骤仅用于MOSFET 60')，随后外延生长MST超晶格25、25'(方框103)，如上所述。应该注意的是，在MST超晶格25'生长之前添加PTS植入物91'可以有利地改进否则由于短沟道效应而受穿通限制的BVDSS。
然后可以形成栅极绝缘体67、67'(例如，SiO2)(方框104)，随后是栅电极68、68'材料的多晶硅化学气相沉积(CVD)(方框105)和栅极图案化(方框106)。再次，应该注意的是，在不同的实施例中，可以使用不同类型的栅极配置(例如，替代金属栅极)。在植入延伸区域66、66'和与延伸区域相对的可选的晕圈(halo)植入(将在下面进一步讨论)之前，可以执行多晶硅栅电极68、68'的再氧化(方框107)，在方框108处，随后是另一个RTA步骤(方框109)。在这个示例中，使用相同的掩模有利地执行LDD和晕圈植入物。该方法进一步说明性地包括方框110处的侧壁间隔件65、65'形成、源极和漏极区域62、62'和63、63'和RTA的植入(方框111-112)，随后是源极/漏极/栅极硅化物以及接触形成和金属化(方框113-114)以完成器件60、60'(方框115)。
另外参考图11的流程图100'，在替代实施例中，图10中所示的步骤108-109可以被改变为首先执行延伸区域66、66'(方框116')，随后是RTA(方框117')，然后是晕圈植入物91'(方框118')和另一个RTA(方框119')。这可以通过在延伸植入物(方框116')和晕圈植入物(方框118')之间插入RTA步骤(方框117')、通过最小化由植入物损伤引入的点缺陷引起的晕圈掺杂剂的非期望TED(瞬态增强扩散)来有利地提供进一步的性能改进/器件缩放。即，该RTA有利地帮助消除由植入物引入的点缺陷以抑制晕圈掺杂剂的非期望的TED。
器件60、60'可以用于多种应用，包括功率开关、射频(RF)开关、CMOS图像传感器、低噪声器件等。更特别地，上述器件配置在减少1/f噪声方面是有效的，因为它们帮助消除沟道中心的掺杂物，从而消除库仑(Coulomb)散射。此外，如上所述，由在延伸和晕圈植入物之间插入RTA所导致的TED抑制也可以有利地对减少噪声有效。此外，引入PTS植入物91'可以有利地帮助改善短沟道控制。
MST超晶格25、25'有利地通过填隙俘获提供掺杂峰锚定和SSR沟道形成。更特别地，在常规的硅基板中，由于OED(氧化增强扩散)，植入物限定的掺杂剂峰被模糊掉。此外，栅极氧化注入Si填隙，而硼和磷扩散由硅填隙介导。MST超晶格25、25'氧单层有利地阻止填隙扩散，并有利地允许在整个制造过程中保留表面未掺杂的沟道。
特别地，在180nm工艺流程中模拟了OED的影响。在该模拟中，打开和关闭栅极氧化热预算以查看OED效果。在PTS植入物和阱RTA之后沉积MST外延膜。模拟表明，OED消除了表面未掺杂的沟道层并降级了短沟道控制。在该模拟中，PTS植入物91'是从180nm节点中的基板61'表面引入～0.15um。为防止深源极/漏极区域(Xj～0.2um)之间的穿通，Xj在55nm节点中进行缩放。
在另一个示例实施例中，可以通过仅在器件的漏极侧而不是源极侧包括延伸植入物来提高短沟道器件的热载流子可靠性。即，跳过源极侧延伸植入物可以有利地增加Leff(有效栅极长度)。此外，增加的Leff会增加Vdsat以降低碰撞电离率，从而提高热载流子可靠性。热载流子退化是由Vd-Vdsat驱动的，随着栅极长度的缩短，Vd-Vdsat增加。较低剂量的源极侧LDD会增加Leff，从而改善热载流子注入。
在一些实施例中，P-体层可以并入在MOSFET 60、60'中(例如，用于功率开关器件配置)以避免热载流子抗扰性。即，P-体层降低了体电阻而避免通过碰撞电离经由较低的IR压降产生的空穴的积累。但是，当P-体层太浅时，它会降级BVDSS。从实验数据得出的结论是，对于180nm工艺，可以用于维持期望BVDSS的P-体层深度>0.6μm，但是在不同的配置中可能有不同的尺度。
现在将参考图12-15描述包括P-阱/P-体区域的器件的示例。更特别地，图12的MOSFET 120是低压漏极延伸金属氧化物半导体(LV-DEMOS)器件，其说明性地包括基板121、PTS层130(P-resurf/APT)、源极和漏极区域122、123、LDD源极延伸131、在源极和LDD源极延伸下方/周围的P-阱/P-体植入物132，以及在漏极下方/周围的漏极延伸区域126(N-漂移)。延伸区域126延伸超过沟道的一半(如长度La所示)以限定如上所述的非对称沟道。MST超晶格125上覆于沟道区域，并且栅极124上覆于MST超晶格并且说明性地包括栅极电介质127和栅电极128。此外，侧壁间隔件140与栅极124横向相邻，并且还提供相应的源极、漏极和栅极触点133、135、135，以及可以用于将晶片上的一个MOSFET 120与下一个隔离的浅沟槽隔离(STI)区域区136。
图13中示出了另一类似的DEMOS器件120'。器件120'类似于上述的LV-DEMOS器件120，但其在沟道和漏极123'之间包括增加的长度(Ld)。图14中示出了还有的另一个示例LDMOS 120”。LDMOS 120”类似于DEMOS 120'，但还包括位于基板121”中漏极123”和沟道区域之间的STI/LOCOS区域137'，以及如图所示在STI/LOCOS区域周围的N-漂移区域126”。
通过上述配置，使用倾斜的LDD植入物有利地使得能够对由于较低的寄生基极电阻而增加的坚固性进行工程设计。此外，使用晕圈/P-阱植入物有利地使得能够对较低Ron进行工程设计，因为可以通过改变间距La来独立地控制到P-体的间距。P-resurf层130使得能够对优化的Ron与击穿电压(BV)进行工程设计。
上述器件120-120”在具有相对低的体电阻的高坚固性配置中有利地提供低Ron。在制造过程中，两个掩模可以用于源极和漏极植入物。Pwell/N-漂移区域132、126使得能够在流程中重用现有植入物并优化Ron和HCI的横向尺度。
一般而言，可以通过两种方法实现更短的拉制沟道或栅极长度(Lg)。第一种方法是零度源极侧LDD植入物，从而减少横向侵占。另一种方法涉及使用双侧壁间隔件。更特别地，第一间隔件将LDD与栅极边缘间隔开(即，在第一间隔件形成之后执行源极LDD植入物)，但横向蔓延导致栅极附近足够的掺杂以帮助确保器件一致且可控的Vt。第二间隔件将源极植入物与栅极边缘间隔开(即，在形成第二栅极侧壁之后执行源极/漏极植入物)。
应该注意的是，虽然在平面MOSFET器件的背景下描述了上述技术，但是它们也可以与其它器件配置，诸如在不同实施例中的垂直(例如，FINFET)器件结合使用，如本领域技术人员将认识到的。关于MST膜的掺杂剂约束能力的更多细节在授予Mears等人的美国专利No.9,941,359中阐述，该专利已转让给本申请人并在此通过引用整体并入本文。
受益于前述描述和相关附图中呈现的教导，本领域技术人员将想到本发明的许多修改和其它实施例。因此，应该理解的是，本发明不限于所公开的具体实施例，并且修改和实施例旨在被包括在所附权利要求书的范围内。

Claims (22)

1.一种半导体器件，包括：
基板；
在基板中的间隔开的第一掺杂区域和第二掺杂区域，第一掺杂区域大于第二掺杂区域以在它们之间限定非对称沟道；
在第一掺杂区域和第二掺杂区域之间延伸以约束其中的掺杂剂的超晶格；
所述超晶格包括多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被约束在相邻基础半导体部分的晶格内的至少一个非半导体单层；以及
上覆于非对称沟道的栅极。
2.如权利要求1所述的半导体器件，其中所述第一区域包括漏极区域，并且所述第二区域包括源极区域。
3.如权利要求1所述的半导体器件，其中所述超晶格上覆于所述第一掺杂区域的至少一部分。
4.如权利要求1所述的半导体器件，其中所述非对称沟道至少部分地在所述超晶格内。
5.如权利要求1所述的半导体器件，还包括基板中的在所述非对称沟道下方的穿通停止植入物。
6.如权利要求1的半导体器件，其中所述第一掺杂区域和第二掺杂区域具有第一导电类型；并且所述半导体器件还包括阱植入物，该阱植入物被与所述第二掺杂区域相邻的超晶格约束在所述基板内且具有与所述第一导电类型不同的第二导电类型。
7.如权利要求6所述的半导体器件，其中所述第一掺杂区域在所述栅极下方横向延伸超过所述非对称沟道的中心。
8.如权利要求1所述的半导体器件，其中所述栅极包括上覆于所述超晶格的栅极电介质和上覆于所述栅极介电层的栅电极。
9.如权利要求1所述的半导体器件，还包括在所述基板上的与所述栅极横向相邻的侧壁间隔件。
10.如权利要求1所述的半导体器件，其中所述基础半导体单层包括硅单层。
11.如权利要求1所述的半导体器件，其中所述至少一个非半导体单层包含氧。
12.一种用于制造半导体器件的方法，包括：
在基板中形成间隔开的第一掺杂区域和第二掺杂区域，所述第一掺杂区域大于所述第二掺杂区域以在它们之间限定非对称沟道；
形成在所述第一掺杂区域和第二掺杂区域之间延伸以约束其中的掺杂剂的超晶格；
所述超晶格包括多个堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层，以及被约束在相邻基础半导体部分的晶格内的至少一个非半导体单层；以及
形成上覆于非对称沟道的栅极。
13.如权利要求12所述的方法，其中所述第一区域包括漏极区域，并且所述第二区域包括源极区域。
14.如权利要求12所述的方法，其中形成所述超晶格包括形成上覆于所述第一掺杂区域的至少一部分的超晶格。
15.如权利要求12所述的方法，其中所述非对称沟道至少部分在所述超晶格内。
16.如权利要求12所述的方法，还包括在所述非对称沟道下方的基板中形成穿通停止植入物。
17.如权利要求12所述的方法，其中所述第一掺杂区域和第二掺杂区域具有第一导电类型；并且所述方法还包括形成阱植入物，该阱植入物被与第二掺杂区域相邻的超晶格约束在所述基板内且具有与所述第一导电类型不同的第二导电类型。
18.如权利要求17所述的方法，其中所述第一掺杂区域在所述栅极下方横向延伸超过所述非对称沟道的中心。
19.如权利要求12所述的方法，其中形成所述栅极包括形成上覆于所述超晶格的栅极电介质，以及形成上覆于所述栅极介电层的栅电极。
20.如权利要求12所述的方法，还包括在所述基板上形成与所述栅极横向相邻的侧壁间隔件。
21.如权利要求12所述的方法，其中所述基础半导体单层包括硅单层。
22.如权利要求12所述的方法，其中所述至少一个非半导体单层包含氧。
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