CN113889525A - 提升耐压工艺窗口的超结器件 - Google Patents

提升耐压工艺窗口的超结器件 Download PDF

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CN113889525A
CN113889525A CN202111487782.2A CN202111487782A CN113889525A CN 113889525 A CN113889525 A CN 113889525A CN 202111487782 A CN202111487782 A CN 202111487782A CN 113889525 A CN113889525 A CN 113889525A
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李吕强
陈辉
王加坤
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Abstract

本发明提供一种提升耐压工艺窗口的超结器件，包括：半导体衬底；沉积于半导体衬底上的外延层，外延层包括第一半导体层及层叠于其上的第二半导体层，且第一半导体层的禁带宽度大于第二半导体层的禁带宽度；形成于外延层中的超结结构，超结结构包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，第一外延柱与第二外延柱横向交替排布。通过采用具有夹层结构的外延层制备超结结构，由于下层的禁带宽度大于上层的禁带宽度，当超结结构在中部区域电场高于两端的电场时，由于第一半导体层的临界电场大于第二半导体层的临界电场，可以保证中部区域不提前击穿，从而可以在保证超结结构的高耐压下扩大耐压工艺窗口。

Description

提升耐压工艺窗口的超结器件
技术领域
本发明涉及半导体功率器件结构技术领域，特别是涉及一种提升耐压工艺窗口的超结器件。
背景技术
超结（Super Junction）结构是基于电荷平衡技术采用交替的PN结结构取代单一导电类型材料作为漂移区，在漂移区引入横向电场，使得器件漂移区在较小的关断电压下即可完全耗尽，击穿电压仅与耗尽层厚度及临界电场有关。因此，在相同耐压条件下，超结结构漂移区的掺杂浓度可以提高一个数量级，大大降低了导通电阻。
超结结构能够实现较高的击穿电压关键在于P区域和N区域的电荷平衡，当P区域和N区域的电荷平衡时超结结构可以得到较高的击穿电压，而当P区域和N区域的电荷失去平衡，则会导致击穿电压迅速降低。然而，在实际的工艺制备过程中，很难做到电荷平衡的P区域和N区域。目前常采用通过控制超结沟槽倾斜角或渐变掺杂分布梯度，抬升超结结构中部区域的电场，使超结结构两端区域的电场降低，以达到扩展器件耐压工艺窗口的效果，但是由于超结结构中部区域的过强电场也会导致器件更易击穿，导致器件耐压的降低。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种提升耐压工艺窗口的超结器件，用于解决现有技术中超结结构由于中部区域的过强电场会使器件更易击穿，导致耐压降低等的问题。
为实现上述目的及其他相关目的，本发明提供一种提升耐压工艺窗口的超结器件，所述超结器件包括：
半导体衬底；
沉积于所述半导体衬底上的外延层，所述外延层包括第一半导体层及层叠于其上的第二半导体层，且所述第一半导体层的禁带宽度大于所述第二半导体层的禁带宽度；
形成于所述外延层中的超结结构，所述超结结构包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，且所述超结结构沿所述第二半导体层上表面向下至少延伸至所述第一半导体层的下表面，其中，所述第一导电类型与所述第二导电类型相反。
可选地，所述半导体衬底为硅衬底，所述第一半导体层的材料为碳化硅或金刚石，所述第二半导体层的材料为硅。
进一步地，所述第一半导体层的厚度大于所述第二半导体层的厚度。
可选地，所述外延层还包括位于所述第一半导体层下表面的第三半导体层，且所述超结结构沿所述第二半导体层上表面向下延伸至所述第三半导体层的下表面，所述第一半导体层的禁带宽度大于所述第三半导体层的禁带宽度。
进一步地，所述半导体衬底为硅衬底，所述第一半导体层的材料为碳化硅或金刚石，所述第二半导体层的材料为硅，所述第三半导体层的材料为硅。
进一步地，所述第一半导体层的厚度大于所述第二半导体层的厚度，且大于所述第三半导体层的厚度。
可选地，所述第一外延柱及所述第二外延柱为互补的倾斜柱。
可选地，所述第一导电类型为N型或P型，所述第二导电类型为P型或N型。
可选地，所述超结器件应用于超结二极管器件中，或IGBT中，或VDMOS中。
如上所述，本发明的提升耐压工艺窗口的超结器件，通过采用具有夹层结构的外延层制备超结结构，由于下层的第一半导体层的禁带宽度大于上层的第二半导体层的禁带宽度，从而可提高第一半导体层所在区域的临界电场，当超结结构在中部区域电场高于两端的电场时，由于第一半导体层的临界电场大于第二半导体层的临界电场，可以保证中部区域不提前击穿，从而可以在保证超结结构的高耐压下扩大耐压工艺窗口。
附图说明
图1显示为现有技术中超结沟槽未倾斜的超结结构及其位置与电场的分布示意图。
图2显示为现有技术中超结沟槽倾斜的超结结构及其位置与电场的分布示意图。
图3显示为本发明一示例的提升耐压工艺窗口的超结器件结构示意图。
图4显示为本发明另一示例的提升耐压工艺窗口的超结器件及其位置与电场的分布结构示意图。
图5显示为现有技术中超结沟槽倾斜的超结结构及其位置与电场的分布示意图，其中超结结构所在的外延层材料为硅。
元件标号说明
10-半导体衬底，11-外延层，111-第一半导体层，112-第二半导体层，113-第三半导体层，121-第一外延柱，122-第二外延柱，13- P型区，14-金属引出层。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图5。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可根据实际需要进行改变，且其组件布局型态也可能更为复杂。
如背景技术中所述，超结结构是基于电荷平衡技术形成的耐高压器件，如图1所示，当超结结构中的所有P区域和所有N区域的电荷平衡时，超结结构可以得到很高的击穿电压Vb。而在实际工艺中很难做到P区域和N区域之间电荷的平衡，为了避免该非平衡导致击穿电压的迅速降低，目前常采用将超结结构的沟槽设置为倾斜槽，如图2所示，将超结沟槽设置为θ角的倾斜，将超结结构中部区域的电场抬升，使超结结构上下两端区域的电场降低，以达到扩展器件耐压工艺窗口的效果；另外还可通过将超结结构从上向下设置为渐变掺杂分布梯度，例如，P柱掺杂上高下低，N柱掺杂上低下高，也可以将超结结构中部区域的电场抬升，使超结结构上下两端区域的电场降低。虽然通过将中部区域的电场抬升可以达到扩展器件耐压工艺窗口的效果，但是中部区域的过强电场也会导致器件更易击穿，拉低器件的耐压性能。
基于以上问题，发明人从如何提高中部区域的耐压性能的角度出发，提出一种提升耐压工艺窗口的超结器件，在保证器件高耐压下扩大器件的耐压工艺窗口。这里的耐压工艺窗口指的是，定义超结器件中P柱与N柱内部的电荷总量比为电荷非平衡度，当P柱/N柱内部电荷总量相等，即电荷平衡时，器件可取得最高的击穿电压BVmax，如此，耐压工艺窗口可表述为器件耐压值可维持在BVmax~预设百分比*BVmax范围内的电荷非平衡度的范围。
如图3所示，本实施例提出的提升耐压工艺窗口的超结器件包括：半导体衬底10；沉积于所述半导体衬底10上的外延层11，所述外延层11包括第一半导体层111及层叠于其上的第二半导体层112，且所述第一半导体层111的禁带宽度大于所述第二半导体层112的禁带宽度；形成于所述外延层11中的超结结构，所述超结结构包括至少一个第一导电类型的第一外延柱121及至少一个第二导电类型的第二外延柱122，所述第一外延柱121与所述第二外延柱122横向交替排布，且所述超结结构沿所述第二半导体层112上表面向下至少延伸至所述第一半导体层111的下表面，其中，所述第一导电类型与所述第二导电类型相反。
本实施例通过采用具有夹层结构的外延层制备超结结构，由于下层的第一半导体层的禁带宽度大于上层的第二半导体层的禁带宽度，从而可提高第一半导体层所在区域的临界电场，当超结结构在中部区域电场高于两端的电场时，由于第一半导体层的临界电场大于第二半导体层的临界电场，可以保证中部区域不提前击穿，从而可以在保证超结结构的高耐压下扩大耐压工艺窗口。
如图4所示，作为示例，所述外延层11还可以在所述第一半导体层111下面设置第三半导体层113，所述超结结构沿所述第二半导体层112上表面向下延伸至所述第三半导体层113的下表面，所述第一半导体层111的禁带宽度大于所述第三半导体层113的禁带宽度。即在两窄禁带宽度的半导体层之间增加一宽禁带宽度的半导体层，沿超结结构厚度的方向Y，当其两端区域的电场小于中部区域的电场时，超结结构的耐压主要落在中部区域上，而中部区域采用禁带宽度大的半导体材料层，所以中部区域半导体材料层的临界电场可得到有效提高，从而可以保证中部区域不被提前击穿，达到可以在保证高耐压下扩大耐压工艺窗口。
具体地，可参考图4及图5，图4中外延层由下向上结构为硅材料层（第三半导体层113）、碳化硅材料层（第一半导体层111）及硅材料层（第二半导体层112），图5中外延层11由单独的硅材料层形成。单纯使用硅材料层作为超结结构的半导体材料层，由于硅的禁带宽度小于碳化硅的禁带宽度，因而碳化硅的临界电场大于硅的临界电场，所以在图5中，超结结构中部区域的临界电场值由硅材料的最大电场承受值Ec（Si）决定，当超结结构中部区域的电场值大于Ec（Si）时，超结结构则面临被击穿的风险，而在图4中，超结结构中部区域的临界电场值由碳化硅材料的最大电场承受值Ec（SiC）决定，当超结结构中部区域的电场值大于Ec（Si）时，超结结构还是具有一定的抗击穿能力，保证超结结构不会提前击穿，达到可以在保证高耐压下扩大耐压工艺窗口的效果。
如上所述，本实施例的超结器件较佳地可以应用于所述半导体衬底为硅衬底，当所述外延层11为双层叠层时，所述第一半导体层111的材料为碳化硅或金刚石，所述第二半导体层112的材料为硅（如图3所示）；当所述外延层11为三层叠层时，所述第一半导体层111的材料为碳化硅或金刚石，所述第二半导体层112的材料为硅，所述第三半导体层113的材料为硅（如图4所示）。考虑不同材料之间的晶格匹配与热匹配参数，所述第一半导体层111的材料优选选择为碳化硅。
如图3及图4所示，作为示例，当所述外延层11为双层叠层时，所述第一半导体层111的厚度大于所述第二半导体层112的厚度；当所述外延层11为三层叠层时，所述第一半导体层111的厚度大于所述第二半导体层112的厚度，且大于所述第三半导体层113的厚度。
如图3及图4所示，于所述外延层11中形成的超结结构，包括所述第一外延柱121及第二外延柱122可以为互补的倾斜柱，即第一外延柱121与第二外延柱122的倾斜方向互相相反。但也不限于此，所述述第一外延柱121及第二外延柱122也可以为没有倾斜的外延柱，可通过将外延柱从上向下设置为渐变掺杂分布梯度，以使超结结构的中部区域的电场大于两端区域的电场。
作为一具体示例，所述外延层11通过多次外延工艺形成，所述超结结构可通过离子注入的方式形成，也可通过先沟槽刻蚀再外延填充的方式形成，但也不限于此，任意现有制备超结结构的工艺均可应用于本实施例中。
本实施例中，所述第一导电类型与所述第二导电类型的导电类型相反，例如，当所述第一导电类型为N型，则所述第二导电类型为P型；当所述第一导电类型为P型，则所述第二导电类型为N型。
本实施例提出的超结器件尤其适用于超结二极管器件中，或IGBT器件中，或VDMOS器件中。如图3及图4所示，即为在超结二极管器件中的应用，其中，半导体衬底10为N型掺杂的N型区，超结结构之上为P型掺杂的P型区13，N型区及P型区13两端分别为金属引出层14。IGBT器件及VDMOS器件也为现有常规结构器件，其具体结构在此不再赘述。
综上所述，本发明提供一种提升耐压工艺窗口的超结器件，通过采用具有夹层结构的外延层制备超结结构，由于下层的第一半导体层的禁带宽度大于上层的第二半导体层的禁带宽度，从而可提高第一半导体层所在区域的临界电场，当超结结构在中部区域电场高于两端的电场时，由于第一半导体层的临界电场大于第二半导体层的临界电场，可以保证中部区域不提前击穿，从而可以在保证超结结构的高耐压下扩大耐压工艺窗口。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (9)

1.一种提升耐压工艺窗口的超结器件，其特征在于，所述超结器件包括：
半导体衬底；
沉积于所述半导体衬底上的外延层，所述外延层包括第一半导体层及层叠于其上的第二半导体层，且所述第一半导体层的禁带宽度大于所述第二半导体层的禁带宽度；
形成于所述外延层中的超结结构，所述超结结构包括至少一个第一导电类型的第一外延柱及至少一个第二导电类型的第二外延柱，所述第一外延柱与所述第二外延柱横向交替排布，且所述超结结构沿所述第二半导体层上表面向下至少延伸至所述第一半导体层的下表面，其中，所述第一导电类型与所述第二导电类型相反。
2.根据权利要求1所述的提升耐压工艺窗口的超结器件，其特征在于：所述半导体衬底为硅衬底，所述第一半导体层的材料为碳化硅或金刚石，所述第二半导体层的材料为硅。
3.根据权利要求2所述的提升耐压工艺窗口的超结器件，其特征在于：所述第一半导体层的厚度大于所述第二半导体层的厚度。
4.根据权利要求1所述的提升耐压工艺窗口的超结器件，其特征在于：所述外延层还包括位于所述第一半导体层下表面的第三半导体层，且所述超结结构沿所述第二半导体层上表面向下延伸至所述第三半导体层的下表面，所述第一半导体层的禁带宽度大于所述第三半导体层的禁带宽度。
5.根据权利要求4所述的提升耐压工艺窗口的超结器件，其特征在于：所述半导体衬底为硅衬底，所述第一半导体层的材料为碳化硅或金刚石，所述第二半导体层的材料为硅，所述第三半导体层的材料为硅。
6.根据权利要求5所述的提升耐压工艺窗口的超结器件，其特征在于：所述第一半导体层的厚度大于所述第二半导体层的厚度，且大于所述第三半导体层的厚度。
7.根据权利要求1所述的提升耐压工艺窗口的超结器件，其特征在于：所述第一外延柱及所述第二外延柱为互补的倾斜柱。
8.根据权利要求1所述的提升耐压工艺窗口的超结器件，其特征在于：所述第一导电类型为N型或P型，所述第二导电类型为P型或N型。
9.根据权利要求1所述的提升耐压工艺窗口的超结器件，其特征在于：所述超结器件应用于超结二极管器件中，或IGBT中，或VDMOS中。
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KR101167530B1 (ko) * 2012-01-05 2012-07-20 주식회사 시지트로닉스 수퍼 헤테로 접합 반도체소자 및 그 제작방법
CN104779290A (zh) * 2014-01-10 2015-07-15 瑞萨电子株式会社 半导体器件
CN107275383A (zh) * 2017-06-22 2017-10-20 四川大学 一种含有异质结的超结igbt

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Publication number Priority date Publication date Assignee Title
KR101167530B1 (ko) * 2012-01-05 2012-07-20 주식회사 시지트로닉스 수퍼 헤테로 접합 반도체소자 및 그 제작방법
CN104779290A (zh) * 2014-01-10 2015-07-15 瑞萨电子株式会社 半导体器件
CN107275383A (zh) * 2017-06-22 2017-10-20 四川大学 一种含有异质结的超结igbt

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