CN113889419A - 具有暴露的集成电路管芯的无带引线框封装件 - Google Patents

具有暴露的集成电路管芯的无带引线框封装件 Download PDF

Info

Publication number
CN113889419A
CN113889419A CN202110735508.6A CN202110735508A CN113889419A CN 113889419 A CN113889419 A CN 113889419A CN 202110735508 A CN202110735508 A CN 202110735508A CN 113889419 A CN113889419 A CN 113889419A
Authority
CN
China
Prior art keywords
integrated circuit
circuit die
tapeless
protrusion
leadframe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110735508.6A
Other languages
English (en)
Inventor
A·卡达格
R·K·塞拉皮奥
E·M·卡达格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of CN113889419A publication Critical patent/CN113889419A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8184—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本公开的各实施例涉及具有暴露的集成电路管芯的无带引线框封装件。无带引线框封装件的第一侧被蚀刻以形成环形突起以及从基底层延伸的引线突起。集成电路管芯以倒装芯片定向而被安装到无带引线框封装件，其中前侧面向第一侧。电气和机械附接件在集成电路管芯的键合焊盘与引线突起之间制成。机械附接件在集成电路管芯的前侧与环形突起之间制成。集成电路管芯和来自无带引线框封装件的突起被包封在包封块内。无带引线框封装件的第二侧然后被蚀刻来去除基底层的部分并且从引线突起限定用于引线框的引线，并且还从环形突起限定用于引线框的管芯支撑件。

Description

具有暴露的集成电路管芯的无带引线框封装件
相关申请的交叉引用
本申请要求于2020年7月1日提交的第63/046,838号美国专利临时申请的优先权，其公开内容通过引用并入本文。
技术领域
本发明总体上涉及集成电路封装件，并且具体地涉及利用支持暴露的集成电路管芯的无带(tapeless)引线框封装件的集成电路封装件。
背景技术
集成电路封装件包括引线框、安装到引线框的管芯焊盘并且被电连接到引线框的引线的集成电路管芯、以及围绕集成电路管芯来提供一定水平的物理保护的包封体。本领域已知有若干类型的引线框。特别令人感兴趣的是被用于制造四方扁平无引线(QFN)集成电路封装件的引线框。在该配置中，引线框的引线不延伸超出包封体的外周。支撑集成电路管芯的管芯焊盘可以具有或可以不具有从包封体暴露的表面(即，与集成电路管芯被安装的表面相对)。
在许多应用中，集成电路管芯从包封体暴露很重要。例如，如果集成电路管芯包括诸如光学传感器的环境传感器，则该传感器不能被包封体的通常不透明材料覆盖。然而，在QFN集成电路封装件中提供集成电路管芯的暴露是一个挑战。图1A示出了QFN集成电路封装件10的截面图，其包括具有管芯焊盘14和引线16的引线框12、粘附地安装到管芯焊盘14的上表面的光学集成电路管芯18、从集成电路管芯18的前侧上的键合焊盘延伸到引线16的键合线20。例如由玻璃材料制成的保护(钝化)层28在集成电路管芯18的前侧之上延伸，其中保护层28覆盖光学传感器26并且包括将集成电路管芯18前侧上的键合焊盘暴露来支持键合线连接的开口。包封体22围绕集成电路管芯。开口24从包封体22的前侧延伸到包封体22中，以暴露光学传感器26的位置。图1B和图1C分别示出了QFN集成电路封装件10的等距前侧和后侧视图。
图1A-图1C中示出了关于封装件解决方案的若干问题。包封体22在传递模制工艺中形成，其中模制工具包括在开口24形成的位置处的弹簧加载插入件。该弹簧加载插入件产生管芯裂纹。附加地，模具溢料可能形成在管芯的暴露面积上并且至少部分地覆盖光学传感器26。由于键合线的存在，制造工艺还引入了对封装件厚度的限制。制造过程也很昂贵，因为它需要专用且昂贵的模制工具、使用脱模薄膜以及借助键合线工艺将管芯电连接到引线。
本领域需要解决上述问题。
发明内容
在一个实施例中，方法包括：蚀刻无带引线框封装件的第一侧，以形成从基底层延伸的第一突起和第二突起；以倒装芯片定向来安装集成电路管芯，其中集成电路管芯的前侧面向无带引线框封装件的第一侧，其中安装包括将集成电路管芯的键合焊盘电气地和机械地附接到第一突起并且将集成电路管芯的前侧机械地附接到第二突起；利用包封材料来包封集成电路管芯以及第一突起和第二突起；以及蚀刻无带引线框封装件的第二侧，来去除基底层的部分并且从第一突起限定用于引线框的引线，并且还从第二突起限定用于引线框的管芯支撑件。
在一个实施例中，无带引线框封装件包括：基底层，具有第一侧和第二侧；第一突起，在第一侧处从基底层延伸；第二突起，在第一侧处从基底层延伸；第一镀层，位于第一侧处，所述第一镀层具有第一图案，该第一图案限定第一突起的尺寸和形状以及第二突起的尺寸和形状；以及第二镀层，位于第二侧处，第二层具有第二图案；其中第一镀层的第一图案与第二镀层的第二图案相同并且彼此对准。
在一个实施例中，集成电路封装件包括：无带引线框，其包括环形管芯支撑件以及多个引线，多个引线以围绕环形管芯支撑件的规则图案而被布置，其中环形管芯支撑件围绕由环形管芯支撑件的内周边界定的开放区域；集成电路管芯，以倒装芯片定向而被安装到无带引线框，其中集成电路管芯的前侧面向无带引线框的第一侧；电气和机械附接件，位于集成电路管芯的键合焊盘与多个引线中的对应引线之间；机械附接件，位于集成电路管芯的前侧与环形管芯支撑件之间，其中集成电路管芯包括环境传感器，并且其中环形管芯支撑件的开放区域与环境传感器对准；以及包封块，在不覆盖开放区域的情况下，将集成电路管芯、多个引线和环形管芯支撑件包封。
附图说明
为了更好地理解实施例，现在将仅通过示例的方式来参考附图，其中：
图1A是本领域已知的四方扁平无引线(QFN)集成电路封装件的截面图；
图1B和图1C是图1A的QFN集成电路封装件的等距视图；
图2A是QFN集成电路封装件的截面图；
图2B和图2C是图2A的QFN集成电路封装件的等距视图；
图3A是裸露无带引线框封装件的截面图；
图3B是图3A的裸露无带引线框封装件的等距视图；
图4A是具有导电烧结材料涂层的裸露无带引线框封装件的截面图；
图4B是图4A的裸露无带引线框封装件的等距视图；
图5A是示出了集成电路管芯到无带引线框封装件的附接件的截面图；
图5B是图5A中所示结构的等距视图；
图6A是示出了集成电路管芯的包封与无带引线框封装件的附接件的截面图；
图6B-图6C是图6A所示结构的等距视图；以及
图7A-图7E图示了用于制造多个集成电路封装件的过程步骤序列。
具体实施方式
现在参考图2A，图2A示出了QFN集成电路封装件100的截面图，QFN集成电路封装件100包括：具有中空管芯环114和多个引线116的引线框112；以“倒装芯片(flip chip)”配置而被安装到管芯环114的上表面的集成电路管芯118，其中在集成电路管芯118的前侧上的键合焊盘面向引线框112；以及从集成电路管芯118的前侧上的键合焊盘延伸到多个引线116的键合柱120。例如由玻璃材料制成的保护(钝化)层128在集成电路管芯118的前侧之上延伸，其中保护层128包括开口，开口暴露集成电路管芯118的前侧上的键合焊盘来支持键合柱120的连接。包封体122围绕集成电路管芯。由中空管芯环114的内周边限定(即，被管芯环围绕)的开口124从封装件的背侧延伸，以暴露环境传感器(诸如例如，集成电路管芯118的光学传感器126或压力传感器)的位置。管芯环114提供用于将集成电路管芯118支撑和安装到引线框112的结构。图2B和图2C分别示出了QFN集成电路封装件110的等距前侧和背侧视图。
图3A到图6C示出了制造如图2A-图2C中所示的QFN集成电路封装件100的过程中的步骤。
现在参考图3A，图3A示出了在第一侧202上被蚀刻以形成环形突起204以及从基底层205垂直延伸的多个引线突起206之后，裸露无带引线框封装件112’的截面图。多个引线突起206以围绕环形突起204的规则图案而被布置(规则图案包括例如阵列图案，在突起之间提供规则节距和/或提供经布置的突起组)。因此，环形突起204具有环形形状，环形形状具有外周边和内周边，并且多个引线突起206在环外部，被定位在偏离外周边的一定距离处。环形突起204和多个引线突起206的顶表面与基底层205具有相同的高度偏移。第一镀层208被提供在环形突起204的顶表面和多个引线突起206的顶表面上，其中该镀层208已被图案化来限定环形突起204和多个引线突起206的尺寸和形状，并且还被用作与第一侧202的选择性蚀刻相关的掩模。第二镀层210被提供在裸露无带引线框封装件112’的第二侧212上。应注意，该第二镀层210被相同地图案化并且被定位为与第一镀层208对准，以包括环形部分214(与镀层208限定环形突起204的部分对准并具有相同的尺寸和形状)和多个引线部分216(与镀层208限定多个引线突起206的部分对准并具有相同的尺寸和形状)。图3B示出了图3A的裸露无带引线框封装的等距前侧(即，第一侧)视图。
导电烧结材料220被沉积为与环形突起204和多个引线突起206顶部上的镀层208接触。该过程步骤的结果在图4A的截面图以及图4B的等距视图中示出。
接着，集成电路管芯118被安装到无带引线框封装件112’。该过程步骤的结果被示出在图5A的截面视图和图5B的等距视图中。
集成电路管芯118包括背侧222和前侧224。集成电路管芯118的半导体衬底226在集成电路管芯118的背侧210处具有后表面并且具有提供集成电路的前表面，这些集成电路包括环境(例如，光学)传感器126。衬底226的前表面之上的互连层228包括用于将衬底226上的集成电路互连的布线连接(未明确示出)并且还包括用于支持外部电连接的键合焊盘230。例如由玻璃材料制成的保护(钝化)层128被安装到互连层228。层128的前表面限定了集成电路管芯118的前侧224。开口被包括在保护层128中，以暴露键合焊盘230。
集成电路管芯118以“倒装芯片”配置被安装到无带引线框封装件112’，其中集成电路管芯118的前侧224面向裸露无带引线框封装件112’的第一侧202。具体地，集成电路管芯118利用键合焊盘230来布置，键合焊盘230与多个引线突起206对准。每个键合焊盘230与对应引线突起206的镀层208之间插入的导电烧结材料220在固化之后，形成键合柱120，键合柱120在集成电路管芯118与无带引线框封装件112’之间提供电气和机械互连件。此外，在层128的前表面与环形突起204的镀层208之间插入的导电烧结材料220在固化之后形成安装附接件234，安装附接件234在集成电路管芯118与无带引线框封装件112’之间提供机械互连件(也可以支持电连接)。这将开放区域238有效地密封，开放区域238由环形突起204以及基底层205与环境(光学)传感器126的位置对准的一部分来界定。环形突起204支持将集成电路管芯118安装到引线框。应注意，保护层128将在管芯附接到无带引线框封装件112’期间，保护管芯的集成电路，特别是环境(光学)传感器免受导电烧结材料220的影响。
接着，传递模制过程被执行以将集成电路管芯118和无带引线框封装件112’嵌入在包封体122中。该过程步骤的结果分别在图6A的截面图和图6B和图6C的等距前视图和后视图中示出。图5A-图5B中所示的结构被插入到模具腔内并且包封材料(诸如不透明环氧树脂)被注入到模具腔中。包封材料将围绕集成电路管芯118并填充引线突起206之间以及环形突起204与引线突起206之间的任何开放空间。应注意，由于开放区域238被密封，因此包封材料不会流入开放区域，并且环境(光学)传感器126被保护免于被包封剂无意地覆盖。通过传递模制过程生产的经包封的结构然后从模具中被移除。
接着，蚀刻在无带引线框封装件112’的第二侧212处被执行。除了基底层205中的、由第二镀层210的环形部分214和多个引线部分216保护的那些部分之外，该蚀刻去除了所有基底层205，以形成引线框112的管芯环114和引线116。蚀刻在基底层205的不期望部分被去除并且包封体122被到达时终止。基底层205的蚀刻使得开放区域238解封并暴露环境(光学)传感器126。管芯环114用作用于将集成电路管芯安装到引线框112的管芯支撑结构。将注意到，保护层128将保护管芯的集成电路，特别是环境(光学)传感器，免受用于蚀刻基底层205的不期望部分的蚀刻剂的影响。该过程步骤的结果分别在图2A的截面图和图2B和图2C的等距前视图和后视图中示出。
应当理解，制造过程通常在大规模基础上执行。这在图7A-图7E中示出。图7A对应于图3A中所示的过程步骤，不同之处在于示出了更大范围的裸露无带引线框封装件112’(在该特定图示中，示出了引线框的两个区段300a和300b)。图7B对应于图5A中所示的过程步骤，其中集成电路管芯118被安装在无带引线框封装件112’的每个区段300a、300b中。图7C对应于图6A所示的过程步骤。应注意，传递模制操作在如图7B所示的整个结构上执行。图7D对应于在无带引线框封装件112’的第二侧212上执行蚀刻的步骤。在从模具中移除之后，如图7C所示，该蚀刻在整个结构上执行。为了形成单独的集成电路封装件，切单操作然后通过沿着穿过包封体122的线302切割来执行。切单操作的结果连同单独的集成电路封装件304的产生在图7E中示出。
虽然已在附图和前面的描述中详细图示和描述了本发明，但是这样的图示和描述被认为是例示性的或示例性的而不是限制性的；本发明不限于所公开的实施例。通过研究附图、公开内容和所附权利要求，本领域技术人员在实践所要求保护的本发明时，可以理解和实现对所公开的实施例的其他变化。

Claims (28)

1.一种方法，包括：
蚀刻无带引线框封装件的第一侧，以形成从基底层延伸的第一突起和第二突起；
以倒装芯片定向来安装集成电路管芯，其中所述集成电路管芯的前侧面向所述无带引线框封装件的所述第一侧，其中安装包括将所述集成电路管芯的键合焊盘电气地和机械地附接到所述第一突起并且将所述集成电路管芯的所述前侧机械地附接到所述第二突起；
利用包封材料来包封所述集成电路管芯以及所述第一突起和所述第二突起；以及
蚀刻所述无带引线框封装件的第二侧，以去除所述基底层的部分并且从所述第一突起限定用于引线框的引线，并且还从所述第二突起限定用于所述引线框的管芯支撑件。
2.根据权利要求1所述的方法，其中所述集成电路管芯包括环境传感器，其中所述第二突起具有围绕所述环境传感器的环形形状，并且其中环形的所述第二突起和所述基底层的一部分在所述包封期间密封位于所述环境传感器之上的开放区域。
3.根据权利要求2所述的方法，其中蚀刻所述第二侧包括去除所述基底层的所述部分来解封位于所述环境传感器之上的所述开放区域。
4.根据权利要求1所述的方法，还包括通过穿过所述包封材料切割来执行切单，以产生集成电路封装件。
5.根据权利要求4所述的方法，其中所述集成电路封装件是四方扁平无引线(QFN)集成电路封装件。
6.根据权利要求1所述的方法，其中将所述集成电路管芯的所述键合焊盘电气地和机械地附接到所述第一突起包括：
在所述第一突起与所述集成电路管芯的所述键合焊盘之间沉积可固化材料；以及
将所述可固化材料固化来形成键合柱。
7.根据权利要求1所述的方法，其中可固化材料是导电烧结材料。
8.根据权利要求1所述的方法，其中将所述集成电路管芯的所述前侧机械地附接到所述第二突起包括：
在所述第二突起与所述集成电路管芯的所述前侧之间沉积可固化材料；以及
将所述可固化材料固化来形成管芯安装附接件。
9.根据权利要求8所述的方法，其中所述可固化材料是导电烧结材料。
10.根据权利要求1所述的方法，其中包封所述集成电路管芯包括执行传递模制过程。
11.根据权利要求1所述的方法，其中所述集成电路管芯在所述集成电路管芯的所述前侧处包括保护层，其中所述保护层包括在所述键合焊盘处的开口，并且其中将所述键合焊盘电气地和机械地附接包括借助在所述键合焊盘处所述开口来安装。
12.根据权利要求1所述的方法，其中所述集成电路管芯在所述集成电路管芯的所述前侧处包括保护层，并且其中将所述集成电路管芯的所述前侧机械地附接到所述第二突起包括将所述保护层安装到所述第二突起。
13.根据权利要求1所述的方法，其中蚀刻所述第一侧包括：
在所述无带引线框封装件上，将第一镀层图案化；以及
使用经图案化的第一镀层作为用于蚀刻所述第一侧的掩膜，经图案化的第一镀层限定了所述第一突起的尺寸和形状以及所述第二突起的尺寸和形状。
14.根据权利要求13所述的方法，其中蚀刻所述第二侧包括：
在所述无带引线框封装件的所述第二侧上，将第二镀层图案化；以及
使用经图案化的第二镀层作为用于蚀刻所述第二侧的掩模，经图案化的第二镀层利用所述第一突起和所述第二突起限定了用于所述引线框的引线的尺寸和形状以及用于所述引线框的所述管芯支撑件的尺寸和形状。
15.根据权利要求14所述的方法，其中所述第一镀层的图案和所述第二镀层的图案相同并且彼此对准。
16.一种无带引线框封装件，包括：
基底层，具有第一侧和第二侧；
第一突起，在所述第一侧处从所述基底层延伸；
第二突起，在所述第一侧处从所述基底层延伸；
第一镀层，位于所述第一侧处，所述第一镀层具有第一图案，所述第一图案限定了所述第一突起的尺寸和形状以及所述第二突起的尺寸和形状；以及
第二镀层，位于所述第二侧处，所述第二层具有第二图案；
其中所述第一镀层的所述第一图案与所述第二镀层的所述第二图案相同并且彼此对准。
17.根据权利要求16所述的无带引线框封装件，其中所述第一镀层的所述第一图案形成蚀刻掩模。
18.根据权利要求16所述的无带引线框封装件，其中所述第二镀层的所述第二图案形成蚀刻掩模。
19.根据权利要求16所述的无带引线框封装件，还包括在所述第一突起的顶表面和所述第二突起的顶表面上的导电涂层材料。
20.根据权利要求16所述的无带引线框封装件，其中所述第二突起具有环形形状，并且其中所述第一突起被定位成偏离所述环形形状的外周边。
21.根据权利要求20所述的无带引线框封装件，还包括多个所述第二突起，其中所述多个第二突起以围绕所述第一突起的所述环形形状的规则图案而被布置。
22.一种集成电路封装件，包括：
无带引线框，包括环形管芯支撑件以及多个引线，所述多个引线以围绕所述环形管芯支撑件的规则图案而被布置；
其中所述环形管芯支撑件围绕由所述环形管芯支撑件的内周边界定的开放区域；
集成电路管芯，以倒装芯片定向而被安装到所述无带引线框，其中所述集成电路管芯的前侧面向所述无带引线框的第一侧；
电气附接件和机械附接件，位于所述集成电路管芯的键合焊盘与所述多个引线中的对应引线之间；
机械附接件，位于所述环形管芯支撑件与所述集成电路管芯的所述前侧之间，
其中所述集成电路管芯包括环境传感器，并且其中所述环形管芯支撑件的所述开放区域与所述环境传感器对准；以及
包封块，在不覆盖所述开放区域的情况下，将所述集成电路管芯、所述多个引线和所述环形管芯支撑件包封。
23.根据权利要求22所述的集成电路封装件，还包括：
位于所述环形管芯支撑件和所述多个引线的顶表面上的第一镀层；
其中所述机械附接件与所述环形管芯支撑件上的所述第一镀层接触；以及
其中所述电气附接件和所述机械附接件与所述多个引线上的所述第一镀层接触。
24.根据权利要求23所述的集成电路封装件，还包括在所述环形管芯支撑件和所述多个引线的底表面上的第二镀层。
25.根据权利要求22所述的集成电路封装件，其中所述电气附接件和所述机械附接件由固化的导电烧结材料提供。
26.根据权利要求22所述的集成电路封装件，其中所述机械附接件由固化的导电烧结材料提供。
27.根据权利要求22所述的集成电路封装件，其中所述集成电路管芯在集成电路管芯的所述前侧处包括保护层，其中所述保护层在集合焊盘处包括开口，并且其中所述机械附接件在所述保护层与所述环形管芯支撑件之间制成。
28.根据权利要求22所述的集成电路封装件，其中所述环境传感器是光学传感器。
CN202110735508.6A 2020-07-01 2021-06-30 具有暴露的集成电路管芯的无带引线框封装件 Pending CN113889419A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063046838P 2020-07-01 2020-07-01
US63/046,838 2020-07-01
US17/342,765 2021-06-09
US17/342,765 US11916090B2 (en) 2020-07-01 2021-06-09 Tapeless leadframe package with exposed integrated circuit die

Publications (1)

Publication Number Publication Date
CN113889419A true CN113889419A (zh) 2022-01-04

Family

ID=79010719

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202110735508.6A Pending CN113889419A (zh) 2020-07-01 2021-06-30 具有暴露的集成电路管芯的无带引线框封装件
CN202121468663.8U Active CN215731589U (zh) 2020-07-01 2021-06-30 无带引线框封装件和集成电路封装件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN202121468663.8U Active CN215731589U (zh) 2020-07-01 2021-06-30 无带引线框封装件和集成电路封装件

Country Status (2)

Country Link
US (1) US11916090B2 (zh)
CN (2) CN113889419A (zh)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG87769A1 (en) 1998-09-29 2002-04-16 Texas Instr Singapore Pte Ltd Direct attachment of semiconductor chip to organic substrate
US20020063314A1 (en) 2000-11-30 2002-05-30 Read Mathew S. Tapeless micro-leadframe
US7122884B2 (en) 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US6943434B2 (en) 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US8124447B2 (en) * 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8334584B2 (en) * 2009-09-18 2012-12-18 Stats Chippac Ltd. Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
US9196504B2 (en) * 2012-07-03 2015-11-24 Utac Dongguan Ltd. Thermal leadless array package with die attach pad locking feature
US9490146B2 (en) 2014-06-02 2016-11-08 Stmicroelectronics, Inc. Semiconductor device with encapsulated lead frame contact area and related methods
US9947636B2 (en) 2014-06-02 2018-04-17 Stmicroelectronics, Inc. Method for making semiconductor device with lead frame made from top and bottom components and related devices
US9754861B2 (en) * 2014-10-10 2017-09-05 Stmicroelectronics Pte Ltd Patterned lead frame
US10147673B2 (en) 2016-09-30 2018-12-04 Stmicroelectronics, Inc. Tapeless leadframe package with underside resin and solder contact

Also Published As

Publication number Publication date
CN215731589U (zh) 2022-02-01
US20220005857A1 (en) 2022-01-06
US11916090B2 (en) 2024-02-27

Similar Documents

Publication Publication Date Title
JP3398721B2 (ja) 半導体パッケージ及びその製造方法
US8659151B2 (en) Semiconductor device and manufacturing method thereof
US6387732B1 (en) Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby
US8487424B2 (en) Routable array metal integrated circuit package fabricated using partial etching process
US11682656B2 (en) Semiconductor device package and method for manufacturing the same
JP2009016839A (ja) 除去可能な保護膜を利用する画像センサパッケージ及び該画像センサパッケージの作製方法
EP3440697B1 (en) Flat no-leads package with improved contact leads
US8105881B2 (en) Method of fabricating chip package structure
KR20060042872A (ko) 반도체장치의 실장 방법
US20180122731A1 (en) Plated ditch pre-mold lead frame, semiconductor package, and method of making same
TWI414028B (zh) 注射封膠系統及其方法
KR200489288Y1 (ko) 리드 프레임 디바이스 및 이 리드 프레임 디바이스를 포함하는 리드 프레임 디바이스 조립체
KR20020025669A (ko) 반도체장치의 제조방법
US7208817B2 (en) Semiconductor device
US11721654B2 (en) Ultra-thin multichip power devices
JPH0837253A (ja) 半導体装置およびその製造方法並びに実装方法
US11348863B2 (en) Semiconductor package having a semiconductor die on a plated conductive layer
US20080006940A1 (en) Lead frames, microelectronic devices with lead frames, and methods for manufacturing lead frames and microelectronic devices with lead frames
CN215731589U (zh) 无带引线框封装件和集成电路封装件
KR20010001159A (ko) 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
US20150084171A1 (en) No-lead semiconductor package and method of manufacturing the same
CN111199924A (zh) 半导体封装结构及其制作方法
JP2023550701A (ja) マイクロ電子デバイスのパッケージ内の領域遮蔽
JP2002270627A (ja) 半導体装置の製造方法
US20220270960A1 (en) Open-Cavity Package for Chip Sensor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination