CN113875143A

CN113875143A - Power conversion device and control method for power conversion device

Info

Publication number: CN113875143A
Application number: CN202080037695.4A
Authority: CN
Inventors: 稻田辽一; 早坂圭介; 重田哲
Original assignee: Hitachi Astemo Ltd
Current assignee: Hitachi Astemo Ltd
Priority date: 2019-05-24
Filing date: 2020-05-19
Publication date: 2021-12-31
Also published as: DE112020002128T5; WO2020241366A1; JP7124218B2; JPWO2020241366A1

Abstract

Conventionally, it has not been possible to determine which part of the power semiconductor constituting the upper arm circuit and the lower arm circuit has failed. In the present invention, an analog DC current calculation unit (451) in a power semiconductor diagnosis unit (45) calculates a 1 st failure-time analog DC current value for each phase based on the duty ratio value (Du, Dv, Dw) and the AC current sensor value (iu, Ivs, Iws) for each phase, and outputs the value to a failure determination unit (452). A failure determination unit (452) determines which portion of the power semiconductor in the power conversion circuit (60) has failed using the 1 st failure-time analog DC current value for each phase, the DC current sensor value (Idcs), the duty ratio value (Du, Dv, Dw) for each phase, and the target torque, and outputs a failure notification signal corresponding to the failed portion to a failure notification device (30) and a PWM signal generation unit (44). A failure determination unit (452) determines the target torque and identifies whether the engine is in power operation or in regeneration operation.

Description

Power conversion device and control method for power conversion device

Technical Field

The present invention relates to a power conversion apparatus and a control method of the power conversion apparatus.

Background

Hybrid vehicles and electric vehicles are equipped with a power conversion device to drive an electric motor. In the power conversion device, power semiconductors constituting an upper arm circuit and a lower arm circuit are switched in correspondence with each phase of the motor, so that a direct current supplied from a battery is converted into an alternating current, and the motor is driven.

In recent years, the necessity of detecting an abnormality or a failure in a power conversion device has been increasing based on a functional safety standard for automobiles. Therefore, it is also necessary to perform diagnosis of the power semiconductor to detect an abnormality or a failure.

Patent document 1 discloses the following apparatus: the power conversion device includes a drive circuit for switching on/off of the power semiconductors for each power semiconductor, and outputs an abnormality notification signal to an external abnormality notification device when it is determined that a fault has occurred inside the power conversion device.

Documents of the prior art

Patent document

Patent document 1: japanese patent laid-open publication No. 2017-208893

Disclosure of Invention

Technical problem to be solved by the invention

In the device described in patent document 1, it is not possible to determine which part of the power semiconductor constituting the upper arm circuit and the lower arm circuit has failed.

Technical scheme for solving technical problem

The power conversion device according to the present invention includes: a power conversion circuit which is configured by an upper arm circuit and a lower arm circuit for each phase of a multi-phase motor and converts a direct current into a multi-phase alternating current; a control circuit that outputs a PWM signal to the upper arm circuit and the lower arm circuit; an analog direct current calculation unit that calculates a 1 st fault-time analog direct current based on an alternating current value of a remaining phase at the time of a 1-phase fault in the plurality of phases, based on the alternating current output by the power conversion circuit and a duty ratio of the PWM signal; and a failure determination unit that detects a failure of the upper arm circuit or the lower arm circuit of an arbitrary phase based on a direct current input to the power conversion circuit or a direct current based on an alternating current value output from the power conversion circuit, a duty ratio of the PWM signal, and the 1 st failure time analog direct current.

In a control method of a power conversion device according to the present invention, a power conversion circuit is configured by an upper arm circuit and a lower arm circuit for each phase of a multi-phase motor, a dc current is converted into a multi-phase ac current, a PWM signal is output to the upper arm circuit and the lower arm circuit, a 1 st fault-time analog dc current based on an ac current value of a remaining phase in a case of a 1-phase fault among a plurality of phases is calculated based on the ac current output by the power conversion circuit and a duty ratio of the PWM signal, and a fault of the upper arm circuit or the lower arm circuit of an arbitrary phase is detected based on the dc current input to the power conversion circuit or the dc current based on the ac current value output from the power conversion circuit, the duty ratio of the PWM signal, and the 1 st fault-time analog dc current.

Effects of the invention

According to the present invention, it is possible to determine which part of the power semiconductors constituting the upper arm circuit and the lower arm circuit has failed.

Drawings

Fig. 1 is a circuit configuration diagram of a power conversion device according to embodiment 1.

Fig. 2 is a circuit configuration diagram of the power conversion circuit.

Fig. 3 is a flowchart showing a failure determination process according to embodiment 1.

Fig. 4 is a flowchart showing the failure handling process.

Fig. 5(a), (B), and (C) are graphs of ac current, duty ratio, and dc current when a fault that the U-phase upper arm circuit is turned off and fixed occurs during power running.

Fig. 6 is a circuit configuration diagram of the power conversion device according to embodiment 2.

Fig. 7 is a flowchart showing a failure determination process according to embodiment 2.

Fig. 8 is a circuit configuration diagram of the power conversion device according to embodiment 3.

Fig. 9 is a flowchart showing a failure determination process according to embodiment 3.

Fig. 10 is a flowchart showing a failure determination process according to embodiment 4.

Fig. 11 is a flowchart showing a failure determination process according to embodiment 5.

Detailed Description

[ embodiment 1]

Fig. 1 is a circuit configuration diagram of a power conversion device 100 according to embodiment 1.

The power conversion apparatus 100 converts dc power obtained from the dc power supply 10 into ac power and drives the motor 20 during power running. The dc power supply 10 is a power supply for driving the motor 20. Further, at the time of regeneration, power conversion device 100 converts the power of motor 20 into dc power and charges dc power supply 10.

The motor 20 is a three-phase motor having three windings inside. The motor 20 is also mounted with an angle sensor (not shown) for measuring a rotation angle of the motor 20, and the angle sensor outputs the measured rotation angle to the power conversion device 100 as an angle sensor value. Power conversion device 100 detects a failure described later and notifies failure notification device 30 of the failure.

The power conversion apparatus 100 includes a control circuit 40, a drive circuit 50, and a power conversion circuit 60. The control circuit 40 includes a motor speed calculation unit 41, a target current calculation unit 42, a duty calculation unit 43, a PWM signal generation unit 44, and a power semiconductor diagnosis unit 45. The power semiconductor diagnosis unit 45 includes an analog dc current calculation unit 451 and a failure determination unit 452.

The voltage sensor 70 is a sensor for measuring the output voltage of the dc power supply 10, and outputs the measured voltage value as a voltage sensor value to the target current calculation section 42 in the control circuit 40.

Dc current sensor 80 measures a dc current flowing between dc power supply 10 and power conversion circuit (inverter circuit) 60, and outputs the measured current value to failure determination unit 452 as dc current sensor value Idcs. In the present embodiment, the dc current sensor 80 is provided so that the current flowing from the dc power supply 10 to the power conversion circuit 60 is measured as a positive current value, but the dc current sensor 80 may be provided so that a reverse current value is measured as a positive current value.

The ac current sensor 90 is a sensor for measuring an ac current flowing through each phase (U-phase, V-phase, W-phase) of the motor 20. Specifically, an ac current Iu flowing through the U phase is measured, and an ac current sensor value Ius is output to the duty ratio calculation unit 43 and the analog dc current calculation unit 451. Similarly, an ac current Iv flowing in the V phase is measured, and an ac current sensor value Ivs is output to the duty ratio calculation unit 43 and the analog dc current calculation unit 451. Similarly, an ac current Iw flowing through the W phase is measured, and an ac current sensor value Iws is output to the duty ratio calculation unit 43 and the analog dc current calculation unit 451.

The motor speed calculation portion 41 calculates a motor speed value from a change in the angle sensor value in the motor 20, and outputs the calculated motor speed value to the target current calculation portion 42.

The control circuit 40 communicates with an electronic control device (not shown) provided outside the power converter 100, receives the target torque of the motor 20 from the external electronic control device, and inputs the target torque to the target current calculation unit 42.

The target current calculation portion 42 calculates a current value to be flowed to the motor 20 using the target torque, the voltage sensor value, and the motor speed value output by the motor speed calculation portion 41, and outputs the current value as a target current value to the duty ratio calculation portion 43. The target current value is expressed in the form of a d-axis target current value and a q-axis target current value, for example.

The duty ratio calculation section 43 calculates the U-phase duty ratio value Du, the V-phase duty ratio value Dv, and the W-phase duty ratio value Dw based on the target current value and the alternating current sensor values iu, Ivs, Iws output by the target current calculation section 42, and outputs to the PWM signal generation section 44 and the analog direct current calculation section 451.

In the present embodiment, the U-phase duty ratio value Du represents the on-time ratio of the U-phase upper arm circuit power semiconductor, and the on-time ratio of the U-phase lower arm circuit power semiconductor is represented by 1 to Du. Similarly, the V-phase duty value Dv represents the on-time ratio of the V-phase upper arm circuit power semiconductor, and the on-time ratio of the V-phase lower arm circuit power semiconductor is represented by 1-Dv. The W-phase duty ratio value Dw represents the on-time ratio of the W-phase upper arm circuit power semiconductor, and the on-time ratio of the W-phase lower arm circuit power semiconductor is represented by 1-Dw.

The PWM signal generation unit 44 includes a timer (not shown) therein, generates a PWM (Pulse width Modulation) signal based on the timer value and the U-phase duty value Du, the V-phase duty value Dv, and the W-phase duty value Dw, and outputs the PWM signal to the drive circuit 50.

PWM signal generation unit 44 controls the PWM signal so that motor 20 is not driven when the abnormality notification signal is output from power semiconductor diagnosis unit 45. The state in which the motor 20 is not driven includes, for example, a state in which all of the 6 power semiconductors in the power conversion circuit 60 are turned off (referred to as a free wheel state in the present embodiment). As another example, among the 6 power semiconductors, a state in which 3 power semiconductors of the upper arm circuit are on and 3 power semiconductors of the lower arm circuit are off (referred to as an upper arm active short-circuit state in the present embodiment), or a state in which 3 power semiconductors of the upper arm circuit are off and 3 power semiconductors of the lower arm circuit are on (referred to as a lower arm active short-circuit state in the present embodiment) may be given.

The drive circuit 50 receives the PWM signal output from the PWM signal generation unit 44, and outputs a drive signal for switching on/off of the power semiconductor to the power conversion circuit 60.

The power conversion circuit 60 includes a smoothing capacitor and 6 power semiconductors therein, and converts dc power obtained from the dc power supply 10 into ac power to drive the motor 20 during power running. At the time of regeneration, the power of the motor 20 is converted into dc power to charge the dc power supply 10.

The power semiconductor diagnosis unit 45 diagnoses a failure of the power semiconductor in the power conversion circuit 60. The analog dc current calculation unit 451 in the power semiconductor diagnosis unit 45 calculates the 1 st failure-time analog dc current value of each phase based on the duty values Du, Dv, Dw of each phase and the ac current sensor values iu, Ivs, Iws, and outputs the value to the failure determination unit 452.

The failure determination unit 452 determines which portion of the power semiconductor in the power conversion circuit 60 has failed using the 1 st failure-time analog dc current value of each phase, the dc current sensor value Idcs, the duty ratio values Du, Dv, Dw of each phase, and the target torque, and outputs a failure notification signal corresponding to the failed portion to the failure notification device 30 and the PWM signal generation unit 44. The failure determination unit 452 determines the target torque and identifies whether the engine is in the power running mode or the regeneration mode. Specifically, the case where the target torque is positive means the power running, and the case where the target torque is negative means the regeneration. As another identification method, it is possible to identify as being the powering operation in the case where the dc current sensor value Idcs is positive, and as being the regeneration operation in the case where the dc current sensor value Idcs is negative.

Fig. 2 is a circuit configuration diagram of the power conversion circuit 60.

The power conversion circuit 60 has an upper and lower arm series circuit of UVW phase. U-phase upper and lower arm series circuit 61 is composed of U-phase upper arm power semiconductor Tuu and U-phase upper arm diode Duu, U-phase lower arm power semiconductor Tul and U-phase lower arm diode Dul. The V-phase upper and lower arm series circuit 62 is composed of a V-phase upper arm power semiconductor Tvu and a V-phase upper arm diode Dvu, a V-phase lower arm power semiconductor Tvl and a V-phase lower arm diode Dvl. The W-phase upper and lower arm series circuit 63 is composed of a W-phase upper arm power semiconductor Twu and a W-phase upper arm diode Dwu, a W-phase lower arm power semiconductor Twl, and a W-phase lower arm diode Dwl.

Upper arm circuit 64 has U-phase upper arm power semiconductor Tuu and U-phase upper arm diode Duu, V-phase upper arm power semiconductor Tvu and V-phase upper arm diode Dvu, W-phase upper arm power semiconductor Twu, and W-phase upper arm diode Dwu. Lower arm circuit 65 has U-phase lower arm power semiconductor Tul and U-phase lower arm diode Dul, V-phase lower arm power semiconductor Tvl and V-phase lower arm diode Dvl, W-phase lower arm power semiconductor Twl, and W-phase lower arm diode Dwl. Examples of the power Semiconductor include a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and the like.

The smoothing capacitor 66 filters the current generated by turning on/off the power semiconductor, and suppresses the ripple of the dc current supplied from the dc power supply 10 to the power conversion circuit 60. The filter capacitor 66 is, for example, an electrolytic capacitor or a film capacitor.

Fig. 3 is a flowchart showing a failure determination process of the power semiconductor in the power semiconductor diagnosis section 45.

As shown in step S10 of fig. 3, the power semiconductor diagnostic portion 45 acquires the alternating current sensor values iu, Ivs, Iws and the direct current sensor value Idcs.

In step S11, the analog dc current calculation unit 451 calculates the U-phase 1-fault-time analog dc current value Idcu, the V-phase 1-fault-time analog dc current value Idcv, and the W-phase 1-fault-time analog dc current value Idcw from the duty ratio values Du, Dv, and Dw of the respective phases and the ac current sensor values iu, Ivs, Iws based on the following expressions (1) to (3), and outputs the values to the fault determination unit 452.

Analog direct current Idcu ═ Dv × Ivs + Dw × Iws (1) at the 1 st fault of U phase

Simulated direct current Idcv at 1 st fault of V-phase dux Ius + Dw x Iws (2)

W-phase 1 st fault time analog dc current Idcw ═ Du × Ius + Dv × Ivs (3)

In step S12, the failure determination unit 452 determines that the power semiconductor of the U-phase has failed when the difference between the dc current sensor value Idcs and the U-phase 1 st failure time simulation dc current value Idcu is smaller than the threshold value 1. When the power semiconductor is in the off-set fault, the 1 st fault-time simulated direct current of the phase is substantially equal to the actual direct current value in the time period for which the current is caused to flow through the faulty power semiconductor. The threshold value 1 is set to a value at which this relationship is established. This makes it possible to determine which phase has failed.

In step S13, the failure determination unit 452 determines whether the motor 20 is in the power running state or the regenerative state based on the input target torque or the like.

If it is determined that the vehicle is in the powering state, the process proceeds to step S14, and in step S14, the failure determination unit 452 determines whether the U-phase duty value Du is larger than the threshold value 2. When the U-phase duty value Du is larger than the threshold value 2, it is determined in step S16 that the U-phase upper arm circuit power semiconductor has a shutdown fixing failure. When the U-phase duty value Du is not larger than the threshold value 2, it is determined in step S17 that the power semiconductor of the U-phase lower arm circuit has a failure in turn-off fixation. The threshold value 2 is set to, for example, 0.5 if the U-phase duty ratio value Du is in the range of 0 to 1. This determines which of the upper arm circuit and the lower arm circuit the current is to be caused to flow.

If it is determined in step S13 that the state is the regenerative state, the process proceeds to step S15, and in step S15, the failure determination unit 452 determines whether the U-phase duty value Du is equal to or less than the threshold value 2. If the U-phase duty ratio value Du is below the threshold value 2, it is determined in step S16 that the U-phase upper arm circuit power semiconductor has a turn-off fixation failure. If the U-phase duty ratio value Du is not below the threshold value 2, it is determined in step S17 that the turn-off fixation of the U-phase lower arm circuit power semiconductor is failed.

In step S18, failure determination unit 452 outputs a failure notification signal corresponding to the failure location to PWM signal generation unit 44 and failure notification device 30.

Thus, since the current does not flow through the failed power semiconductor, when the current is caused to flow through the failure site, the direct current becomes almost equal to the simulated direct current at the 1 st failure of the failed phase. At this time, since it is known which main body of the upper and lower arms is on from the duty value of the failure phase, the failure location of the upper and lower arms can be determined from the duty value. In addition, the phase of the voltage (i.e., duty ratio) and the current at the time of power running is the same, and therefore, the period in which the duty ratio is larger than the threshold value 0.5 coincides with the period in which the current is caused to flow through the upper arm. On the other hand, the phase of the voltage (i.e., duty ratio) and the current at the time of regeneration is shifted by 180 °, and therefore, the period in which the duty ratio is smaller than the threshold value 0.5 coincides with the period in which the current is caused to flow through the upper arm.

Steps S22 to S27 show the V-phase failure determination process, and steps S32 to S37 show the W-phase failure determination process.

In step S12, if the difference between the dc current sensor value Idcs and the U-phase 1 st-fault-time simulation dc current value Idcu is smaller than the threshold value 1, the process proceeds to step S22. In step S22, the failure determination unit 452 determines that the power semiconductor of the V-phase has failed when the difference between the dc current sensor value Idcs and the V-phase 1 st failure-time analog dc current value Idcv is smaller than the threshold value 1. Hereinafter, steps S22 to S27 are the same as steps S12 to S17, which are failure determination processing of the U-phase, and therefore, description thereof is omitted.

In step S22, if the difference between the dc current sensor value Idcs and the V-phase 1 st-failure-time analog dc current value Idcv is smaller than the threshold value 1, the process proceeds to step S32. In step S32, when the difference between the dc current sensor value Idcs and the W-phase 1 st failure-time analog dc current value Idcw is smaller than the threshold value 1, the failure determination unit 452 determines that the power semiconductor of the W phase has failed. Hereinafter, steps S32 to S37 are the same as steps S12 to S17, which are failure determination processing of the U-phase, and therefore, description thereof is omitted.

In step S32, if the difference between the dc current sensor value Idcs and the W-phase 1-th failure-time analog dc current value Idcw is smaller than the threshold value 1, the failure determination unit 452 proceeds to step S39. In step S39, it is determined that the power semiconductor has not failed in the off-fixation.

Fig. 4 is a flowchart showing the failure handling process of the PWM signal generation unit 44.

The PWM signal generation unit 44 receives the failure notification signal from the failure determination unit 452, and starts the failure handling process. When the failure notification signal is received in step S18 of fig. 3, if it is determined in step S40 of fig. 4 that the upper arm off fixed fault has occurred in any of the U-phase, V-phase, and W-phase, the process proceeds to step S41.

In step S41, a PWM signal is generated in the free wheel state or the lower arm active short-circuit state. The power semiconductor of the upper arm circuit cannot be turned on due to a failure, and therefore, the upper arm circuit cannot be brought into an active short-circuit state.

When it is determined in step S42 that the lower arm off fixing fault has occurred in any of the U-phase, V-phase, and W-phase, the process proceeds to step S43.

In step S43, a PWM signal is generated which is in a free wheel state or an upper arm active short circuit state. The power semiconductor of the lower arm circuit cannot be turned on due to a failure, and therefore, the lower arm circuit cannot be brought into an active short-circuit state.

If there is no failure in step S40 or step S42, the process proceeds to step S44. In step S44, since no failure has occurred, the PWM signal generation unit 44 continues the PWM operation, generates PWM signals corresponding to the duty values Du, Dv, and Dw of the respective phases, and outputs the PWM signals to the drive circuit 50.

Fig. 5(a), 5(B), and 5(C) are graphs of an ac current, a duty ratio, and a dc current when a fault that the U-phase upper arm circuit is turned off and fixed occurs during the powering operation.

Fig. 5(a) shows an alternating current, fig. 5(B) shows a duty ratio, fig. 5(C) shows a direct current, and the horizontal axis of each graph is time. At time t, the U-phase upper arm circuit is in the power running state, and a failure of the shutdown fixation occurs.

As shown in fig. 5(a), the U-phase upper arm circuit has a failure of off-fixation at time t, and therefore, the ac current sensor value Ius flowing in the U-phase becomes zero. As shown in fig. 5(C), a period during which the U-phase 1 st fault-time analog direct current value Idcu approaches the direct current sensor value Idcs is generated, and in this period, as shown in step S13 of fig. 3, it is determined that the difference between the direct current sensor value Idcs and the U-phase 1 st fault-time analog direct current value Idcu is smaller than the threshold value 1. Then, in this period, as shown in fig. 5(B), the duty value Du of the U-phase exceeds 0.5. Therefore, as shown in step S14 of fig. 3, it is determined that the U-phase duty value Du is greater than the threshold value 2. As a result, in step S16 of fig. 3, the turn-off fixation failure of the U-phase upper arm circuit power semiconductor is determined.

[ embodiment 2]

Fig. 6 is a circuit configuration diagram of the power converter 200 according to embodiment 2.

The power converter 200 according to embodiment 2 is different from the power converter 100 according to embodiment 1 shown in fig. 1 in that it does not include the dc current sensor 80 and the power semiconductor diagnostic unit 46 does not. The same parts as those of the power conversion device 100 according to embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted, and different parts will be described below.

The analog dc current calculation unit 461 of the power semiconductor diagnosis unit 46 calculates the 1 st failure-time analog dc current of each phase based on the expressions (1) to (3) shown in embodiment 1. Further, the normal-time analog dc current value is calculated using the duty ratios Du, Dv, and Dw of the respective phases and the ac current sensor values iu, Ivs, Iws of the respective phases. That is, since the direct current in the normal state can be calculated by the following expression (4), a value calculated by the expression (4) can be used instead of the direct current sensor.

Dc current (Du × Ius) + (Dv × Ivs) + (Dv × Iws) (4)

Here, Du: u-phase duty ratio, Dv: v-phase duty ratio, Dw: w-phase duty ratio, Ius: u-phase alternating current sensor value, Ivs: v-phase alternating current sensor value, Iws: w alternating current sensor value.

The analog dc current calculator 461 outputs the calculated dc current to the failure determination unit 462. The failure determination unit 462 determines which portion of the power semiconductor in the power conversion circuit 60 has failed using the 1 st failure-time analog dc current value, the normal-time analog dc current value, the duty values Du, Dv, Dw of each phase, and the target torque, and outputs a failure notification signal corresponding to the failed portion to the failure notification device 30 and the PWM signal generation unit 44. The failure determination unit 462 determines the target torque and identifies whether the engine is in the power running mode or in the regeneration mode. Specifically, the case where the target torque is positive means the power running, and the case where the target torque is negative means the regeneration. As another identification method, it is possible to identify the power running mode when the normal-time analog dc calculated by the analog dc calculation unit 461 is positive, and identify the regeneration mode when the normal-time analog dc calculated by the analog dc calculation unit 461 is negative.

Fig. 7 is a flowchart showing a failure determination process of the power semiconductor in the power semiconductor diagnosis section 46.

In the failure determination process in the power semiconductor diagnostic unit 46 according to embodiment 2, the same components as those in the flowchart illustrating the failure determination process according to embodiment 1 shown in fig. 3 are denoted by the same reference numerals, and the description thereof is omitted, and different portions are described below.

As shown in step S10' of fig. 7, the power semiconductor diagnostic unit 46 acquires the ac current sensor values iu, Ivs, Iws.

In step S11', the analog dc current calculation unit 461 calculates the U-phase 1-fault-time analog dc current value Idcu, the V-phase 1-fault-time analog dc current value Idcv, and the W-phase 1-fault-time analog dc current value Idcw based on the duty ratio values Du, Dv, and Dw of the respective phases and the ac current sensor values iu, Ivs, and Iws based on expressions (1) to (3), and outputs the values to the fault determination unit 462. Further, a normal-time analog dc current Idce, which is a normal-time dc current, is calculated based on equation (4) and output to the failure determination unit 462.

In step S12', when the difference between the normal-time analog dc current Idec and the U-phase 1 st-fault analog dc current value Idcu is smaller than the threshold value 1, the fault determination unit 462 determines that the power semiconductor of the U-phase has a fault. When the power semiconductor is in the off-set fault, the 1 st fault-time simulated direct current of the phase is substantially equal to the actual direct current value in the time period for which the current is caused to flow through the faulty power semiconductor. The threshold value 1 is set to a value at which this relationship is established. This makes it possible to determine which phase has failed.

In step S13, the failure determination unit 462 determines whether the motor 20 is in the power running state or the regenerative state based on the input target torque and the like. The following is the same as the flowchart showing the failure determination process according to embodiment 1 shown in fig. 3.

In step S12 ', if the difference between the normal-time analog direct current Idce and the U-phase 1 st-fault analog direct current value Idcu is smaller than the threshold 1, the process proceeds to step S22'. In step S22', when the difference between the normal-time pseudo dc current Idce and the V-phase 1 st failure-time pseudo dc current value Idcv is smaller than the threshold value 1, the failure determination unit 462 determines that the power semiconductor of the V-phase has failed. Hereinafter, steps S23 to S27 are the same as steps S13 to S17 of the U-phase failure determination processing, and therefore, the description thereof is omitted.

In step S22 ', if the difference between the normal-time analog direct current Idce and the V-phase 1 st-fault-time analog direct current value Idcv is smaller than the threshold 1, the process proceeds to step S32'. In step S32', when the difference between the normal-time pseudo dc current Idce and the W-phase 1 st fault-time pseudo dc current value Idcw is smaller than the threshold value 1, the fault determination unit 462 determines that the power semiconductor of the W phase has a fault. Hereinafter, steps S33 to S37 are the same as steps S13 to S17 of the U-phase failure determination processing, and therefore, the description thereof is omitted.

In step S32', if the difference between the normal-time analog dc current Idce and the W-phase 1 st-fault-time analog dc current value Idcw is smaller than the threshold value 1, the fault determination unit 462 proceeds to step S39. In step S39, it is determined that the power semiconductor has not failed in the off-fixation.

[ embodiment 3]

Fig. 8 is a circuit configuration diagram of a power conversion device 300 according to embodiment 3.

The power conversion device 300 according to embodiment 3 is different from the power semiconductor diagnostic unit 47 in the power conversion device 100 according to embodiment 1 shown in fig. 1. The same parts as those of the power conversion device 100 according to embodiment 1 are denoted by the same reference numerals, and the description thereof is omitted, and different parts will be described below.

The analog dc current calculation unit 471 of the power semiconductor diagnostic unit 47 calculates the 1 st failure-time analog dc current of each phase based on the expressions (1) to (3) shown in embodiment 1. Further, the 2 nd fault-time simulation direct current of each phase is calculated based on the following expressions (5) to (7).

Analog direct current Idcu2 ═ K × Ius + Dv × Ivs + Dw × Iws (5) at the 2 nd fault of U phase

Analog direct current Idcv2 at 2 nd fault of V-phase (Du × Ius + K × Ivs + Dw × Iws (6)

W-phase 2 nd fault time analog dc current Idcw2 (Du × Ius + Dv × Ivs + K × Iws (7)

Here, Du: u-phase duty ratio, Dv: v-phase duty ratio, Dw: w-phase duty ratio, Ius: u-phase alternating current sensor value, Ivs: v-phase alternating current sensor value, Iws: the W AC current sensor value, K is the coefficient. The coefficient K is set in the range of 0 < K < 1. The 1 st failure time simulation dc current of the expressions (1) to (3) shown in embodiment 1 corresponds to the case where the expressions (5) to (7) are calculated with K being 0. To avoid false detection in the normal state, it is preferable to set K to a value greatly different from 0 (for example, K is 1).

The 1 st fault-time simulated dc current and the 2 nd fault-time simulated dc current of each phase calculated by the simulated dc current calculation unit 471 are output to the fault determination unit 472.

The failure determination unit 472 determines which portion of the power semiconductor in the power conversion circuit 60 has failed using the 1 st failure-time analog dc current value of each phase, the 2 nd failure-time analog dc current value of each phase, the dc current sensor value Idcs, the duty ratio values Du, Dv, Dw of each phase, and the target torque, and outputs a failure notification signal corresponding to the failed portion to the failure notification device 30 and the PWM signal generation unit 44.

In the present embodiment, the failure determination unit 472 determines whether or not the difference between the dc current sensor value Idcs and the 1 st failure time simulated dc current value is smaller than the threshold 1, and whether or not the difference between the dc current sensor value Idcs and the 2 nd failure time simulated dc current value is smaller than the threshold 1.

Since the current does not flow through the failed power semiconductor, the analog dc current and the dc current are also equal at the time of the 2 nd fault using the ac currents of all three phases. Therefore, even if the 2 nd fault time simulation direct current is additionally used, the fault position can be determined. When only the difference between the dc current sensor value Idcs and the 1 st failure-time analog dc current value is determined, the analog dc current value is approximated to the dc current at the 1 st failure time other than the timing failure phase with a small duty ratio (duty ratio ≈ 0), and therefore, erroneous detection of a failure may be induced. In contrast, in the present embodiment, it is possible to eliminate erroneous detection of a fault by determining whether the difference between the dc current sensor value Idcs and the 1 st-fault-time analog dc current value is smaller than the threshold 1 and whether the difference between the dc current sensor value Idcs and the 2 nd-fault-time analog dc current value is smaller than the threshold 1.

Fig. 9 is a flowchart showing a failure determination process of the power semiconductor in the power semiconductor diagnosis section 47.

In the failure determination process in the power semiconductor diagnostic unit 47 according to embodiment 3, the same components as those in the flowchart illustrating the failure determination process according to embodiment 1 shown in fig. 3 are denoted by the same reference numerals, and the description thereof is omitted, and different portions are described below.

In step S10 of fig. 9, the power semiconductor diagnostic unit 45 acquires the ac current sensor values iu, Ivs, Iws and the dc current sensor value Idcs, and in step S11 ″, the analog dc current calculation unit 471 calculates the U-phase 1-fault analog dc current value Idcu, the V-phase 1-fault analog dc current value Idcv and the W-phase 1-fault analog dc current value Idcw based on the duty ratio values Du, Dv, Dw and the ac current sensor values iu, Ivs, Iws based on the expressions (1) to (3) described in embodiment 1, and outputs the values to the fault determination unit 472. The analog dc current calculation unit 471 calculates the U-phase 2-fault analog dc current value Idcu2, the V-phase 2-fault analog dc current value Idcv2, and the W-phase 2-fault analog dc current value Idcw2 based on equations (5) to (7), and outputs the values to the fault determination unit 472.

In step S12 ″, when the difference between the dc current sensor value Idcs and the U-phase 1 st-fault-time analog dc current value Idcu is smaller than the threshold 1 and the difference between the dc current sensor value Idcs and the U-phase 2 nd-fault-time analog dc current value Idcu2 is smaller than the threshold 1, the fault determination unit 472 determines that the U-phase power semiconductor has a fault.

In step S13, the failure determination unit 462 determines whether the motor 20 is in the power running state or the regenerative state based on the input target torque and the like. Hereinafter, steps S13 to S18 are the same as the flowchart shown in fig. 3 showing the failure determination process according to embodiment 1.

In step S12 ″, when the conditions that the difference between the dc current sensor value Idcs and the U-phase 1-th failure-time simulated dc current value Idcu is smaller than the threshold 1 and the difference between the dc current sensor value Idcs and the U-phase 2-th failure-time simulated dc current value Idcu2 is smaller than the threshold 1 are not satisfied, the failure determination unit 472 proceeds to the process of step S22 ″. In step S22 ″, when the difference between the dc current sensor value Idcs and the V-phase 1 st-failure-time analog dc current value Idcv is smaller than the threshold 1 and the difference between the dc current sensor value Idcs and the V-phase 2 nd-failure-time analog dc current value Idcv2 is smaller than the threshold 1, the failure determination unit 472 determines that the power semiconductor of the V-phase has failed. Hereinafter, steps S23 to S27 are the same as steps S13 to S17 of the U-phase failure determination processing, and therefore, the description thereof is omitted.

In step S22 ″, when the conditions that the difference between the dc current sensor value Idcs and the V-phase 1-st failure-time analog dc current value Idcv is smaller than the threshold 1, and the difference between the dc current sensor value Idcs and the V-phase 2-nd failure-time analog dc current value Idcv2 is smaller than the threshold 1 are not satisfied, the process proceeds to step S32 ″. In step S32 ″, when the difference between the dc current sensor value Idcs and the W-phase 1-th failure-time analog dc current value Idcw is smaller than the threshold 1 and the difference between the dc current sensor value Idcs and the W-phase 2-th failure-time analog dc current value Idcw2 is smaller than the threshold 1, the failure determination unit 472 determines that the power semiconductor of the W-phase has failed. Hereinafter, steps S33 to S37 are the same as steps S13 to S17 of the U-phase failure determination processing, and therefore, the description thereof is omitted.

In step S32 ″, when the condition that the difference between the dc current sensor value Idcs and the W-phase 1-st failure-time analog dc current value Idcw is smaller than the threshold 1 and the difference between the dc current sensor value Idcs and the W-phase 2-th failure-time analog dc current value Idcw2 is smaller than the threshold 1 is not satisfied, the failure determination section 462 proceeds to step S39. In step S39, it is determined that the power semiconductor has not failed in the off-fixation.

[ embodiment 4]

The power conversion device 100 according to embodiment 4 is the same as the power conversion device 100 according to embodiment 1 shown in fig. 1, and therefore the same parts are denoted by the same reference numerals and the description thereof is omitted.

Fig. 10 is a flowchart showing a failure determination process of the power semiconductor in the present embodiment. In the present embodiment, the failure determination process has a portion different from the flowchart shown in fig. 3 showing the failure determination process according to embodiment 1. The same portions in the flowchart showing the failure determination process according to embodiment 1 shown in fig. 3 are denoted by the same reference numerals, and the description thereof is omitted, and different portions will be described below.

In embodiment 1, in step S12 in fig. 3, it is determined whether or not the difference between the dc current sensor value Idcs and the U-phase 1 st-fault-time simulated dc current value Idcu is smaller than the threshold value 1. In the present embodiment, in step S12' ″ of fig. 10, it is determined whether or not a state in which the difference between the dc current sensor value Idcs and the U-phase 1 st-failure-time simulated dc current value Idcu is smaller than the threshold value 1 continues for a predetermined time or longer. Even if the power semiconductor is not faulty, if the ac current of a certain phase is 0, the dc current sensor value matches the 1 st fault-time analog dc current value of that phase, and therefore, there is a possibility that false detection of a fault occurs. Therefore, in the present embodiment, when the state in which the difference between the dc current sensor value Idcs and the U-phase 1 st failure is smaller than the analog dc current value Idcu continues for a predetermined time or longer, the failure is detected, thereby avoiding erroneous detection of the failure.

In step S22' ″ of fig. 10, it is determined whether or not a state in which the difference between the dc current sensor value Idcs and the V-phase 1 st-failure-time simulated dc current value Idcv is smaller than the threshold value 1 continues for a predetermined time or longer.

In step S32' ″ of fig. 10, it is determined whether or not the state where the difference between the dc current sensor value Idcs and the W-phase 1 st-failure-time simulated dc current value Idcw is smaller than the threshold value 1 continues for a predetermined time or longer.

[ embodiment 5]

The power conversion device 300 according to embodiment 5 is the same as the power conversion device 300 according to embodiment 3 shown in fig. 8, and therefore the same parts are denoted by the same reference numerals and the description thereof is omitted.

Fig. 11 is a flowchart showing a failure determination process of the power semiconductor in the present embodiment. In the present embodiment, the failure determination process has a portion different from the flowchart shown in fig. 9 and showing the failure determination process according to embodiment 3. The same portions in the flowchart showing the failure determination process according to embodiment 3 shown in fig. 9 are denoted by the same reference numerals, and the description thereof is omitted, and different portions will be described below.

In embodiment 3, in step S12 ″ of fig. 9, it is determined whether the difference between the dc current sensor value Idcs and the U-phase 1-st failure-time simulated dc current value Idcu is smaller than the threshold 1, and whether the difference between the dc current sensor value Idcs and the U-phase 2-nd failure-time simulated dc current value Idcu2 is smaller than the threshold 1. In the present embodiment, in step S12 ″' of fig. 11, it is determined whether or not the difference between the U-phase 1 st fault-time simulated dc current value Idcu and the U-phase 2 nd fault-time simulated dc current value Idcu2 is smaller than the threshold value 1. In embodiment 3, when the conditions that the difference between the dc current sensor value Idcs and the U-phase 1 st-failure-time simulated dc current value Idcu is smaller than the threshold value 1 and the difference between the dc current sensor value Idcs and the U-phase 2 nd-failure-time simulated dc current value Idcu2 is smaller than the threshold value 1 are satisfied, the difference between the U-phase 1 st-failure-time simulated dc current value Idcu and the U-phase 2 nd-failure-time simulated dc current value Idcu2 is also within the predetermined range. Therefore, by setting the determination conditions of the present embodiment, the determination conditions can be simplified as compared with embodiment 3, and determination equivalent to the determination conditions of embodiment 3 can be performed.

In step S22 ″' of fig. 11, it is determined whether or not the difference between the V-phase 1-fault-time analog direct current value Idcv and the V-phase 2-fault-time analog direct current value Idcv2 is smaller than the threshold value 1.

In step S32 ″' of fig. 11, it is determined whether or not the difference between the W-phase 1-fault-time analog direct current value Idcw and the W-phase 2-fault-time analog direct current value Idcw2 is smaller than the threshold value 1.

According to the above-described embodiments, the following operational effects can be obtained.

(1) The power conversion apparatus 100 includes: a power conversion circuit 60, which is configured by an upper arm circuit and a lower arm circuit corresponding to each phase of the multi-phase motor 20, and which converts a direct current into a multi-phase alternating current; a control circuit 40, the control circuit 40 outputting a PWM signal to the upper arm circuit and the lower arm circuit; an analog dc current calculation unit 451 that calculates a 1 st fault-time analog dc current based on the ac current value of the remaining phase at the time of the 1-phase fault in the plurality of phases, based on the ac current output from the power conversion circuit 60 and the duty ratio of the PWM signal; and a failure determination unit 452 that detects a failure of the upper arm circuit or the lower arm circuit of any phase based on the dc current input to the power conversion circuit 60 or the dc current based on the ac current value output from the power conversion circuit 60, the duty ratio of the PWM signal, and the 1 st failure time pseudo dc current. This makes it possible to determine which part of the power semiconductors constituting the upper arm circuit and the lower arm circuit has failed.

(2) In the control method of power conversion device 100, power conversion circuit 60 is configured by an upper arm circuit and a lower arm circuit for each phase of motor 20 corresponding to a plurality of phases, and converts a direct current into an alternating current of the plurality of phases, outputs a PWM signal to the upper arm circuit and the lower arm circuit, calculates a 1 st fault-time analog direct current based on an alternating current value of a remaining phase at the time of a fault of the 1 phase among the plurality of phases based on the alternating current output by power conversion circuit 60 and a duty ratio of the PWM signal, and detects a fault of the upper arm circuit or the lower arm circuit of any phase based on the direct current input to power conversion circuit 60 or the direct current based on the alternating current value output from power conversion circuit 60, the duty ratio of the PWM signal, and the 1 st fault-time analog direct current. This makes it possible to determine which part of the power semiconductors constituting the upper arm circuit and the lower arm circuit has failed.

(modification example)

The present invention can be implemented by modifying the above-described embodiments 1 to 5 as follows.

(1) The motor 20 has been described as an example of three phases having 3 windings inside, but the motor is not limited to three phases and may be a multi-phase motor. In this case, a failure of the upper arm circuit or the lower arm circuit of any phase can be detected.

(2) The power conversion apparatus 100 internally has the ac current sensor 90 of an amount corresponding to three phases, but may have an amount of only 2 phases. In this case, the remaining 1-phase alternating current can be calculated using a case where the total of the three-phase alternating currents is 0, and a failure of the upper arm circuit or the lower arm circuit of any phase can be detected as in the case of the alternating current sensor 90 having an amount corresponding to three phases.

The present invention is not limited to the above-described embodiments, and other embodiments that can be considered within the scope of the technical idea of the present invention are also included within the scope of the present invention as long as the features of the present invention are not impaired. Further, a combination of the above embodiments may be employed.

Description of the reference symbols

10 DC power supply

20 electric motor

40 control circuit

41 motor speed calculating part

42 target current calculating part

43 duty ratio calculating part

44 PWM signal generating part

45 power semiconductor diagnostic unit

50 drive circuit

60 power conversion circuit

100 power conversion device

451 analog DC current calculating part

452 a failure determination unit.

Claims

1. A power conversion apparatus, comprising:

a power conversion circuit which is configured by an upper arm circuit and a lower arm circuit for each phase of a multi-phase motor and converts a direct current into a multi-phase alternating current;

a control circuit that outputs a PWM signal to the upper arm circuit and the lower arm circuit;

an analog direct current calculation unit that calculates a 1 st fault-time analog direct current based on an alternating current value of a remaining phase at the time of a 1-phase fault in the plurality of phases, based on the alternating current output by the power conversion circuit and a duty ratio of the PWM signal; and

and a failure determination unit that detects a failure of the upper arm circuit or the lower arm circuit of any phase based on a direct current input to the power conversion circuit or a direct current based on an alternating current value output from the power conversion circuit, a duty ratio of the PWM signal, and the 1 st failure time analog direct current.

2. The power conversion apparatus according to claim 1,

a DC current sensor for measuring a DC current inputted to the power conversion circuit,

the failure determination unit detects a failure of the upper arm circuit or the lower arm circuit of any phase based on the dc current measured by the dc current sensor.

3. The power conversion apparatus according to claim 1,

the analog direct current calculation section calculates the direct current according to the alternating current value output from the power conversion circuit based on the alternating current value output from the power conversion circuit and the duty ratio of the PWM signal,

the failure determination unit detects a failure of the upper arm circuit or the lower arm circuit of any phase based on the calculated direct current.

4. The power conversion apparatus according to any one of claims 1 to 3,

the simulated dc current calculation unit calculates a 2 nd fault-time simulated dc current based on all the ac current values of the plurality of phases, and detects a fault in the upper arm circuit and the lower arm circuit of any phase based on the 1 st fault-time simulated dc current and the 2 nd fault-time simulated dc current.

5. The power conversion apparatus according to any one of claims 1 to 3,

when the difference between the dc current and the 1 st failure-time simulated dc current of a certain phase is equal to or smaller than a predetermined value, the failure determination unit determines that the upper arm circuit of the phase has failed if the duty ratio of the phase is equal to or larger than a threshold value during powering of the motor or the duty ratio of the phase is equal to or smaller than a threshold value during regeneration of the motor.

6. The power conversion apparatus of claim 5,

when a state in which a difference between the dc current and the 1 st failure-time simulated dc current of a certain phase is equal to or less than a predetermined value continues for a predetermined time or longer, the failure determination unit determines that a failure has occurred in the upper arm circuit of the phase if the duty ratio of the phase is equal to or greater than a threshold value during powering of the motor or the duty ratio of the phase is equal to or less than a threshold value during regeneration of the motor.

7. The power conversion apparatus of claim 5,

the control circuit outputs the PWM signal in which all power semiconductors of the upper arm circuit and the lower arm circuit constituting the power conversion circuit are turned off or all power semiconductors of the lower arm circuit constituting the power conversion circuit are turned on, when the failure determination unit determines that the upper arm circuit has failed.

8. The power conversion apparatus according to any one of claims 1 to 3,

when the difference between the dc current and the 1 st failure-time simulated dc current of a certain phase is equal to or smaller than a predetermined value, the failure determination unit determines that the lower arm circuit of the certain phase has failed if the duty ratio of the certain phase is equal to or smaller than a threshold value during powering operation of the motor or the duty ratio of the certain phase is equal to or larger than a threshold value during regeneration of the motor.

9. The power conversion apparatus of claim 8,

when a state in which a difference between the dc current and the 1 st failure-time simulated dc current of a certain phase is equal to or less than a predetermined value continues for a predetermined time or longer, the failure determination unit determines that a failure has occurred in the lower arm circuit of the certain phase if the duty ratio of the certain phase is equal to or less than a threshold value during powering operation of the motor or the duty ratio of the certain phase is equal to or more than a threshold value during regeneration of the motor.

10. The power conversion apparatus of claim 8,

the control circuit outputs the PWM signal in which all power semiconductors of the upper arm circuit and the lower arm circuit constituting the power conversion circuit are turned off or outputs the PWM signal in which all power semiconductors of the upper arm circuit constituting the power conversion circuit are turned on, when the failure determination unit determines that the lower arm circuit has failed.

11. A control method of a power conversion apparatus,

a power conversion circuit is constituted by an upper arm circuit and a lower arm circuit for each phase of a multi-phase motor, and converts a direct current into a multi-phase alternating current,

outputting a PWM signal to the upper arm circuit and the lower arm circuit,

calculating a 1 st-fault-time analog direct current based on alternating current values of remaining phases at the time of a 1-phase fault among the plurality of phases based on the alternating current output by the power conversion circuit and the duty ratio of the PWM signal,

a fault of the upper arm circuit or the lower arm circuit of an arbitrary phase is detected based on a direct current input to the power conversion circuit or a direct current according to an alternating current value output from the power conversion circuit, a duty ratio of the PWM signal, and the 1 st fault-time analog direct current.

12. The control method of a power conversion apparatus according to claim 11,

and detecting a failure of the upper arm circuit or the lower arm circuit of any phase based on the dc current measured by the dc current sensor.

13. The control method of a power conversion apparatus according to claim 11,

calculating the direct current according to an alternating current value output from the power conversion circuit based on an alternating current value output from the power conversion circuit and a duty ratio of the PWM signal,

detecting a failure of the upper arm circuit or the lower arm circuit of an arbitrary phase based on the calculated direct current.

14. The control method of a power conversion apparatus according to any one of claims 11 to 13,

a2 nd fault-time simulation direct current based on all the alternating current values of the plurality of phases is calculated, and a fault of the upper arm circuit and the lower arm circuit of an arbitrary phase is detected based on the 1 st fault-time simulation direct current and the 2 nd fault-time simulation direct current.

15. The control method of a power conversion apparatus according to any one of claims 11 to 13,

when the difference between the direct current and the 1 st failure-time simulated direct current of a certain phase is equal to or less than a predetermined value, if the duty ratio of the phase is equal to or more than a threshold value during powering of the motor or the duty ratio of the phase is equal to or less than a threshold value during regeneration of the motor, it is determined that a failure has occurred in the upper arm circuit of the phase.

16. The control method of a power conversion apparatus according to claim 15,

when a state in which a difference between the dc current and the 1 st failure-time simulated dc current of a certain phase is equal to or less than a predetermined value continues for a predetermined time or longer, if the duty ratio of the phase is equal to or more than a threshold value during powering of the motor or the duty ratio of the phase is equal to or less than a threshold value during regeneration of the motor, it is determined that a failure has occurred in the upper arm circuit of the phase.

17. The control method of a power conversion apparatus according to claim 15,

when it is determined that the upper arm circuit has failed, the PWM signal is output such that all power semiconductors of the upper arm circuit and the lower arm circuit constituting the power conversion circuit are turned off or all power semiconductors of the lower arm circuit constituting the power conversion circuit are turned on.

18. The control method of a power conversion apparatus according to any one of claims 11 to 13,

when the difference between the direct current and the 1 st failure-time simulated direct current of a certain phase is equal to or less than a predetermined value, if the duty ratio of the phase is equal to or less than a threshold value during powering operation of the motor or the duty ratio of the phase is equal to or more than a threshold value during regeneration of the motor, it is determined that the lower arm circuit of the phase has failed.

19. The control method of a power conversion apparatus according to claim 18,

when a state in which a difference between the dc current and the 1 st failure-time simulated dc current of a certain phase is equal to or less than a predetermined value continues for a predetermined time or longer, if the duty ratio of the phase is equal to or less than a threshold value during powering operation of the motor or the duty ratio of the phase is equal to or more than a threshold value during regeneration of the motor, it is determined that the lower arm circuit of the phase has failed.

20. The control method of a power conversion apparatus according to claim 18,

when it is determined that the lower arm circuit has failed, the PWM signal is output such that all power semiconductors of the upper arm circuit and the lower arm circuit constituting the power conversion circuit are turned off, or the PWM signal is output such that all power semiconductors of the upper arm circuit constituting the power conversion circuit are turned on.