JP6690466B2 - Power system - Google Patents

Description

  This specification discloses a power supply system. In particular, a plurality of voltage conversion converters are connected in parallel between a DC power supply and an inverter, and a power supply system for a motor vehicle (including a hybrid vehicle) that runs by connecting a motor to the inverter is disclosed.

  Some motor vehicles include a converter that boosts the voltage of a DC power supply and supplies the voltage to an inverter. Further, since the traveling motor may function as a generator, some motor vehicles charge the DC power source by reducing the voltage generated by the traveling motor with a converter. Such a motor vehicle utilizes a buck-boost converter.

  As disclosed in Patent Document 1, a technique has been developed in which a plurality of step-up / down converters are connected in parallel between a DC power supply and an inverter. Rather than covering the range from low output to high output with one buck-boost converter, it is better to adjust the number of buck-boost converters to operate according to the amount of electric power required for the motor. Opportunities to utilize the output range with high power conversion efficiency increase. Alternatively, it is possible to suppress the fluctuation of the output voltage by shifting the phases among the plurality of buck-boost converters.

  The buck-boost converter is composed of a positive electrode end on the power source side connected to the positive electrode of the DC power source, a negative electrode end on the power source side connected to the negative electrode of the DC power source, an inverter side positive electrode end connected to the positive electrode of the inverter, and an inverter. The negative electrode end on the inverter side connected to the negative electrode, two switching elements connected in series between the positive electrode end on the inverter side and the negative electrode end on the inverter side, and one end connected to the positive electrode end on the power source side. The reactor has the other end connected to the connecting portion of the two switching elements described above.

  In the above step-up / step-down converter, the high voltage sent from the inverter is switched by turning on / off the switching element on the positive electrode end side of the inverter (herein referred to as the upper arm switching element) of the two switching elements. Step down and charge the DC power supply. On the contrary, by turning on / off the switching element on the negative electrode end side of the inverter (hereinafter referred to as the lower arm switching element), the voltage of the DC power supply is boosted and supplied to the inverter.

JP, 2012-210138, A

  In the case of a power supply system in which a plurality of buck-boost converters are connected in parallel, the upper arm switching element of any of the buck-boost converters may fail on (fails to turn off at all times). In that case, when the other upper arm switching element of the step-up / down converter is turned on, a circuit for connecting the DC power supply and the inverter in parallel with a plurality of reactors is formed. The total inductance decreases when the reactors are connected in parallel. Comparing the circuit in which the DC power supply and the inverter are connected by a single reactor with the circuit in which the DC power supply and the inverter are connected by a parallel circuit of multiple reactors When using the latter circuit rather than the former circuit, a large inrush current flows to the DC power supply side, the voltage on the DC power supply side rises excessively, and a secondary failure occurs.

  In the present specification, in a power supply system in which a plurality of buck-boost converters are connected in parallel between a DC power supply and an inverter, even if an ON failure occurs in the upper arm switching element of any of the buck-boost converters, the DC power supply A technique in which an excessively large voltage is not applied to the side is disclosed.

The power supply system disclosed in this specification includes a DC power supply, an inverter, a plurality of step-up / down converters connected in parallel between the DC power supply and the inverter, a failure detection device, and a controller.
Each of the buck-boost converters has a power supply side positive end connected to the positive pole of the DC power supply, a power supply side negative end connected to the DC power supply negative pole, and an inverter side positive end connected to the inverter positive pole. , A negative electrode end on the inverter side connected to the negative electrode of the inverter. The positive electrode and the negative electrode of the inverter here correspond to the high potential side and the low potential side, the high potential side is called the positive electrode, and the low potential side is called the negative electrode. Two switching elements are connected in series between the inverter-side positive electrode end and the inverter-side negative electrode end. Each of the step-up / down converters further includes a reactor. One end of the reactor is connected to the positive electrode end on the power supply side, and the other end of the reactor is connected to the connecting portion of the two switching elements.
The failure detection device detects that the switching element (upper arm switching element) on the positive electrode end side of the inverter of one of the step-up / down converters has an on failure. The controller holds the upper arm switching elements of the other buck-boost converters in the off state for a predetermined time when the failure detection device detects an on-failure of the upper arm switching element of any of the buck-boost converters.

According to the technique disclosed in the present specification, when an ON failure occurs in an upper arm switching element of any of the step-up / down converters, the upper arm switching element of another step-up / down converter is held in an OFF state. As a result, a circuit that connects the DC power supply and the inverter in parallel with a plurality of reactors is not formed. As a result, it is possible to prevent a large inrush current from flowing to the DC power supply side, which causes an excessive increase in the voltage on the DC power supply side to cause a secondary failure.
Details of the technology disclosed in the present specification and further improvements will be described in the following “Description of Embodiments”.

It is a block diagram of the electric power system of electric vehicle 100 including power supply system 2 of an example. 7 is a flowchart of an on-failure monitoring process performed by the failure detection device 12. 6 is a flowchart of switching control of an upper arm switching element executed by a controller 9. 5 is a time chart showing the switching operation of the upper arm switching element and the transitions of the inverter side voltage and the power source side voltage. 7 is another flowchart of the failure determination by the failure detection device 12.

The main features of the embodiments described below are listed.
(Characteristic 1) The upper arm switching element in which the ON failure has occurred is specified, and the control procedure of the other upper arm switching elements (which have not been in the ON failure) is switched to that for the abnormal time.
(Characteristic 2) Although it is detected that an ON failure has occurred in any one of the upper arm switching elements, the upper arm switching element having the ON failure is not specified. The control procedure of all the upper arm switching elements is switched to the one for abnormal times.
(Feature 3) A plurality of converters connected in parallel are commonly controlled.
(Feature 4) A plurality of converters connected in parallel are individually controlled.
(Characteristic 5) A converter to be operated is selected from a plurality of converters connected in parallel.

A power supply system 2 of the embodiment will be described with reference to FIG. The electric vehicle 100 runs by supplying drive power from the power supply system 2 to the running motor 30. The power supply system 2 is mounted on the electric vehicle 100.
The electric vehicle 100 of the embodiment includes a DC power source 3, two step-up / down converters 10a and 10b, an inverter 20, a traveling motor 30, and the like. The DC power supplied from the DC power supply 3 is converted into AC power by the inverter 20, and the AC motor drives the traveling motor 30 to rotate and the electric vehicle 100 travels. When the driver steps on the brake, the motor 30 is reversely driven from the output shaft side, and the motor 30 generates power. The AC power generated by the motor 30 is converted into DC power by the inverter 20 to charge the DC power supply 3. The motor 30 generating torque to drive the vehicle is referred to as “power running”, and the motor 30 functioning as a generator to generate electric power is referred to as “regeneration”. The electric power generated by regeneration is called regenerative electric power. The regenerative power is used to charge the DC power supply 3.

  The power supply system 2 includes, in addition to the DC power supply 3 and the inverter 20, two buck-boost converters 10a and 10b, a failure detection device 12, a controller 9, a system main relay 13, a filter capacitor 14, a smoothing capacitor 15, and the like. In the power supply system 2, each of the two step-up / down converters 10 a and 10 b boosts the DC voltage supplied from the DC power supply 3 and supplies the boosted DC voltage to the inverter 20. Further, each of the step-up / down converters 10 a and 10 b can reduce the regenerative electric power sent from the inverter 20 to charge the DC power supply 3. That is, the buck-boost converters 10a and 10b are bidirectional DC-DC converters. Below, the buck-boost converter 10a may be called the 1st converter 10a, and the buck-boost converter 10b may be called the 2nd converter 10b.

  The DC power supply 3 is, for example, a lithium ion battery, and is a secondary battery. Two buck-boost converters 10a and 10b are connected in parallel between the DC power supply 3 and the inverter 20. The DC power supply 3 side is referred to as a power supply side 17 and the inverter 20 side is referred to as an inverter side 18 as viewed from the buck-boost converters 10a and 10b. A terminal connected to the positive electrode of the DC power supply 3 is called a power supply side positive electrode end 17a, and a terminal connected to the negative electrode of the DC power supply 3 is called a power supply side negative electrode end 17b. A terminal connected to the high potential pole of the inverter 20 is called an inverter-side positive electrode end 18a, and a terminal connected to the low potential pole of the inverter 20 is called an inverter-side negative electrode end 18b. The power supply side positive electrode end 17a, the power supply side negative electrode end 17b, the inverter side positive electrode end 18a, and the inverter side negative electrode end 18b are common to the first converter 10a and the second converter 10b.

  A system main relay 13 is connected between the DC power supply 3 and the two buck-boost converters 10a and 10b. The system main relay 13 is linked with a main switch (not shown) of the vehicle. When a main switch (not shown) of the vehicle is turned on, the system main relay 13 is closed and the DC power supply 3 is connected to the two step-up / down converters 10a and 10b. When the main switch is turned off, the system main relay 13 is opened, and the two buck-boost converters 10a and 10b are disconnected from the DC power supply 3.

  The first converter 10a and the second converter 10b have the same circuit configuration. The first converter 10a will be described. The first converter 10a includes a reactor 4a, two transistors 5a and 6a, and two diodes 7a and 8a. The two transistors 5a and 6a are IGBTs (Insulated Gate Bipolar Transistors). The two transistors 5a and 6a are connected in series. The high potential side of the series connection of the two transistors 5a and 6a is connected to the inverter side positive electrode end 18a, and the low potential side is connected to the inverter side negative electrode end 18b. For convenience of explanation, the transistor on the high potential side may be referred to as the upper arm transistor 5a, and the transistor on the low potential side may be referred to as the lower arm transistor 6a. The diode 7a is connected in antiparallel to the high potential side transistor 5a, and the diode 8a is connected in antiparallel to the low potential side transistor 6a. One end of the reactor 4a is connected to the positive electrode end 17a on the power source side, and the other end is connected to the connecting portion of the two transistors 5a and 6a. The inverter side negative electrode end 18b and the power source side negative electrode end 17b are directly connected.

  The second converter 10b includes two transistors 5b and 6b, a reactor 4b, and diodes 7b and 8b. As understood from FIG. 1, the circuit configuration of the second converter 10b is the same as the circuit configuration of the first converter 10a. Therefore, the detailed explanation is omitted. For convenience of description, of the two transistors 5b and 6b, the transistor on the high potential side may be referred to as the upper arm transistor 5b, and the transistor on the low potential side may be referred to as the lower arm transistor 6b.

  The filter capacitor 14 is connected between the power supply side positive electrode end 17a and the power supply side negative electrode end 17b. The filter capacitor 14 is a capacitor common to the two step-up / down converters 10a and 10b, and temporarily stores or releases electric energy in cooperation with the reactors 4a and 4b. The smoothing capacitor 15 is connected between the inverter-side positive electrode end 18a and the inverter-side negative electrode end 18b. The smoothing capacitor 15 is also a capacitor common to the two buck-boost converters 10a and 10b, and suppresses the pulsation of the current supplied from the buck-boost converters 10a and 10b to the inverter 20 to smooth the current.

  As described above, the step-up / step-down converters 10a and 10b boost the voltage of the DC power supply 3 and supply it to the inverter 20, and reduce the regenerative power sent from the inverter 20 and supply it to the DC power supply 3. A step-down operation can be performed. The lower arm transistor 6a of the first converter 10a participates in the step-up operation, and the upper arm transistor 5a participates in the step-down operation. Similarly, the lower arm transistor 6b of the second converter 10b participates in the step-up operation, and the upper arm transistor 5b participates in the step-down operation. Each of the transistors 5a, 5b, 6a, 6b is switched on and off by a PWM signal (drive signal) given to the gate from the controller 9. The controller 9 generates a PWM signal for driving the transistors 5a, 5b, 6a, 6b. For convenience of explanation, the drive signal supplied to the upper arm transistor 5a is referred to as an A1 drive signal, and the drive signal supplied to the lower arm transistor 6a is referred to as an A2 drive signal. Similarly, the drive signal supplied to the upper arm transistor 5b is referred to as a B1 drive signal, and the drive signal supplied to the lower arm transistor 6b is referred to as a B2 drive signal. “A1”, “A2”, “B1”, and “B2” in the figure mean the A1 drive signal, the A2 drive signal, the B1 drive signal, and the B2 drive signal, respectively.

  In the electric vehicle 100, the accelerator pedal and the brake pedal are frequently changed over. That is, in the electric vehicle 100, power running and regeneration are frequently switched. That is, the directions of the currents in the first converter 10a are frequently changed. Therefore, the controller 9 of the power supply system 2 supplies a complementary drive signal (PWM pulse signal) to the transistors 5a and 6a. Specifically, a PWM signal obtained by inverting the HIGH potential and the LOW potential of the PWM signal (A2 drive signal) supplied to the lower arm transistor 6a involved in the boosting operation is supplied to the upper arm transistor 5a as the A1 drive signal. Then, the first converter 10a operates so as to keep the ratio of the voltage on the low voltage side and the voltage on the high voltage side constant regardless of the direction of the current. The same applies to the second converter 10b. That is, the controller 9 supplies complementary drive signals (PWM pulse signals) to the transistors 5b and 6b. Specifically, a PWM signal obtained by inverting the HIGH potential and the LOW potential of the PWM signal (B2 drive signal) supplied to the lower arm transistor 6b involved in the boosting operation is supplied to the upper arm transistor 5b as the B1 drive signal.

The controller 9 supplies drive signals (A1 drive signal and B1 drive signal) having the same waveform to the upper arm transistors 5a and 5b of the respective step-up / down converters so that the first converter 10a and the second converter 10b perform the same operation. To do. Similarly, the controller 9 supplies drive signals (A2 drive signal and B2 drive signal) having the same waveform to the lower arm transistors 6a and 6b of the respective step-up / down converters. Here, the same waveform means that the duty ratio is the same. The controller 9 determines the target rotation speed and the target torque of the motor 30 based on the vehicle state (for example, the charge amount of the DC power supply 3) such as the depression amount of an accelerator pedal (not shown), and the target of the converters 10a and 10b is determined from these. Determine the voltage. The duty ratio of the drive signal given to each transistor, that is, the PWM signal is determined so that the target voltage is realized. As described above, the upper arm transistors 5a and 5b have the same duty ratio, and the lower arm transistors 6a and 6b also have the same duty ratio.
In this embodiment, the A1 drive signal and the B1 drive signal are common, and the A2 drive signal and the B2 drive signal are common. Two converters 10a and 10b connected in parallel are commonly controlled. In this embodiment, only one of the two inverters 10a and 10b can be operated. For example, the B1 drive signal and the B2 drive signal can be fixed to OFF and only the converter 10a can be operated. When the amount of power passing through the inverter is low, only one of the inverters can be used and the other inverter can be suspended. Instead of the above, a phase difference may be provided between the A1 drive signal and the B1 drive signal. By shifting the phase, it is possible to reduce pulsation such as output voltage. Alternatively, the A1 drive signal and the B1 drive signal may be controlled independently.

  The target voltages of the two buck-boost converters 10a and 10b are determined with reference to the voltage map stored in the controller 9. The voltage map is a map in which the horizontal axis represents the target rotational speed of the motor 30 and the vertical axis represents the target torque of the motor 30, and the coordinate system is divided into a plurality of regions. The voltage assigned to the region to which the set of the target rotation speed and the target torque of the motor 30 belongs becomes the target voltage.

  Further, the power supply system 2 includes a first ammeter 12a for detecting a current value ia flowing through the first upper arm switching element 5a and a second ammeter for detecting a current value ib flowing through the second upper arm switching element 5a. 12b is provided. The first ammeter 12a and the second ammeter 12b are connected to the failure detection device 12.

  FIG. 2 shows an on-failure monitoring process of the upper arm transistors 5a and 5b by the failure detection device 12. In steps 1 and 2, it is monitored whether or not a current flows through the first upper arm transistor 5a even though the off voltage is applied to the gate of the first upper arm transistor 5a. If the ON failure occurs in the first upper arm transistor 5a, step 2 is YES. In that case, in step 3, the first flag indicating that an on-failure has occurred in the first upper arm transistor 5a is turned on. In steps 4 and 5, it is monitored whether or not a current flows through the second upper arm transistor 5b even though the off voltage is applied to the gate of the second upper arm transistor 5b. If the second upper arm transistor 5b has an ON failure, step 5 becomes YES. In that case, in step 6, the second flag indicating that an on-failure has occurred in the second upper arm transistor 5b is turned on. The process of FIG. 2 is repeatedly executed at single time intervals. When the on-failure occurs, steps 3 and 6 are executed, and the flag indicating the on-failure is turned on. Note that “turning on the flag” means storing a predetermined value (for example, “1”) in the “flag” which is a variable on the program. In the subroutine of FIG. 3, which is a subroutine different from the subroutine of FIG. 2, the value of the “flag” is referred to, and different processing is executed depending on whether or not an ON failure has occurred.

  The controller 9 performs switching control of the upper arm transistors 5a and 5b of the step-up / down converters 10a and 10b based on the determination information from the failure detection device 12.

FIG. 3 shows a processing procedure in which the controller 9 controls switching of the upper arm transistors 5a and 5b. The switching control flow of the upper arm transistor will be described with reference to FIG. In step 11, it is determined whether or not at least one of the first flag and the second flag is on. If both are off, the process at the time of abnormality is skipped and the process for that time is ended.
If one of the upper arm transistors has an on-failure, it is determined whether or not the timing at which the process of FIG. 3 is executed is within a period for turning on the upper arm transistor that has not been on-failure. If it is within the ON period (YES in S12), the upper arm transistor (normal switching element without ON failure) is forcibly turned OFF (S14). If it is within the OFF period (NO in S12), the upper arm transistor (normal switching element that has not failed to turn ON) is kept OFF for a predetermined time (S13). This prevents both the upper arm transistor that has failed to turn on and the upper arm transistor that has not failed to turn on from turning on. For a predetermined time after the ON failure, both are prevented from turning ON. Note that step 13 and step 14 are processes that are executed when an abnormality occurs, and are not executed when normal.

  FIG. 4 shows the state of the upper arm transistor 5a of the first converter 10a, the switching operation of the upper arm transistor 5b of the second converter 10b, and the transitions of the inverter-side voltage VH and the power supply-side voltage VL. FIG. 4 exemplifies a case where an ON failure has occurred in the first upper arm transistor 5a.

The horizontal axis of FIG. 4 indicates the passage of time. Graph A shows the state of the first upper arm transistor 5a of the first converter 10a. FIG. 4 exemplifies a case where the first upper arm transistor 5a has an ON failure at time t1. In this case, as shown in the graph B, the first flag is turned on, which indicates that the first upper arm transistor 5a has an on-failure.
A graph C1 indicated by a solid line shows a state change of the second upper arm transistor 5b in the case where the present technology is not used, and the constant duty ratio is maintained even after the time t2 when it is determined that the on-arm failure has occurred in the upper arm transistor 5a. Then, the on / off operation is repeated. On the other hand, the graph C2 indicated by the broken line is the second upper case in the case where the present technique (a technique of keeping a normal upper arm transistor off for a certain period of time if one of the upper arm transistors fails to turn on) The state change of the arm transistor 5b is shown, and after the time t2 when it is determined that the on-arm failure has occurred in the upper arm transistor 5a, it is kept off for a certain period of time.

  Before time t1, both the first upper arm transistor 5a and the second upper arm transistor 5b are normal, and the switching operation is performed at a constant duty ratio. In this case, the voltage VH on the inverter side shows a boosted voltage value of 650 V as shown in Graph D. Further, the power supply side voltage VL is maintained at a constant voltage of 300V as shown in the graphs E1 and E2.

The graph E1 shows a change in the power supply voltage VL when the present technology is not used. In addition to the first upper arm transistor 5a that has failed to turn on, the second upper arm transistor 5b that operates normally is turned on by a parallel circuit of the reactors 4a and 4b between the DC power supply 3 and the smoothing capacitor 15. It will be connected. Therefore, a large inrush current flows from the smoothing capacitor 15 (where 650V was applied) to the DC power supply 3 (maintained at 300V). As indicated by the solid line graph E1 in FIG. 4, the power supply side voltage temporarily rises to a large value.
A graph E2 indicated by a broken line shows a change in the power supply voltage VL according to the present technology. Only the first upper arm transistor 5a that has failed to turn on is turned on, and the normally operating second upper arm transistor 5b is kept off. Therefore, only the reactor 4a is provided between the DC power supply 3 and the smoothing capacitor 15. Connected through. Therefore, a large inrush current does not flow from the smoothing capacitor 15 to the DC power supply 3. As shown by the graph E2 indicated by the broken line in FIG. 4, the power supply side voltage temporarily rises, but its peak value is suppressed to be smaller than the peak value of the graph E1.

  In any case, if the voltage of the smoothing capacitor 15 becomes equal to the voltage of the DC power supply 3, the inrush current stops flowing and the voltage of the smoothing capacitor 15 becomes equal to the voltage of the DC power supply 3. In the process of FIG. 4, the upper arm switching element that normally operates is kept off until then.

  It should be noted that the shorter the time from when the upper arm transistor 5a is turned on to when the failure is determined, that is, the shorter the time from time t1 to time t2, the more quickly the power supply side voltage VL rise can be suppressed, which is more effective. is there.

  In the above description, the case where the upper arm transistor 5a of the first converter 10a has an ON failure has been described. However, even when the upper arm transistor 5b of the second converter 10b has an ON failure, the same control by the controller 9 causes the upper arm transistor 5a to operate. 5a is kept off for a predetermined time. For this reason, the ON states of the upper arm transistors of both converters do not overlap, and it is possible to prevent damage to the element on the power supply side due to the inrush current.

The on-failure monitoring process is not limited to that shown in FIG. For example, it may be used in the technique described in Japanese Patent Laid-Open No. 2007-068305. In that case, the voltage VL on the power source side of the DC power source and the voltage VH on the inverter side are detected, and the processing of FIG. 5 is performed.
In step 21, it is determined whether or not the absolute value ΔV1 of the potential difference between the inverter side voltage VH and the power source side voltage VL is equal to or greater than the threshold value A. The value of A is set to the minimum potential difference when the converters 10a and 10b normally step up and down. Further, it is determined whether or not the absolute value ΔV2 of the potential difference between the target voltage VP and the inverter-side voltage VH described above is equal to or less than the threshold value B. The value of B is set to the maximum error when the converters 10a and 10b are operating normally. If ΔV1 is A or more and ΔV2 is B or less, it can be seen that converters 10a and 10b are operating normally. In that case, the process proceeds to step 25.
If step 21 is NO, that is, if ΔV1 <A or ΔV2> B, then the duration is compared with the threshold value C. If the on-failure occurs, the threshold value C is exceeded, and the process proceeds to step 23. If the normal condition is satisfied before the threshold value C is exceeded, step 25 is executed. If an ON failure occurs in any of the converters 10a and 10b, the process proceeds from step 23 to step 24, and the failure determination flag is turned on.

  In the process of FIG. 5, it is not known which of the first upper arm transistor 5a and the second upper arm transistor 5b has the ON failure. In this embodiment, the first converter 10a and the second converter 10b are simultaneously controlled in the same manner. In this case, if an ON failure occurs in either the first upper arm transistor 5a or the second upper arm transistor 5b, both the first upper arm transistor 5a and the second upper arm transistor 5b are turned off. When both the first upper arm transistor 5a and the second upper arm transistor 5b are commonly controlled, an ON failure has occurred in either the first upper arm transistor 5a or the second upper arm transistor 5b. Need only be known, and it may be unclear which one has failed.

  In the above embodiment, the control in the power supply system in which two buck-boost converters are connected in parallel has been described. However, the technology disclosed in this specification can also be applied to a power supply system in which three or more buck-boost converters are connected in parallel. In that case, when it is determined that one of the three or more buck-boost converters has an ON failure in one buck-boost converter, the other two or more buck-boost converter upper-arm transistors are switched. By keeping the off state for a certain period of time, a secondary failure can be prevented.

  In the above-described embodiment, in the on-failure determination, the on-failure of the upper arm transistor is determined based on the potential difference between the power supply side voltage and the inverter side voltage and the difference between the output side target voltage and the actually measured value. However, the on failure determination is not limited to this, and any known on failure determination can be applied.

  In the power supply system 2 of the embodiment, when the failure detection device 12 detects an ON failure of the upper arm transistor of any of the buck-boost converters, the controller 9 turns off the upper arm transistors of the other buck-boost converters for a predetermined time. Hold. Here, the "predetermined time" is set to the time until the generated inrush current becomes sufficiently small. The time is determined depending on the characteristics of the reactors 4a and 4b and the characteristics of the smoothing capacitor 15.

  The transistors 5a, 6a, 5b, 6b in the above embodiment correspond to an example of the "switching element" in the claims. The “switching element” is not limited to the IGBT. The “switching element” in the claims may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or other element.

  Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings can simultaneously achieve a plurality of objects, and achieving the one object among them has technical utility.

2: Power supply system 3: DC power supplies 4a, 4b: Reactors 5a, 6a, 5b, 6b: Transistors 7a, 8a, 7b, 8b: Diode 9: Controller 10a: First buck-boost converter 10b: Second buck-boost converter 12: Failure detection devices 12a and 12b: Ammeter 13: System main relay 14: Filter capacitor 15: Smoothing capacitor 17a: Power supply side positive end 17b: Power supply side negative end 18a: Inverter side positive end 18b: Inverter side negative end 20: Inverter 30 : Motor 100: Electric Vehicle

Claims (1)

A DC power supply, an inverter, a plurality of step-up / down converters connected in parallel between the DC power supply and the inverter, a failure detection device, and a controller,
Each of the step-up / down converters has a power supply side positive electrode end connected to the positive electrode of the DC power supply, a power supply side negative electrode end connected to the negative electrode of the DC power supply, and an inverter side positive electrode end connected to the positive electrode of the inverter. An inverter-side negative electrode end connected to the negative electrode of the inverter; two switching elements connected in series between the inverter-side positive electrode end and the inverter-side negative electrode end; And a reactor whose other end is connected to the connecting portion of the two switching elements,
The failure detection device detects that the switching element (upper arm switching element) on the inverter-side positive end of one of the step-up / down converters has an ON failure,
A power supply system in which the controller holds the upper arm switching elements of the other buck-boost converters in an off state for a predetermined time when the failure detection device detects an on-failure of one of the upper arm switching elements of the buck-boost converter. .

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