JP2010246182A - Failure detector for inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the open failure of the switching element of an inverter. <P>SOLUTION: A failure detector is provided with a failure detector 31 into which the output currents of the phases U, V and W of an inverter 104 are inputted. The failure detector 31 has a means which detects the amplitude peak value in the first half period of the output current from the switching element, a means which detects the amplitude peak value in the latter half period following the first half period of the output current, and a means which outputs a failure detection signal on the switching element in case that the amplitude peak value in the first half period or the amplitude peak value in the latter half period is nearly zero and that a difference between the amplitude peak value in the first half period and the amplitude peak value in the latter half period is over a threshold. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inverter failure detection device, and more particularly to a technique for detecting a failure of a switching element of an inverter.

  Conventionally, a technique for detecting a failure of a switching element of an inverter has been proposed. For example, Patent Document 1 uses a logical product of a gate pulse signal input to a gate drive circuit of a switching element of an inverter and a polarity signal indicating a polarity of a command value of an inverter output current in phase with the switching element. It is described that an open failure of a switching element is detected.

  FIG. 6 shows an overall configuration diagram of an inverter provided with the failure detection apparatus according to the prior art.

  The speed of the motor M is detected by the speed sensor 13 and the speed calculation circuit 14. The target speed ω * of the motor is given to the subtractor 15 from the outside, and a deviation Δω from the detected speed ω is obtained here. The obtained deviation Δω is input to a deviation speed control circuit (ASR) 16, and the ASR 16 generates a target value It * of the torque current component of the motor current so as to reduce the deviation speed Δω. The generated target value It * is input to the subtractor 17, and a deviation ΔIt from the detected value It of the torque current component is obtained. The torque current component deviation ΔIt is input to the torque current control circuit (ACR-q) 18, and the ASR-q 18 generates a q-axis voltage component target value Vq * to reduce the deviation ΔIt to 3 / Outputs to 2-phase conversion circuit 21. The motor current is detected by the current detector 19 and converted by the 2/3 phase conversion circuit 20 from the 3 phase to the d / q axis two phase components Im and It corresponding to the excitation current component and the torque current component.

  The target value Im * of the excitation current component of the motor M is given from the excitation current setting unit 22. The subtractor 23 obtains a deviation ΔIm between the target value Im * of the exciting current component and the detected value Im. The exciting current control circuit (ACR-d) 24 takes the deviation ΔIm from the subtractor 23, generates the target value Vd * of the d-axis voltage component so as to reduce the deviation ΔIm, and supplies it to the 3/2 phase conversion circuit 21. Output.

  The 3 / 2-phase conversion circuit 21 takes in the generated target values Vq * and Vd * of the two voltage components and converts them into three-phase (u, v, w) voltage target values Vu *, Vv *, and Vw *. And output to the adder 25 (a, b, c). The voltage distortion compensation signals Fu, Fv, and Fw are input from the voltage distortion correction circuit 26 to the other input terminals of the adder 25 (a, b, c). The phase difference detection circuit 27 is a circuit that detects the rotational phase θ of the motor M necessary for the phase conversion and voltage distortion correction circuit 26 such as the 2/3 phase conversion circuit 20.

  The PWM pulse generator 12 takes in the corrected voltage target values Vu, Vv, Vw, modulates them with a PWM carrier wave, and gate pulse signals GP (u, v, w) of the switching elements of the arms of the inverter circuit 11, GN (u, v, w) is generated and output to the inverter circuit 11. The gate pulse signals GP and GN are each amplified by a driver circuit and applied to the gates of the switching elements of the positive arm and the negative arm of the inverter circuit 11. Note that during the period when the switching element is off, current circulates through the free-wheeling diodes connected in reverse parallel to the switching elements.

  The failure prediction device 30 calculates the logical product of the gate pulse signal Gpu and the polarity signal Fu indicating the polarity of the command value of the inverter output current in phase with the switching element. Further, the current signal obtained by shaping the current of the polarity corresponding to the polarity signal of the detection current of the inverter output current corresponding to the switching element with a certain threshold value is compared with the logical product. As a result of the comparison, an inverter failure prediction signal is output when there is a mismatch beyond a certain range.

JP-A-7-163155

  In the above prior art, a failure is detected by assuming that the logical product signal corresponds to a normal signal for each positive or negative polarity of the gate pulse signal, and that the signal obtained by waveform shaping corresponds to the feedback signal corresponding to the normal signal. ing.

  However, even if the inverter output current in the same phase as the switching element is normal, an imbalance between the switching element of the upper arm (positive arm) and the switching element of the lower arm (negative arm) and the offset error of the current detector Due to the variation in the frequency, a deviation may occur between the amplitude in the first half of one cycle and the amplitude in the second half. In this case, since the signal obtained by waveform shaping changes, a mismatch occurs between the logical product signal and the waveform shaping signal, and even if the switching element is normal, the failure prediction signal is erroneously output. There is a problem.

  The present invention provides an apparatus that can more reliably detect a failure of a switching element of an inverter.

  The present invention is a detection device for detecting a failure of a switching element of an inverter, the means for detecting an amplitude peak value of the first half period of an output current from the switching element, and a second half period following the first half period of the output current The amplitude peak value of the first half cycle or the amplitude peak value of the second half cycle is close to 0, and the amplitude peak value of the first half cycle and the amplitude peak value of the second half cycle are And a means for outputting a failure detection signal of the switching element when the deviation exceeds a threshold value.

  In one embodiment of the present invention, the outputting means has an amplitude peak value of the first half cycle or an amplitude peak value of the second half cycle close to 0, and the amplitude peak value of the first half cycle and the second half cycle. When the time over which the deviation from the amplitude peak value exceeds the threshold exceeds the threshold time, a failure detection signal for the switching element is output.

  ADVANTAGE OF THE INVENTION According to this invention, the failure of the switching element of an inverter can be detected more reliably.

It is a configuration block diagram of an embodiment. It is a basic composition block diagram of the failure detection device of an embodiment It is a configuration block diagram of a failure detection device of an embodiment. It is a timing chart of an embodiment. It is a processing flowchart of an embodiment. It is a structure block diagram of a prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the overall configuration of an inverter device including a failure detection device according to this embodiment. The inverter device includes a power supply circuit, an inverter main circuit, and a motor generator driven by the inverter main circuit, and is mounted on, for example, an electric vehicle or a hybrid vehicle. Below, the case where it mounts in a hybrid vehicle is demonstrated as an example.

  Motor generator MG is connected to drive wheels (not shown) and is incorporated as a motor that drives the drive wheels. Motor generator MG includes a U-phase, V-phase, and W-phase three-phase coil as a stator coil. One end of each phase coil forming the three-phase coil is connected to each other to form a neutral point. The other end of each phase coil is connected to the connection point of the switching transistor of each phase arm of inverter 104.

  The positive electrode of the battery 100 as a power source is connected to the power supply line (positive side), and the negative electrode of the battery 100 is connected to the ground line (negative side). The capacitor C1 is connected between the power supply line and the ground line. The battery 100 is a DC power source that can be charged and discharged, and is composed of, for example, a nickel metal hydride battery or a lithium ion battery. Battery 100 outputs DC power to boost converter 102. Battery 100 is charged by boost converter 102 during regenerative braking of the vehicle. Instead of the battery 100, a large capacity capacitor or a fuel cell may be used.

  Boost converter 102 includes a reactor L, switching transistors Q1 and Q2, and diodes D1 and D2. Switching transistors Q1 and Q2 are connected in series between the power supply line and the ground line. Diodes D1 and D2 are connected in antiparallel to the switching transistors Q1 and Q2, respectively. One end of the reactor L is connected to the connection point of the switching transistors Q1 and Q2, and the other end is connected to the power supply line. As the switching transistors Q1 and Q2, an npn transistor, IGBT, power MOSFET, or the like can be used. Capacitor C2 is connected between the power supply line and the ground line. The capacitor C2 smoothes voltage fluctuation between the power supply line and the ground line.

  Boost converter 102 boosts the DC voltage from battery 100 using reactor L based on a signal from a control device (not shown), and outputs the boosted voltage to the power supply line. That is, boost converter 102 boosts a DC voltage by accumulating current flowing according to switching operation of switching transistor Q2 as magnetic field energy in reactor L, and supplies power via diode D1 at the timing when switching transistor Q2 is turned off. Output to line.

  Inverter 104 includes a U-phase arm, a V-phase arm, and a W-phase arm. The U-phase arm, V-phase arm, and W-phase arm are connected in parallel with each other between the power supply line and the ground line. The U phase arm includes switching transistors Q11 and Q12 connected in series with each other, the V phase arm includes switching transistors Q13 and Q14 connected in series with each other, and the W phase arm includes switching transistors connected in series with each other. Transistors Q15 and Q16 are included. A diode is connected in antiparallel to each of the switching transistors Q11, Q12, Q13, Q14, Q15, and Q16.

  Inverter 104 converts a DC voltage supplied from the power supply line into a three-phase AC voltage based on a PWM signal from a control device (not shown) and outputs the same to motor generator MG. In addition, during regenerative braking of the vehicle, inverter 104 receives the rotational force from the drive wheels and converts the three-phase AC voltage generated by motor generator MG into a DC voltage and outputs the DC voltage to the power supply line.

  The failure detection device 31 detects an open failure of at least one of the switching transistors Q11 to Q16 of the inverter 104 based on the inverter output current output from at least one of the U-phase arm, V-phase arm, and W-phase arm of the inverter 104. Detect. The failure detection device 31 outputs a detection signal to the control device when detecting a failure of at least one of the switching transistors Q11 to G16.

  In the present embodiment, a case where an open failure of the switching transistor Q11 of the U-phase arm is detected will be described as an example. In this case, the U-phase inverter output current is detected by the current detector 19 and supplied to the failure detection device 31.

  The failure detection device 31 detects an open failure of the U-phase switching element of the inverter 104 based on the U-phase inverter output current and outputs a detection signal to a control device (not shown).

FIG. 2 shows a basic configuration block diagram of the failure detection device 31. The failure detection device 31 includes a first peak hold circuit 31a that holds an amplitude peak value P1 of the first half of one cycle of the U-phase inverter output current, and an amplitude peak value P2 of the second half cycle that follows that of one cycle. The peak peak value P1 of the first half cycle or the amplitude peak value P2 of the second half cycle is close to 0, and the amplitude peak value P1 of the first half cycle and the amplitude peak value P2 of the second half cycle The output circuit 31z outputs a failure detection signal of the switching element under a certain condition when the deviation of exceeds a threshold value. For example, the detection signal is output as a binary signal having a logic level of 0 (Low) when normal and a logic level of 1 (Hi) when a certain condition is satisfied. In short, the output circuit 31z is
(1) Function for calculating deviation between peak value P1 and peak value P2 (2) Function for determining whether either peak value P1 or peak value P2 is near 0 (3) Deviation exceeds a threshold value, In addition, it is determined whether or not the conditions (4) and (3) satisfy the condition that either the peak value P1 or the peak value P2 satisfies the condition that either the peak value P1 or the peak value P2 is near 0. It has the function to do. Of course, these functions may be constituted by a plurality of circuit elements, respectively, or some circuit elements may be realized in an overlapping manner.

  Here, that either the peak value P1 or the peak value P2 is close to 0 means that the absolute value of the peak value P1 or the peak value P2 is within a predetermined allowable range ε set for 0. It does not necessarily mean that it is strictly 0.

  The reason why the output circuit 31z outputs the detection signal under a certain condition is that the detection signal is not erroneously output when the condition (3) is accidentally satisfied due to some noise. . That is, it can be said that the certain condition is a condition for determining that an open failure has occurred. In the present embodiment, for example, when a certain condition is a certain time and the time satisfying the condition (3) is maintained for a certain time, reliability is ensured by outputting a detection signal. The control device that has received the detection signal executes a predetermined abnormality process such as outputting an alarm or stopping the operation of the inverter.

  FIG. 3 shows a specific configuration example of the failure detection device 31. A first peak hold circuit 31a that holds the amplitude peak value P1 of the first half cycle of one cycle of the U-phase inverter output current, and a second peak hold circuit that holds the amplitude peak value P2 of the second half cycle of one cycle. 31b, a subtractor 31c that calculates a deviation ΔP between the amplitude peak value P1 of the first half cycle and the amplitude peak value P2 of the second half cycle, a comparator 31d that compares the deviation ΔP with a predetermined threshold value, and an amplitude peak of the first half cycle A first determination circuit 31e for determining whether the value or the amplitude peak value of the second half cycle is near zero, the amplitude peak value of the first half cycle or the amplitude peak value of the second half cycle is near zero, and the deviation ΔP is A counter 31f that counts a time exceeding a predetermined threshold, and a second determination circuit that outputs a failure detection signal when the count value of the counter 31f exceeds a predetermined threshold Including the 1g. Hereinafter, a case where an open failure of the switching transistor Q11 of the U-phase arm (switching transistor of the U-phase upper arm) is detected will be described.

  FIG. 4 shows a timing chart of each part of FIG. FIG. 4A shows the waveform of the U-phase inverter output current. When the switching transistors Q11 and Q12 are operating normally, the amplitude peak of the first half cycle of the output current is almost equal to the amplitude peak of the second half cycle. However, if an open failure occurs in the switching transistor Q11 at a certain timing, the amplitude of the first half cycle The peak is almost zero.

  FIG. 4B shows an output waveform of the first peak hold circuit 31a. The first peak hold circuit 31a holds and outputs the amplitude peak of the first half cycle of the inverter output current. The amplitude peak value is a constant value until an open failure of the switching transistor Q11 occurs, but when an open failure occurs, the peak hold value becomes almost zero after that timing.

  FIG. 4C shows the output waveform of the subtractor 31c. The subtractor 31c calculates a deviation ΔP between the output P1 of the first peak hold circuit 31a and the output P2 of the second peak hold circuit 31b. The comparator 31d compares the deviation ΔP with a threshold value, and outputs a signal to that effect when the deviation ΔP exceeds the threshold value. In FIG. 4C, the threshold level in the case of comparison by the comparator 31d is indicated by a one-dot chain line. The deviation ΔP rises from 0 and exceeds the threshold at the timing when the amplitude peak of the first half cycle is determined and the amplitude cycle of the second half cycle is determined, specifically, at the next cycle after the open transistor has occurred in the switching transistor Q11. It becomes like this.

  FIG. 4D shows the output waveform of the second determination circuit 31g. The counter 31f counts the time when the amplitude peak of the first half cycle is near 0 and the deviation ΔP exceeds the threshold value. This time functions as an abnormality determination time, and is for removing noise and improving the reliability of failure detection. And the 2nd determination circuit 31g outputs a detection signal, when the count time in the counter 31f is more than threshold time.

  In the configuration of FIG. 3, the difference ΔP between the amplitude peak value P1 of the first half cycle and the amplitude peak value P2 of the second half cycle of the inverter output current is always calculated by the subtractor 31c. The deviation ΔP may be calculated by the subtractor 31c only when it is determined that the amplitude peak value of the latter half period is near zero.

  FIG. 5 shows a processing flowchart of failure detection in the present embodiment. When the operation of the inverter 104 starts, the U-phase inverter output current is detected, and the amplitude peak value (MAX) of the first half cycle of the inverter output current is held (S101). Next, the amplitude peak value (MIN) of the latter half period of the inverter output current is held (S102).

  It is determined whether or not one cycle of the inverter output current has ended (S103), and it is determined whether or not the amplitude peak value of the first half cycle or the amplitude peak value of the second half cycle is close to 0 when one cycle ends. (S104). If it is determined that the amplitude peak value of the first half cycle or the amplitude peak value of the second half cycle is close to 0, a deviation ΔP between the amplitude peak value of the first half cycle and the amplitude peak value of the second half cycle is calculated (S105).

  After calculating the deviation ΔP, the deviation ΔP is compared with a predetermined threshold value to determine whether or not the threshold value is exceeded (S106). When the deviation ΔP exceeds the threshold value, the time counter is sequentially added (S107). When the value of the time counter (abnormal count value) is equal to or longer than a predetermined abnormality confirmation time (YES in S108), it is determined that an open failure has occurred and a detection signal is output.

  As described above, in this embodiment, the switching element failure is not detected based on the deviation (or difference) between the amplitude peak value of the first half cycle and the amplitude peak value of the second half cycle. Determine whether the peak value itself or the amplitude peak value of the second half cycle is close to 0, the amplitude peak value of the first half cycle or the amplitude peak value of the second half cycle is close to 0, and the deviation is a threshold value By determining whether or not there is a failure based on the weighting condition of whether or not it exceeds the threshold value, it is possible to mistake this even if a situation occurs in which the switching elements of the upper and lower arms of the inverter 104 are unbalanced, which may occur even under normal conditions. There is no detection.

  In the present embodiment, since an open failure of the switching element can be reliably detected, deterioration of the battery 100 due to power fluctuation due to a half-wave current, that is, secondary failure (failure of components other than the inverter 104) is suppressed in advance. be able to.

  In this embodiment, the case of detecting an open failure of the U-phase switching transistor is exemplified. Similarly, the V-phase inverter output current is detected to detect an open failure of the V-phase switching transistor, or W By detecting the phase inverter output current, it is possible to detect an open failure of the W phase switching transistor.

  Further, in the present embodiment, the configuration as shown in FIG. 3 is shown as a specific configuration of the failure detection device 31. However, the configuration in FIG. 3 is merely an example, and those skilled in the art can use the basic configuration shown in FIG. Various different configurations can be conceived under the configuration, and these configurations are all included in the technical idea of the present invention.

  31 failure detection device, 100 battery, 102 boost converter, 104 inverter, Q11 to Q16 switching transistor.

Claims (2)

A detection device for detecting a failure of a switching element of an inverter,
Means for detecting the amplitude peak value of the first half period of the output current from the switching element;
Means for detecting an amplitude peak value of a second half period following the first half period of the output current;
When the amplitude peak value of the first half cycle or the amplitude peak value of the second half cycle is near 0, and the deviation between the amplitude peak value of the first half cycle and the amplitude peak value of the second half cycle exceeds a threshold value, Means for outputting a failure detection signal of the switching element;
An inverter failure detection device characterized by comprising: The apparatus of claim 1.
The outputting means has an amplitude peak value in the first half cycle or an amplitude peak value in the second half cycle close to 0, and a deviation between the amplitude peak value in the first half cycle and the amplitude peak value in the second half cycle is a threshold. An inverter failure detection device that outputs a failure detection signal of the switching element when a time exceeding a value exceeds a threshold time.

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