CN113872176A - Double-bus positive line reverse filling prevention circuit based on field effect transistor - Google Patents
Double-bus positive line reverse filling prevention circuit based on field effect transistor Download PDFInfo
- Publication number
- CN113872176A CN113872176A CN202111195674.8A CN202111195674A CN113872176A CN 113872176 A CN113872176 A CN 113872176A CN 202111195674 A CN202111195674 A CN 202111195674A CN 113872176 A CN113872176 A CN 113872176A
- Authority
- CN
- China
- Prior art keywords
- bus
- resistor
- voltage
- field effect
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 171
- 230000002265 prevention Effects 0.000 title claims abstract description 14
- 238000005070 sampling Methods 0.000 claims abstract description 114
- 239000003990 capacitor Substances 0.000 claims description 41
- 230000000087 stabilizing effect Effects 0.000 claims description 17
- 238000004146 energy storage Methods 0.000 claims description 14
- 230000009977 dual effect Effects 0.000 claims 3
- 229920006395 saturated elastomer Polymers 0.000 description 10
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/10—Parallel operation of dc sources
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a field effect transistor-based double-bus positive line reverse filling prevention circuit. The first bus comparison control module controls the first field effect tube to be switched on through the first bus switch driving module when the first sampling voltage is greater than or equal to the output sampling voltage, and controls the first field effect tube to be switched off through the first bus switch driving module when the first sampling voltage is less than the output sampling voltage; the second bus comparison control module controls the second field effect tube to be switched on through the second bus switch driving module when the second sampling voltage is larger than or equal to the output sampling voltage, and controls the second field effect tube to be switched off through the second bus switch driving module when the second sampling voltage is smaller than the output sampling voltage. By implementing the invention, the power consumption can be reduced while three basic requirements of the existing common-ground double-bus power supply mode are met.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a field effect transistor-based double-bus positive line reverse filling prevention circuit.
Background
The existing common-ground double-bus power supply mode basically requires three points, wherein firstly, the high-voltage bus is mainly used for supplying power, and the low-voltage bus is not used for supplying power or is used for supplying less power; secondly, the high-voltage bus cannot reversely flow current to the low-voltage bus; and thirdly, when any one or two of the two buses is powered down, the energy storage capacitor of the system cannot reversely flow current to the buses. For the three point requirements, it is now conventional to use a diode in series with each of the positive lines of the two buses Vain and vbi, as shown in fig. 1.
The main problem of the scheme is that the forward conduction voltage drop Vfm of the power diodes Da and Db with high voltage and large current is often as high as 2V or even higher, and when the bus current reaches more than 10A-30A, the forward conduction power consumption of the power diodes is very large. Taking 30A as an example, the on power consumption is as high as 60W or more. For higher power applications, the bus current is higher, and the power diode conduction power consumption is higher.
Disclosure of Invention
The embodiment of the invention provides a field effect transistor-based double-bus positive line reverse filling prevention circuit, which can reduce the energy consumption of a common-ground double-bus power supply circuit.
An embodiment of the present invention provides a field effect transistor-based double-bus positive line reverse filling prevention circuit, including: the bus voltage sampling device comprises a first bus switch module, a first bus voltage sampling module, a first bus comparison control module, a first bus switch driving module, a second bus switch module, a second bus voltage sampling module, a second bus comparison control module, a second bus switch driving module, an output voltage sampling module and a power supply control module;
the first bus bar switch module comprises: the first field effect transistor, the first resistor and the first voltage stabilizing diode; the drain electrode of the first field effect transistor is connected with the voltage input end of the first positive bus, the source electrode of the first field effect transistor is connected with the voltage output end of the first positive bus, and the grid electrode of the first field effect transistor is connected with the first bus switch driving module; the first end of the first resistor is connected with the source electrode of the first field effect transistor, the second end of the first resistor is connected with the grid electrode of the first field effect transistor, the anode of the first voltage stabilizing diode is connected with the grid electrode of the first field effect transistor, and the cathode of the first voltage stabilizing diode is connected with the source electrode of the first field effect transistor;
the second bus bar switch module comprises: the second field effect transistor, the second resistor and the second voltage stabilizing diode; the drain electrode of the second field effect transistor is connected with the voltage input end of the second positive bus, the source electrode of the second field effect transistor is connected with the voltage output end of the second positive bus, and the grid electrode of the second field effect transistor is connected with the second bus switch driving module; the second end of the second resistor is connected with the source electrode of the second field effect transistor, the second end of the second resistor is connected with the grid electrode of the second field effect transistor, the anode of the second voltage stabilizing diode is connected with the grid electrode of the second field effect transistor, and the cathode of the second voltage stabilizing diode is connected with the source electrode of the second field effect transistor;
the voltage output end of the first positive bus and the voltage output end of the second positive bus are the same bus voltage output end; the on-resistance of the first field effect transistor is the same as that of the second field effect transistor;
the power supply control module is used for supplying power to the first bus comparison control module and the second bus comparison control module;
the first bus voltage sampling module is used for collecting the input voltage of the first positive bus to obtain a first sampling voltage; the second bus voltage sampling module is used for collecting the input voltage of the second positive bus to obtain a second sampling voltage; the output voltage sampling module is used for collecting output voltage and obtaining output sampling voltage;
the first bus comparison control module is configured to compare the first sampling voltage with the output sampling voltage, and then output a high-level signal to the first bus switch driving module when the first sampling voltage is greater than or equal to the output sampling voltage, so that the first bus switch driving module controls the first field-effect transistor to be turned on; when the first sampling voltage is smaller than the output sampling voltage, outputting a low-level signal to the first bus switch driving module so that the first bus switch driving module controls the first field effect transistor to be switched off;
the second bus comparison control module is configured to compare the second sampling voltage with the output sampling voltage, and then output a high-level signal to the second bus switch driving module when the second sampling voltage is greater than or equal to the output sampling voltage, so that the second bus switch driving module controls the second field-effect transistor to be turned on; and when the second sampling voltage is smaller than the output sampling voltage, outputting a low-level signal to the second bus switch driving module so that the second bus switch driving module controls the second field-effect tube to be cut off.
Further, the first bus comparison control module comprises: the circuit comprises a third resistor, a fourth resistor, a first comparator, a first capacitor, a second capacitor and a first diode;
the non-inverting input end of the first comparator is connected with the first bus voltage sampling module, the inverting input end of the first comparator is connected with the output voltage sampling module, the output end of the first comparator is connected with the first bus switch driving module, the power supply end of the first comparator is connected with the power supply control module, and the grounding end of the first comparator is grounded;
the negative electrode of the first diode is connected with the power supply end of the first comparator, and the positive electrode of the first diode is connected with the non-inverting input end of the first comparator;
the first end of the first capacitor is connected with a power supply end of a first comparator, and the second end of the first capacitor is grounded;
the first end of the third resistor is connected with a power supply end of a first comparator, and the second end of the third resistor is connected with an output end of the first comparator;
the first end of the fourth resistor is connected with the output end of the first comparator, and the second end of the fourth resistor is grounded;
and the first end of the second capacitor is connected with the inverting input end of the first comparator, and the second end of the second capacitor is connected with the output end of the first comparator.
Further, the first bus voltage sampling module includes: a fifth resistor and a sixth resistor;
a first end of the fifth resistor is connected with a voltage input end of the first positive bus, and a second end of the fifth resistor is connected with a non-inverting input end of the first comparator;
and the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is grounded.
Further, the first bus bar switch driving module includes: a seventh resistor and a first triode;
the first end of the seventh resistor is connected with the grid electrode of the first field effect transistor, and the second end of the seventh resistor is connected with the collector electrode of the first triode;
the base electrode of the first triode is connected with the output end of the first comparator, and the emitting electrode of the first triode is grounded.
Furthermore, an eighth resistor, a ninth resistor, a second comparator, a third capacitor and a second diode;
the non-inverting input end of the second comparator is connected with the second bus voltage sampling module, the inverting input end of the second comparator is connected with the output voltage sampling module, and the output end of the second comparator is connected with the second bus switch driving module;
the negative electrode of the second diode is connected with the power supply control module, and the positive electrode of the second diode is connected with the non-inverting input end of the second comparator;
the first end of the third capacitor is connected with the inverting input end of the second comparator, and the second end of the third capacitor is connected with the output end of the second comparator;
a first end of the eighth resistor is connected with a cathode of the second diode, and a second end of the eighth resistor is connected with an output end of the second comparator;
and the first end of the ninth resistor is connected with the output end of the second comparator, and the second end of the ninth resistor is grounded.
Further, the second bus voltage sampling module includes: a tenth resistor and an eleventh resistor;
a first end of the tenth resistor is connected with a voltage input end of the second positive bus, and a second end of the tenth resistor is connected with a non-inverting input end of the second comparator;
the first end of the eleventh resistor is connected with the second end of the tenth resistor, and the second end of the eleventh resistor is grounded.
Further, the second bus bar switch driving module includes: a twelfth resistor and a second triode;
a first end of the twelfth resistor is connected with the grid electrode of the second field effect transistor, and a second end of the twelfth resistor is connected with the collector electrode of the second triode;
and the base electrode of the second triode is connected with the output end of the second comparator, and the emitting electrode of the second triode is grounded.
Further, the output voltage sampling module includes: a thirteenth resistor, a fourteenth resistor, and a third diode;
a first end of the thirteenth resistor is connected with the bus voltage output end, and a second end of the thirteenth resistor is connected with the anode of the third diode;
a first end of the fourteenth resistor is connected with a second end of the thirteenth resistor, and a second end of the fourteenth resistor is grounded;
the negative pole of the third diode is connected with the power supply control module, and the positive pole of the third diode is also connected with the inverting input end of the first comparator and the inverting input end of the second comparator respectively.
Further, the power supply control module includes: a fifteenth resistor, a fourth diode, a third voltage stabilizing diode and an energy storage capacitor;
a first end of the fifteenth resistor is connected with the bus voltage output end, a second end of the fifteenth resistor is connected with an anode of the fourth diode, and a cathode of the fourth diode is connected with an anode of the energy storage capacitor;
the anode of the energy storage capacitor is also connected with the power supply end of the first comparator, the cathode of the second diode and the cathode of the third diode respectively, and the cathode of the energy storage capacitor is grounded;
the anode of the third zener diode is grounded, and the cathode of the third zener diode is connected to the second end of the fifteenth resistor.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a double-bus positive line reverse filling prevention circuit based on a field effect tube, wherein a first field effect tube and a second field effect tube are respectively connected in series on a first positive bus and a second positive bus, and the advantage of small on-resistance (up to tens of milliohms or even smaller) of the field effect tubes is utilized to greatly reduce the voltage drop of the large current of the buses flowing through the tubes, so that the power consumption of the large current generated on the tubes is greatly reduced. Taking 30A and 10m omega as an example, the conduction voltage drop is 0.3V, and the power consumption is only 9W. Even if the on-resistance of the tube is doubled to 20m omega at high temperature, the on-voltage drop is 0.6V, and the power consumption is only 18W, which is greatly lower than that of the conventional power diode. Meanwhile, the first bus comparison control module controls the first field effect tube to be switched on through the first bus switch driving module when the first sampling voltage is greater than or equal to the output sampling voltage, and controls the first field effect tube to be switched off through the first bus switch driving module when the first sampling voltage is less than the output sampling voltage; and the second bus comparison control module controls the second field effect transistor to be switched on through the second bus switch driving module when the second sampling voltage is greater than or equal to the output sampling voltage, and controls the second field effect transistor to be switched off through the second bus switch driving module when the second sampling voltage is less than the output sampling voltage, so that the technical scheme disclosed by the invention can meet three basic requirements of the conventional common-ground double-bus power supply mode.
Drawings
Fig. 1 is a schematic structural diagram of a double-bus positive line reverse filling prevention circuit in the prior art.
Fig. 2 is a schematic structural diagram of a double-bus positive line reverse-filling prevention circuit based on a field effect transistor according to an embodiment of the present invention.
Description of the drawings: the field-effect-transistor-based double-bus positive line reverse filling prevention circuit comprises a double-bus positive line reverse filling prevention circuit 1, a first bus switch module 11, a second bus switch module 12, a power supply control module 13, an output voltage sampling module 14, a second bus switch driving module 15, a second bus comparison control module 16, a first bus switch driving module 17, a first bus comparison control module 18, a second bus voltage sampling module 19 and a first bus voltage sampling module 20.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, an embodiment of the present invention provides a field effect transistor-based dual-bus positive line reverse-filling prevention circuit 1, which includes: the bus voltage sampling device comprises a first bus switch module 11, a first bus voltage sampling module 20, a first bus comparison control module 18, a first bus switch driving module 17, a second bus switch module 12, a second bus voltage sampling module 19, a second bus comparison control module 16, a second bus switch driving module 15, an output voltage sampling module 14 and a power supply control module 13;
the first bus bar switch module 11 includes: a first field effect transistor PMa, a first resistor R1 and a first zener diode Za; the drain electrode of the first field effect transistor PMa is connected with the voltage input end of the first positive bus, the source electrode of the first field effect transistor PMa is connected with the voltage output end of the first positive bus, and the grid electrode of the first field effect transistor PMa is connected with the first bus switch driving module 17; a first end of the first resistor R1 is connected to the source of the first field-effect transistor PMa, a second end of the first resistor R1 is connected to the gate of the first field-effect transistor PMa, an anode of the first zener diode Za is connected to the gate of the first field-effect transistor PMa, and a cathode of the first zener diode Za is connected to the source of the first field-effect transistor PMa;
the second bus bar switch module 12 includes: a second field effect transistor PMb, a second resistor R2, and a second zener diode Zb; the drain electrode of the second field effect transistor PMb is connected with the voltage input end of the second positive bus, the source electrode of the second field effect transistor is connected with the voltage output end of the second positive bus, and the grid electrode of the second field effect transistor PMb is connected with the second bus switch driving module 15; a second end of the second resistor R2 is connected to a source of the second field-effect transistor PMb, a second end of the second resistor R2 is connected to a gate of the second field-effect transistor PMb, an anode of the second zener diode Zb is connected to the gate of the second field-effect transistor PMb, and a cathode of the second zener diode Zb is connected to the source of the second field-effect transistor PMb;
the voltage output end of the first positive bus and the voltage output end of the second positive bus are the same bus voltage output end; the on-resistance of the first field effect transistor PMa is the same as that of the second field effect transistor PMb.
The power supply control module 13 is configured to supply power to the first bus comparison control module 18 and the second bus comparison control module 16;
the first bus voltage sampling module 20 is configured to collect an input voltage of the first positive bus to obtain a first sampling voltage; the second bus voltage sampling module 19 is configured to collect the second positive bus input voltage to obtain a second sampling voltage; the output voltage sampling module 14 is configured to collect an output voltage and obtain an output sampling voltage;
the first bus comparison control module 18 is configured to compare the first sampling voltage with the output sampling voltage, and then output a high-level signal to the first bus switch driving module 17 when the first sampling voltage is greater than or equal to the output sampling voltage, so that the first bus switch driving module 17 controls the first field effect transistor PMa to be turned on; when the first sampling voltage is smaller than the output sampling voltage, outputting a low-level signal to the first bus switch driving module 17, so that the first bus switch driving module 17 controls the first field-effect transistor PMa to be turned off;
the second bus comparison control module 16 is configured to compare the second sampling voltage with the output sampling voltage, and then output a high-level signal to the second bus switch driving module 15 when the second sampling voltage is greater than or equal to the output sampling voltage, so that the second bus switch driving module 15 controls the second field-effect transistor PMb to be turned on; and when the second sampling voltage is smaller than the output sampling voltage, outputting a low-level signal to the second bus switch driving module 15, so that the second bus switch driving module 15 controls the second field-effect transistor PMb to be turned off.
In a preferred embodiment, the first bus comparison control module 18 comprises: a third resistor R3, a fourth resistor R4, a first comparator U1A, a first capacitor C1, a second capacitor C2 and a first diode D1;
the non-inverting input terminal of the first comparator U1A is connected to the first bus voltage sampling module 20 (as shown, connected to a point a of the first bus voltage sampling module 20), the inverting input terminal of the first comparator U1A is connected to the output voltage sampling module 14 (as shown, connected to Vo of the output voltage sampling module 14), the output terminal of the first comparator U1A is connected to the first bus switch driving module 17, the power supply terminal of the first comparator U1A is connected to the power supply control module 13, and the ground terminal of the first comparator U1A is grounded;
the cathode of the first diode D1 is connected with the power supply terminal of the first comparator U1A, and the anode of the first diode D1 is connected with the non-inverting input terminal of the first comparator U1A;
a first end of the first capacitor C1 is connected with a power supply end of a first comparator U1A, and a second end of the first capacitor C1 is grounded;
a first end of the third resistor R3 is connected with a power supply end of a first comparator U1A, and a second end of the third resistor R3 is connected with an output end of the first comparator U1A;
a first end of the fourth resistor R4 is connected with the output end of the first comparator U1A, and a second end of the fourth resistor R4 is grounded;
the first end of the second capacitor C2 is connected to the inverting input of the first comparator U1A, and the second end of the second capacitor C2 is connected to the output of the first comparator U1A.
In a preferred embodiment, the first bus voltage sampling module 20 includes: a fifth resistor R5 and a sixth resistor R6;
a first end of the fifth resistor R5 is connected with the voltage input end of the first positive bus, and a second end of the fifth resistor R5 is connected with the non-inverting input end of the first comparator U1A;
the first end of the sixth resistor R6 is connected with the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is grounded.
In a preferred embodiment, the first bus bar switch driving module 17 includes: a seventh resistor R7 and a first triode Na;
a first end of the seventh resistor R7 is connected to the gate of the first field effect transistor PMa, and a second end of the seventh resistor R7 is connected to the collector of the first transistor Na;
the base electrode of the first triode Na is connected with the output end of the first comparator U1A, and the emitting electrode of the first triode Na is grounded.
In a preferred embodiment, the second bus comparison control module 16 includes: an eighth resistor R8, a ninth resistor R9, a second comparator U1B, a third capacitor C3 and a second diode D2;
the non-inverting input terminal of the second comparator U1B is connected to the second bus voltage sampling module 19 (as shown, at point b of the second bus voltage sampling module 19), the inverting input terminal of the second comparator U1B is connected to the output voltage sampling module 14 (as shown, at Vo of the output voltage sampling module 14), and the output terminal of the second comparator U1B is connected to the second bus switch driving module 15;
the cathode of the second diode D2 is connected to the power supply control module 13, and the anode of the second diode D2 is connected to the non-inverting input terminal of the second comparator U1B;
a first end of the third capacitor C3 is connected with an inverting input terminal of the second comparator U1B, and a second end of the third capacitor C3 is connected with an output terminal of the second comparator U1B;
a first end of the eighth resistor R8 is connected with the cathode of the second diode D2, and a second end of the eighth resistor R8 is connected with the output end of the second comparator U1B;
a first end of the ninth resistor R9 is connected to the output end of the second comparator U1B, and a second end of the ninth resistor R9 is grounded.
In a preferred embodiment, the second bus voltage sampling module 19 comprises: a tenth resistor R10 and an eleventh resistor R11;
a first end of the tenth resistor R10 is connected to the voltage input end of the second positive bus, and a second end of the tenth resistor R10 is connected to the non-inverting input end of the second comparator U1B;
a first end of the eleventh resistor R11 is connected to a second end of the tenth resistor R10, and a second end of the eleventh resistor R11 is grounded.
In a preferred embodiment, the second bus bar switch driving module includes: a twelfth resistor R12 and a second transistor Nb;
a first end of the twelfth resistor R12 is connected to the gate of the second field effect transistor PMb, and a second end of the twelfth resistor R12 is connected to the collector of the second transistor Nb;
the base of the second triode Nb is connected to the output terminal of the second comparator U1B, and the emitter of the second triode Nb is grounded.
In a preferred embodiment, the output voltage sampling module 14 includes: a thirteenth resistor R13, a fourteenth resistor R14, and a third diode D3;
a first end of the thirteenth resistor R13 is connected to the bus voltage output terminal, and a second end of the thirteenth resistor R13 is connected to the anode of the third diode D3;
a first end of the fourteenth resistor R14 is connected to a second end of the thirteenth resistor R13, and a second end of the fourteenth resistor R14 is grounded;
the cathode of the third diode D3 is connected to the power supply control module 13, and the anode of the third diode D3 is also connected to the inverting input terminal of the first comparator U1A and the inverting input terminal of the second comparator U1B, respectively.
In a preferred embodiment, the power supply control module comprises: a fifteenth resistor R15, a fourth diode D4, a third zener diode Zc and an energy storage capacitor C4;
a first end of the fifteenth resistor R15 is connected to the bus voltage output end, a second end of the fifteenth resistor R15 is connected to the anode of the fourth diode D4, and the cathode of the fourth diode D4 is connected to the anode of the energy storage capacitor C4;
the anode of the energy storage capacitor C4 is further connected to the power supply terminal of the first comparator U1A, the cathode of the second diode D2 and the cathode of the third diode D3, respectively, and the cathode of the energy storage capacitor C4 is grounded;
the anode of the third zener diode Zc is grounded, and the cathode of the third zener diode Zc is connected to the second end of the fifteenth resistor R15.
The field-effect-transistor-based double-bus positive line reverse filling prevention circuit 1 has the following specific working principle: assuming that the input voltage of the first positive bus is Vain (collected by the first bus voltage sampling module 20), the input voltage of the second positive bus is Vbin (collected by the second bus voltage sampling module 19), the output sampling voltage of the bus voltage output end shared by the two buses is Vout (collected by the output voltage sampling module 14), and the output voltage of the power supply control module 13 is Vcc;
when initially powering on, if Vain is equal to Vbin; in the process that Vain is rising from 0V, Vcc also rises gradually from 0V, the first comparator U1A and the second comparator U1B are from non-operation to operation, the initial internal OC output of each comparator unit is off to ground, and the outputs of both comparator units are high. Although the "high" level output by the comparator when the Vout and Vcc voltages are too low does not drive the first transistor and the second transistor to make the first fet PMa and the second fet PMb conductive, body diode conduction of the first fet PMa and the second fet PMb will generate Vout. As long as Vain-vbi rises and is greater than the forward turn-on voltage of the first field effect transistor PMa and the second field effect transistor PMb, the first field effect transistor PMa and the second field effect transistor PMb can be driven to conduct. After the first field effect transistor PMa and the second field effect transistor PMb are conducted, the conduction of the body diode is replaced. Due to the voltage drop of the first field effect transistor PMa and the second field effect transistor PMb, Vout is smaller than Vain and vbi, so after power-up, the OC output inside the first comparator U1A and the second comparator U1B is continuously in an off state with respect to ground, that is, the first bus comparison control module 18 and the second bus comparison control module 16 continuously output a high level. The first bus comparison control module 18 outputs a high level, drives the first triode Na to be saturated and conducted by Vcc through a seventh resistor R7 to provide a base current, a parallel network of a first resistor R1 and a first voltage stabilizing diode Za in the first bus switch module 11 and a seventh resistor R7 in the first bus switch driving module 17 carry out series voltage division on Vout, so that a voltage Vgs1 of a gate relative to a source in the first field effect transistor PMa is- Δ Vr1 is less than or equal to- Δ Vza, Δ Vr1 is a voltage across a first resistor R1, Δ Vza is a voltage across a first voltage stabilizing diode Za, and the first field effect transistor PMa is saturated and conducted; similarly, the second bus comparison control module 16 outputs a high level to drive the second triode Nb to be saturated and switched on by Vcc through the eighth resistor R8 to provide a base current, the second resistor R2 and the second zener diode Zb parallel network in the second bus switch module 12 and the twelfth resistor R12 in the second bus switch driving module 15 perform serial voltage division on Vout, so that the voltage Vgs2 of the gate relative to the source in the second field effect transistor PMb is- Δ Vr2 ≦ Δ Vzb, Δ Vr2 is the voltage across the second resistor R2, Δ Vzb is the voltage across the second zener diode Zb, and the second field effect transistor PMb is saturated and switched on.
Therefore, if Vain is equal to Vbin during initial power-on, the first positive bus and the second positive bus in the field-effect-tube-based double-bus positive line reverse-filling circuit provided by the invention can supply power at the same time, no matter whether the individual parameters of the two field-effect tubes are different or not; however, if the scheme of the prior art shown in fig. 1 is adopted, if Vain is equal to vbi at the time of initial power-on, then the two diodes may be simultaneously turned on, or due to a significant difference in conduction voltage drop between the individuals, conduction with a small conduction voltage drop is caused, and non-conduction with a large conduction voltage drop is caused, that is, the first positive bus may supply power, and the second positive bus may supply power. The operating state determination of the present invention is relatively more reliable under the condition of Vain-vbi at initial power-on.
During initial power-on, if Vain > vbi, Vout is generated by Vain, and due to the voltage drop of the first fet PMa, Vout is smaller than Vain, the first bus comparison control module 18 continues to output a high level after power-on. The first bus comparison control module 18 outputs high level to drive the first triode Na to be saturated and conducted by Vcc through a seventh resistor R7 to provide base current, the parallel network of the first resistor R1 and the first zener diode Za in the first bus switch module 11 and the seventh resistor R7 in the first bus switch driving module 17 divide Vout in series, the voltage Vgs1 of the gate relative to the source in the first field effect transistor PMa is equal to or less than-delta Vr1 and equal to or less than-delta Vza, delta Vr1 is the voltage at two ends of the first resistor R1, delta Vza is the voltage at two ends of the first voltage stabilizing diode Za, the first field effect transistor PMa is in saturated conduction, after the first field effect transistor PMa is powered on, the first field effect transistor PMa is continuously conducted to supply power, and at the moment, the current which flows through the first field effect transistor PMa in the forward direction (namely, the current which flows from the drain electrode to the source electrode of the first field effect transistor PMa) is equal to the difference of the drain-source voltage of the first field effect transistor PMa divided by the saturated on-resistance of the first field effect transistor PMa; for the second fet PMb, there are two cases, when vbi is greater than or equal to Vout, the second bus comparison control module 16 continuously outputs high level to drive the second triode Nb to provide base current through the eighth resistor R8 by Vcc to conduct in saturation, the parallel network of the second resistor R2 and the second zener diode Zb in the second bus switch module 12 and the twelfth resistor R12 in the second bus switch driving module 15 divide voltage in series for Vout, so that Vgs2 of the gate of the second fet PMb relative to the source is- Δ Vr2 or less- Δ Vzb, Δ Vr2 is the voltage across the second resistor R2, Δ Vzb is the voltage across the second zener diode Zb, the second fet PMb is conducted in saturation, that is, after power-up, the second fet PMb is continuously conducted, the second positive voltage also supplies power, but current flowing through the second fet in forward direction (i.e., current flowing from the drain of the second fet to the source) is equal to the drain of the second fet PMb Dividing the difference by the saturated on-resistance of the second field effect transistor PMb; since the first field effect transistor PMa and the second field effect transistor PMb are the same in type, and therefore the saturation on-resistances of the two field effect transistors are the same, the current flowing from the drain to the source of the first field effect transistor PMa is larger than the current flowing from the drain to the source of the second field effect transistor PMb, so that the first positive bus mainly supplies power, and the second positive bus supplies less power. In the second mode, when Vbin is less than Vout, the second bus comparison control module 16 outputs a low level to control the second field effect transistor PMb to be cut off, the first positive bus continuously supplies power, and the second positive bus does not supply power. That is, during initial power-on, if Vain > vbi, the system is powered by the first positive bus and the second positive bus is powered less or no.
In practical use, Vout is smaller than Vain but is very close to Vain, and Vain and Vbin are often greatly different from each other, so that even though there is a certain difference in on-resistance values between the two field effect transistors, it is ensured that the current flowing from the drain to the source of the first field effect transistor PMa is larger than the current flowing from the drain to the source of the second field effect transistor PMb.
During initial power-on, if Vain is less than vbi, Vout is generated by vbi, and due to the existence of voltage drop of the second field effect transistor PMb, Vout is less than vbi, the second bus comparison control module 16 continuously outputs a high level to control the second field effect transistor PMb to be continuously turned on (the specific conduction principle is the same as the above, and is not described herein again), and supplies power to the bus voltage output end, and the current flowing through the second field effect transistor PMb in the forward direction at this time is equal to the drain-source voltage difference of the second field effect transistor PMb divided by the saturated conduction resistance of the second field effect transistor PMb; for the first field effect transistor PMa, there are two situations, the first is when Vain is greater than or equal to Vout, the first bus comparison control module 18 continuously outputs a high level to control the first field effect transistor PMa to be continuously conducted, but at this time, the current flowing through the first field effect transistor PMa in the forward direction is equal to the drain-source voltage difference of the first field effect transistor PMa divided by the saturation on-resistance of the first field effect transistor PMa; because the first field effect transistor PMa and the second field effect transistor PMb are the same in type and the saturation on-resistance of the two field effect transistors is the same, the current flowing from the drain electrode to the source electrode of the second field effect transistor PMb is larger than the current flowing from the drain electrode to the source electrode of the first field effect transistor PMa, the second positive bus mainly supplies power, and the first positive bus supplies less power. In the second mode, when Vain is less than Vout, the first bus comparison control module 18 outputs a low level to control the first field effect transistor PMa to be turned off, power is supplied by the second positive bus, and power is not supplied by the first positive bus. That is, during initial power-on, if Vain < vbi, the system is powered by the second positive bus, and the first positive bus is powered less or not.
In addition, in the steady-state operation of the circuit, the on or off of the first field-effect transistor PMa and the second field-effect transistor PMb is completely controlled by the control logic with the two comparators as cores, and for a certain load current, the specific operating principle and the operating process of the on or off of the first field-effect transistor PMa and the second field-effect transistor PMb are as follows:
1. vout < Vain is equal to Vbin, a first field effect transistor PMa is in saturation conduction and a large current flows, a second field effect transistor PMb is in saturation conduction and a large current flows, and the first positive bus and the second positive bus supply power simultaneously.
2. Vout is more than Vain and less than Vbin, the first field effect transistor PMa is in saturation conduction and flows through small current, the second field effect transistor PMb is in saturation conduction and flows through large current, the second positive bus mainly supplies power, and the first positive bus supplies less power.
3. Vout is more than Vbin and less than Vain, the first field effect transistor PMa is in saturation conduction and flows through large current, the second field effect transistor PMb is in saturation conduction and flows through small current, power is mainly supplied by the first positive bus, and less power is supplied by the second positive bus.
4. Vout > Vain ═ vbi, the first field effect transistor PMa and the second field effect transistor PMb are cut off, and neither the first positive bus nor the second positive bus supplies power.
5. Vout is more than Vain is more than Vbin, the first field effect transistor PMa and the second field effect transistor PMb are cut off, and the first positive bus and the second positive bus do not supply power.
6. Vout is more than Vbin is more than Vain, the first field effect transistor PMa and the second field effect transistor PMb are cut off, and the first positive bus and the second positive bus do not supply power.
7. Vout-Vain-vbi, the first fet PMa and the second fet PMb are both conductive but no current flows through them, and neither the first positive bus nor the second positive bus is powered.
8. Vout is Vain < Vbin, the first field effect transistor PMa is conducted but no current flows, the second field effect transistor PMb is conducted in a saturated mode and large current flows, the first positive bus is not powered, and the second positive bus is powered.
9. And Vout is Vbin < Vain, the first field effect transistor PMa is in saturation conduction and flows large current, the second field effect transistor PMb is in conduction but does not flow current, the first positive bus supplies power, and the second positive bus does not supply power.
10. And Vout is Vain and Vbin, the first field effect transistor PMa is switched on but no current flows, the second field effect transistor PMb is switched off, and the first positive bus and the second positive bus do not supply power.
11. And Vout is Vbin > Vain, the first field effect transistor PMa is cut off, the second field effect transistor PMb is switched on but no current flows, and the first positive bus and the second positive bus do not supply power.
12. Vbin is less than Vout and less than Vain, the first field effect transistor PMa is in saturation conduction and flows through large current, the second field effect transistor PMb is cut off, the first positive bus supplies power, and the second positive bus does not supply power.
13. Vain is more than Vout and less than Vbin, the first field effect transistor PMa is cut off, the second field effect transistor PMb is in saturation conduction and flows through large current, the first positive bus is not powered, and the second positive bus is powered.
According to the principle, the technical scheme disclosed by the invention can meet the requirements that the existing common-ground double-bus power supply mode is mainly supplied by a high-voltage bus, the low-voltage bus does not supply power or supplies less power, and the problems that the high-voltage bus reversely flows current to the low-voltage bus and the energy storage capacitor reversely flows current to the bus do not occur. In addition, in the circuit, the first field effect tube and the second field effect tube are respectively connected in series on the first positive bus and the second positive bus, and the advantage that the on-resistance of the field effect tube is small (up to tens of milliohms or even smaller) is utilized, so that the voltage drop of the bus high current flowing through the tube is greatly reduced, and the power consumption of the high current generated on the tube is greatly reduced. Taking 30A and 10m omega as an example, the conduction voltage drop is 0.3V, and the power consumption is only 9W. Even if the on-resistance of the tube is doubled to 20m omega at high temperature, the on-voltage drop is 0.6V, and the power consumption is only 18W, which is greatly lower than that of the conventional power diode. Therefore, the technical scheme disclosed by the invention can meet three-point basic requirements of a common-ground double-bus power supply mode while reducing power consumption.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (9)
1. A field effect transistor-based double-bus positive line reverse filling prevention circuit is characterized by comprising: the bus voltage sampling device comprises a first bus switch module, a first bus voltage sampling module, a first bus comparison control module, a first bus switch driving module, a second bus switch module, a second bus voltage sampling module, a second bus comparison control module, a second bus switch driving module, an output voltage sampling module and a power supply control module;
the first bus bar switch module comprises: the first field effect transistor, the first resistor and the first voltage stabilizing diode; the drain electrode of the first field effect transistor is connected with the voltage input end of a first positive bus, the source electrode of the first field effect transistor is connected with the voltage output end of the first positive bus, and the grid electrode of the first field effect transistor is connected with the first bus switch driving module; the first end of the first resistor is connected with the source electrode of the first field effect transistor, the second end of the first resistor is connected with the grid electrode of the first field effect transistor, the anode of the first voltage stabilizing diode is connected with the grid electrode of the first field effect transistor, and the cathode of the first voltage stabilizing diode is connected with the source electrode of the first field effect transistor;
the second bus bar switch module comprises: the second field effect transistor, the second resistor and the second voltage stabilizing diode; the drain electrode of the second field effect tube is connected with the voltage input end of a second positive bus, the source electrode of the second field effect tube is connected with the voltage output end of the second positive bus, and the grid electrode of the second field effect tube is connected with the second bus switch driving module; the first end of the second resistor is connected with the source electrode of the second field effect transistor, the second end of the second resistor is connected with the grid electrode of the second field effect transistor, the anode of the second voltage stabilizing diode is connected with the grid electrode of the second field effect transistor, and the cathode of the second voltage stabilizing diode is connected with the source electrode of the second field effect transistor;
the voltage output end of the first positive bus and the voltage output end of the second positive bus are the same bus voltage output end; the on-resistance of the first field effect transistor is the same as that of the second field effect transistor;
the power supply control module is used for supplying power to the first bus comparison control module and the second bus comparison control module;
the first bus voltage sampling module is used for collecting the input voltage of the first positive bus to obtain a first sampling voltage; the second bus voltage sampling module is used for collecting the input voltage of the second positive bus to obtain a second sampling voltage; the output voltage sampling module is used for collecting output voltage and obtaining output sampling voltage;
the first bus comparison control module is configured to compare the first sampling voltage with the output sampling voltage, and then output a high-level signal to the first bus switch driving module when the first sampling voltage is greater than or equal to the output sampling voltage, so that the first bus switch driving module controls the first field-effect transistor to be turned on; when the first sampling voltage is smaller than the output sampling voltage, outputting a low-level signal to the first bus switch driving module so that the first bus switch driving module controls the first field effect transistor to be switched off;
the second bus comparison control module is configured to compare the second sampling voltage with the output sampling voltage, and then output a high-level signal to the second bus switch driving module when the second sampling voltage is greater than or equal to the output sampling voltage, so that the second bus switch driving module controls the second field-effect transistor to be turned on; and when the second sampling voltage is smaller than the output sampling voltage, outputting a low-level signal to the second bus switch driving module so that the second bus switch driving module controls the second field-effect tube to be cut off.
2. The fet-based dual bus positive line anti-reverse flow circuit of claim 1, wherein the first bus comparison control module comprises: the circuit comprises a third resistor, a fourth resistor, a first comparator, a first capacitor, a second capacitor and a first diode;
the non-inverting input end of the first comparator is connected with the first bus voltage sampling module, the inverting input end of the first comparator is connected with the output voltage sampling module, the output end of the first comparator is connected with the first bus switch driving module, the power supply end of the first comparator is connected with the power supply control module, and the grounding end of the first comparator is grounded;
the negative electrode of the first diode is connected with the power supply end of the first comparator, and the positive electrode of the first diode is connected with the non-inverting input end of the first comparator;
the first end of the first capacitor is connected with a power supply end of a first comparator, and the second end of the first capacitor is grounded;
the first end of the third resistor is connected with a power supply end of a first comparator, and the second end of the third resistor is connected with an output end of the first comparator;
the first end of the fourth resistor is connected with the output end of the first comparator, and the second end of the fourth resistor is grounded;
and the first end of the second capacitor is connected with the inverting input end of the first comparator, and the second end of the second capacitor is connected with the output end of the first comparator.
3. The fet-based dual bus positive line anti-reverse flow circuit of claim 2, wherein the first bus voltage sampling module comprises: a fifth resistor and a sixth resistor;
a first end of the fifth resistor is connected with a voltage input end of the first positive bus, and a second end of the fifth resistor is connected with a non-inverting input end of the first comparator;
and the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is grounded.
4. The fet-based dual-bus positive line anti-reverse flow circuit of claim 3, wherein the first bus switch driver module comprises: a seventh resistor and a first triode;
the first end of the seventh resistor is connected with the grid electrode of the first field effect transistor, and the second end of the seventh resistor is connected with the collector electrode of the first triode;
the base electrode of the first triode is connected with the output end of the first comparator, and the emitting electrode of the first triode is grounded.
5. The fet-based dual-bus positive line anti-reverse flow circuit of claim 4, wherein the second bus comparison control module comprises: the circuit comprises an eighth resistor, a ninth resistor, a second comparator, a third capacitor and a second diode;
the non-inverting input end of the second comparator is connected with the second bus voltage sampling module, the inverting input end of the second comparator is connected with the output voltage sampling module, and the output end of the second comparator is connected with the second bus switch driving module;
the negative electrode of the second diode is connected with the power supply control module, and the positive electrode of the second diode is connected with the non-inverting input end of the second comparator;
the first end of the third capacitor is connected with the inverting input end of the second comparator, and the second end of the third capacitor is connected with the output end of the second comparator;
a first end of the eighth resistor is connected with a cathode of the second diode, and a second end of the eighth resistor is connected with an output end of the second comparator;
and the first end of the ninth resistor is connected with the output end of the second comparator, and the second end of the ninth resistor is grounded.
6. The fet-based dual bus positive line anti-reverse flow circuit of claim 5, wherein the second bus voltage sampling module comprises: a tenth resistor and an eleventh resistor;
a first end of the tenth resistor is connected with a voltage input end of the second positive bus, and a second end of the tenth resistor is connected with a non-inverting input end of the second comparator;
the first end of the eleventh resistor is connected with the second end of the tenth resistor, and the second end of the eleventh resistor is grounded.
7. The fet-based dual-bus positive line anti-reverse flow circuit of claim 6, wherein the second bus switch driver module comprises: a twelfth resistor and a second triode;
a first end of the twelfth resistor is connected with the grid electrode of the second field effect transistor, and a second end of the twelfth resistor is connected with the collector electrode of the second triode;
and the base electrode of the second triode is connected with the output end of the second comparator, and the emitting electrode of the second triode is grounded.
8. The fet-based dual-bus positive line anti-reverse flow circuit of claim 7, wherein the output voltage sampling module comprises: a thirteenth resistor, a fourteenth resistor, and a third diode;
a first end of the thirteenth resistor is connected with the bus voltage output end, and a second end of the thirteenth resistor is connected with the anode of the third diode;
a first end of the fourteenth resistor is connected with a second end of the thirteenth resistor, and a second end of the fourteenth resistor is grounded;
the negative pole of the third diode is connected with the power supply control module, and the positive pole of the third diode is also connected with the inverting input end of the first comparator and the inverting input end of the second comparator respectively.
9. The fet-based dual-bus positive line anti-reverse flow circuit of claim 8, wherein the power supply control module comprises: a fifteenth resistor, a fourth diode, a third voltage stabilizing diode and an energy storage capacitor;
a first end of the fifteenth resistor is connected with the bus voltage output end, a second end of the fifteenth resistor is connected with an anode of the fourth diode, and a cathode of the fourth diode is connected with an anode of the energy storage capacitor;
the anode of the energy storage capacitor is also connected with the power supply end of the first comparator, the cathode of the second diode and the cathode of the third diode respectively, and the cathode of the energy storage capacitor is grounded;
the anode of the third zener diode is grounded, and the cathode of the third zener diode is connected to the second end of the fifteenth resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111195674.8A CN113872176A (en) | 2021-10-14 | 2021-10-14 | Double-bus positive line reverse filling prevention circuit based on field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111195674.8A CN113872176A (en) | 2021-10-14 | 2021-10-14 | Double-bus positive line reverse filling prevention circuit based on field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113872176A true CN113872176A (en) | 2021-12-31 |
Family
ID=78999540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111195674.8A Pending CN113872176A (en) | 2021-10-14 | 2021-10-14 | Double-bus positive line reverse filling prevention circuit based on field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113872176A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023231318A1 (en) * | 2022-06-01 | 2023-12-07 | 北京京东乾石科技有限公司 | Voltage holding device for unmanned vehicle and unmanned vehicle |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4812672A (en) * | 1987-10-01 | 1989-03-14 | Northern Telecom Limited | Selective connection of power supplies |
| US6522190B1 (en) * | 2001-10-31 | 2003-02-18 | International Business Machines Corporation | High efficiency multiple input voltage sources power supply |
| US20040095021A1 (en) * | 2002-11-15 | 2004-05-20 | Inostor Corporation | Power distributor |
| CN210985660U (en) * | 2019-10-24 | 2020-07-10 | 深圳市道通智能航空技术有限公司 | Anti-reverse-filling circuit |
-
2021
- 2021-10-14 CN CN202111195674.8A patent/CN113872176A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4812672A (en) * | 1987-10-01 | 1989-03-14 | Northern Telecom Limited | Selective connection of power supplies |
| US6522190B1 (en) * | 2001-10-31 | 2003-02-18 | International Business Machines Corporation | High efficiency multiple input voltage sources power supply |
| US20040095021A1 (en) * | 2002-11-15 | 2004-05-20 | Inostor Corporation | Power distributor |
| CN210985660U (en) * | 2019-10-24 | 2020-07-10 | 深圳市道通智能航空技术有限公司 | Anti-reverse-filling circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023231318A1 (en) * | 2022-06-01 | 2023-12-07 | 北京京东乾石科技有限公司 | Voltage holding device for unmanned vehicle and unmanned vehicle |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106712207B (en) | Reverse connection-preventing and reverse-flowing-preventing battery charging protection circuit | |
| CN111432528B (en) | LED driving power supply and controller thereof | |
| CN107209524B (en) | Linear power supply and the electronic device for using it | |
| CN107947539B (en) | Switching power supply driving power supply circuit and switching power supply | |
| CN102033560A (en) | Voltage regulator | |
| CN111969577A (en) | Low-power-consumption reverse connection protection circuit for vehicle and control method thereof | |
| CN211557239U (en) | Low-loss backflow-preventing high-end load switch circuit | |
| CN113872176A (en) | Double-bus positive line reverse filling prevention circuit based on field effect transistor | |
| CN201663546U (en) | Multi-power-supply power-up sequence control device and system | |
| CN214850479U (en) | Reverse connection prevention and overvoltage prevention protection circuit and edge computing equipment | |
| CN113872177B (en) | Anti-reverse-filling circuit based on field effect transistor | |
| CN211508901U (en) | Power supply circuit and power supply device | |
| CN216904653U (en) | Drive circuit, chip and electronic equipment | |
| CN114244082B (en) | Driving circuit, chip and electronic equipment | |
| CN113885644B (en) | Substrate switching circuit for preventing LDO backflow | |
| CN203218904U (en) | Control circuit reducing static power consumption of power battery management system | |
| CN114257071A (en) | Power supply preprocessing circuit | |
| CN211063335U (en) | High-power surge voltage suppression module based on three NMOS tubes are parallelly connected | |
| CN218919981U (en) | Low-resistance nonpolar direct current access circuit | |
| CN109980766B (en) | Vibration energy collector power management circuit with hysteresis self-locking function | |
| CN114162213B (en) | Power steering system | |
| CN112202155A (en) | Input voltage surge suppression circuit | |
| CN211405456U (en) | Prevent drive circuit of motor stalling | |
| CN214255817U (en) | Dormancy action circuit | |
| CN217656419U (en) | Surge suppression circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211231 |