CN113867650A - IO command processing method and solid-state storage device - Google Patents
IO command processing method and solid-state storage device Download PDFInfo
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The application provides an IO command processing method and solid-state storage equipment. The disclosed method comprises: obtaining LUN number and/or block address from IO command; the LUN number is used to indicate a virtual LUN or a logical LUN, where the virtual LUN includes multiple physical LUNs, and the logical LUN includes one or more physical LUNs from different virtual LUNs or multiple physical blocks provided by one or more physical LUNs from different virtual LUNs; selecting one or more processing units from the plurality of processing units according to the LUN number; each processing unit determines a physical LUN accessed by the IO command and a physical block address on the physical LUN according to the block address; sending an effective chip enabling signal to a CE port of a physical LUN accessed by the IO command; and issuing NVM interface commands to the accessed physical LUNs, wherein each processing unit executes multiple IO commands in parallel; or multiple processing units execute one or more IO commands in parallel.
Description
Technical Field
The present application relates to the field of storage technologies, and in particular, to an IO command processing method and a solid-state storage device.
Background
NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM (Non-Volatile Memory).
The memory Target (Target) is one or more Logic units (Logic units) of a shared Chip Enable (CE) signal within the flash memory granule package, each Logic Unit having a Logic Unit Number (LUN). One or more DIEs (DIEs) may be included within the NAND flash memory package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other. In "Open NAND Flash Interface Specification (Revision 3.2)" obtained by http:// www.onfi.org// media/ONFI/specs/ONFI-3-2% 20gold. pdf, the meaning for target (target), logical unit, LUN, Plane (Plane) is provided, and the commands to operate the NVM chip are also provided.
The solid state hard disk controller includes a flash memory interface controller (or referred to as a media interface controller, a flash memory channel controller) coupled to the NVM chip and configured to issue commands to the NVM chip in a manner compliant with an interface protocol of the NVM chip to operate the NVM chip and receive command execution results output from the NVM chip. Known NVM chip interface protocols include "Toggle", "ONFI", etc.
In chinese patent application publication No. CN1414468A, a scheme is provided for Processing a CPU (Central Processing Unit) instruction by executing a micro instruction sequence. When the CPU is to process a specific instruction, the conversion logic circuit converts the specific instruction into a micro instruction sequence corresponding to the specific instruction, and the function of the specific instruction is realized by executing the micro instruction sequence. The micro instruction sequence or a template of the micro instruction sequence is stored in a ROM (Read Only Memory). In converting a particular instruction into a micro instruction sequence, the micro instruction sequence template may be populated to correspond to the particular instruction.
Chinese patent applications CN201610009789.6 and CN201510253428.1 provide methods and apparatus for executing micro instructions for flash memory interface controllers, and chinese patent application CN 201610861793.5 provides methods and apparatus for scheduling micro instruction sequences, the entire contents of which are incorporated herein. The flash interface controller is typically coupled to a plurality of NVM chips, the NVM chips including a plurality of LUNs (logical units) or dies, which can respond to and access NVM commands in parallel, and since there can be a plurality of NVM commands to be processed on each LUN or die, the NVM controller needs to schedule a plurality of NVM commands or a plurality of microinstruction sequences to maintain a plurality of NVM commands in-process or to be processed, or to maintain a plurality of microinstruction sequences for generating NVM commands.
In a large-capacity solid state disk, the controller needs to connect more NVM chips. Multiple dies or targets may also be included within a single NVM chip. Since each die or target on the NVM Chip has a Chip Enable (CE) pin and each die or target is operated with a separate CE signal applied to it to distinguish it from the operation of other NVM chips/dies/targets in the solid state disk. However, the numerous CE signals require the consumption of a large amount of IO pin resources of the controller.
FIG. 1 is a schematic diagram of a memory system with chip enable signal extension of Chinese patent CN 201632269U. The storage system shown in fig. 1 includes a memory controller 101 (also referred to as a solid state disk controller) and flash channels 1(102) to m (103), each of which includes one or more flash chips (not shown). In the storage system of fig. 1, CE extender 104 is also included. CE extender 104 is connected to memory controller 101. The CE extender 104 is connected to the memory controller 101 via, for example, a CE data signal line and a CE control signal line. Data may also be transferred between CE extender 104 and memory controller 101 via a communication protocol such as IIC (Inter-Integrated Circuit), UART (Universal Asynchronous Receiver/Transmitter), LIN (Local Interconnect Network), etc. in the embodiment of FIG. 1, flash channels 102 and 103 share data signal lines and control signal lines other than chip enable.
In the embodiment of fig. 1, there are m flash memory channels in the memory system, each flash memory channel has 1 flash memory chip, each flash memory chip includes n dies and n Chip Enable (CE) ports corresponding to the n dies, and thus n × m CE signal lines are required in total. These n × m CE signal ports are each connected to CE expander 104, and communication between CE expander 104 and memory controller 201 is performed through fewer signal lines (e.g., the CE data signal line and the CE control signal line in fig. 1). For example, memory controller 101 indicates to CE extender 104 that the first die of the first flash chip on flash channel 103 is to be enabled, CE extender 104 generates a valid enable signal on the corresponding "flash channel m-CE 1" chip enable signal line, and does not generate a valid enable signal on the other chip enable signal lines.
It will still be appreciated that multiple CE expanders may be provided for enabling the memory controller to access more flash memory chips. And the technique provided by chinese patent CN201632269U can be applied to access other NVM chips.
Disclosure of Invention
The application aims to provide an IO command processing method and an NVM interface controller, which are used for supporting the application of a CE expander and an expansion mechanism so as to access more NVM chips.
According to a first aspect of the present invention, there is provided a first IO command processing method according to the first aspect of the present invention, the method including: obtaining an IO command from a command queue; acquiring a virtual LUN number and/or a virtual block address from the IO command; selecting a processing unit according to the virtual LUN number; the processing unit determines a physical LUN accessed by the IO command and a physical block address on the physical LUN according to the virtual block address; sending an effective chip enabling signal to a CE port of a physical LUN accessed by the IO command; and issuing the NVM interface command to the accessed physical LUN.
According to a first IO command processing method of a first aspect of the present invention, there is provided a second IO command processing method of the first aspect of the present invention, wherein the blocks of the virtual LUN are addressed according to the virtual block address, and the number of the blocks of the virtual LUN is equal to the sum of the number of the blocks of the plurality of physical LUNs included in the virtual LUN.
According to a second IO command processing method of the first aspect of the present invention, there is provided a third IO command processing method of the first aspect of the present invention, wherein the virtual LUN includes a plurality of physical LUNs.
According to the first to third IO command processing methods of the first aspect of the present invention, there is provided a fourth IO command processing method of the first aspect of the present invention, in which a processing unit is provided for each virtual LUN, so that when an IO command is processed, a corresponding processing unit is selected according to a virtual LUN number.
According to a fourth IO command processing method of the first aspect of the present invention, there is provided the fifth IO command processing method of the first aspect of the present invention, wherein the processing unit is coupled to a plurality of physical LUNs.
According to a fifth IO command processing method of the first aspect of the present invention, there is provided the sixth IO command processing method of the first aspect of the present invention, wherein the processing unit is coupled to the plurality of physical LUNs through a CE extender; and the CE expander sends an effective chip enabling signal to a CE port of the physical LUN accessed by the IO command under the control of the processing unit.
According to the fifth or sixth IO command processing method of the first aspect of the present invention, there is provided the seventh IO command processing method of the first aspect of the present invention, where the CE extender further sends an invalid chip enable signal to a CE port corresponding to each physical LUN except the accessed physical LUN in the virtual LUN to which the physical LUN accessed by the IO command belongs under the control of the processing unit.
According to the fourth to seventh IO command processing methods of the first aspect of the present invention, there is provided the eighth IO command processing method of the first aspect of the present invention, wherein the processing unit executes its function by executing the microinstruction sequence.
According to an eighth IO command processing method of the first aspect of the present invention, there is provided the ninth IO command processing method of the first aspect of the present invention, wherein the microinstruction sequence has a plurality of execution contexts, and each execution of the microinstruction sequence utilizes one of the plurality of execution contexts.
According to the first to ninth IO command processing methods of the first aspect of the present invention, there is provided the tenth IO command processing method of the first aspect of the present invention, further comprising: the type of the IO command is acquired.
According to a tenth IO command processing method of the first aspect of the present invention, there is provided the eleventh IO command processing method of the first aspect of the present invention, if the IO command is a reset command, acquiring all physical LUNs corresponding to the virtual LUNs, and sending an effective chip enable signal to CE ports that provide all these physical LUNs; and issuing a reset command to all of the physical LUNs; and processing the reset command until the reset command is confirmed to be executed on all physical LUNs.
According to a tenth IO command processing method of the first aspect of the present invention, there is provided the twelfth IO command processing method of the first aspect of the present invention, if the IO command is a reset command, acquiring all physical LUNs corresponding to the virtual LUNs, issuing the reset command to one of the physical LUNs each time, repeatedly issuing the reset command to each physical LUN, and issuing a chip enable signal to a corresponding CE port that provides the physical LUNs; and processing the reset command until all physical LUNs in the virtual LUN are reset.
According to a tenth IO command processing method of the first aspect of the present invention, there is provided a thirteenth IO command processing method of the first aspect of the present invention, wherein if the IO command is a program command, determining a physical LUN to be accessed and a physical block address on the physical LUN according to the accessed virtual block address, and sending a chip enable signal to a CE port providing the physical LUN; and issuing a programming command to the physical LUN; and processing the programming command and acquiring the execution state of the programming command until the execution of the programming command is completed.
According to the first to thirteenth IO command processing methods of the first aspect of the present invention, there is provided the fourteenth IO command processing method of the first aspect of the present invention, further comprising: and recording the execution state of the command in the command set to be processed.
According to a fourteenth IO command processing method of the present invention, there is provided the fifteenth IO command processing method according to the first aspect of the present invention, further comprising: selecting one of the commands to be processed from the set of commands to be processed, obtaining a state of the selected command, and continuing processing of the selected command according to the state of the selected command, wherein each execution of the command may be one phase of executing the command.
According to a fourteenth or fifteenth IO command processing method of the first aspect of the present invention, there is provided the sixteenth IO command processing method of the first aspect of the present invention, in response to receiving a program command, processing the program command on a corresponding physical LUN; pausing the processing of the programming command, and recording the state of the programming command, which indicates the command processing progress, in the command set to be processed; responding to the processing of the recovery programming command, and inquiring the processing progress of the programming command on the corresponding physical LUN; if the processing of the programming command is not finished, continuing the processing of the programming command; and suspending processing of the program command again.
According to the fourteenth to sixteenth IO command processing methods of the first aspect of the present invention, there is provided the seventeenth IO command processing method of the first aspect of the present invention, wherein if there are at least two programming commands accessing the same virtual LUN in the command queue, the first programming command is processed; pausing the processing of the first programming command, and recording the state of the first programming command, which indicates the command processing progress, in the command set to be processed; and if other second programming commands which are not started to be executed exist on the virtual LUN, processing the second programming commands.
According to a seventeenth IO command processing method of the first aspect of the present invention, there is provided the eighteenth IO command processing method of the first aspect of the present invention, if there is no other second command that has not yet started to be executed on the virtual LUN, selecting a first programming command from the set of commands to be processed, and acquiring a state of the first programming command; if the execution state of the first programming command indicates that the execution state of the first programming command is not completed, processing the first programming command; and continuously acquiring the execution state of the first programming command from the physical LUN accessed by the first programming command until the execution state of the first programming command indicates that the processing is finished.
According to an eighth IO command processing method of the first aspect of the present invention, there is provided the nineteenth IO command processing method of the first aspect of the present invention, wherein if the execution status of the first programming command indicates that the processing is completed, the third programming command is continuously selected from the set of commands to be processed.
According to a second aspect of the present invention, there is provided a first IO command processing method according to the second aspect of the present invention, including: obtaining an IO command from a command queue; acquiring a logical LUN number and/or a logical block address from the IO command; obtaining the number of the virtual LUN corresponding to the logical LUN according to the logical LUN number and/or the logical block address; selecting a processing unit according to the number of the virtual LUN and a physical LUN accessed by the IO command; sending an effective chip enabling signal to a CE port of a physical LUN accessed by the IO command; and issuing the NVM interface command to the accessed physical LUN.
According to a first IO command processing method of a second aspect of the present invention, there is provided a second IO command processing method of the second aspect of the present invention, wherein the virtual LUN includes a plurality of physical LUNs; and one or more physical LUNs coupled to different virtual LUNs, or a plurality of physical blocks provided by one or more physical LUNs coupled to different virtual LUNs, are organized as a logical LUN.
According to a second IO command processing method of the second aspect of the present invention, there is provided a third IO command processing method according to the second aspect of the present invention, wherein the logical LUN is mapped to a plurality of virtual LUNs.
According to the second IO command processing method of the second aspect of the present invention, there is provided a fourth IO command processing method of the second aspect of the present invention, wherein the logical LUNs correspond to the physical LUNs one to one.
According to a second IO command processing method of the second aspect of the present invention, there is provided a fifth IO command processing method according to the second aspect of the present invention, wherein a plurality of logical blocks having consecutive logical block addresses within the same logical LUN are mapped to different virtual LUNs.
According to a second IO command processing method of the second aspect of the present invention, there is provided a sixth IO command processing method according to the second aspect of the present invention, wherein a plurality of logical blocks having the same logical block address within different logical LUNs are mapped to different virtual LUNs.
According to the first to sixth IO command processing methods of the second aspect of the present invention, there is provided the seventh IO command processing method of the second aspect of the present invention, wherein a processing unit is provided for each virtual LUN to select a corresponding processing unit according to a virtual LUN number when an IO command is processed.
According to a third aspect of the present invention, there is provided a first NVM interface controller according to the third aspect of the present invention, the NVM interface controller comprising a command queue and an NVM command processing unit, the NVM command processing unit being coupled to the plurality of NVM chips, the command queue being configured to receive an IO command, the NVM command processing unit being configured to obtain the IO command from the command queue and send the NVM interface command to the NVM chips or receive data or status from the NVM chips according to the indication of the IO command, the NVM command processing unit comprising a plurality of processing units configured to access the corresponding NVM chips, the NVM command processing unit being coupled to CE ports of the NVM chips through one or more CE extenders, the NVM command processing unit being further configured to issue a chip enable signal to a designated NVM chip by setting the CE extender to access the corresponding NVM chip.
According to a first NVM interface controller of a third aspect of the present invention there is provided a second NVM interface controller according to the third aspect of the present invention wherein the CE extender is coupled to Chip Enable (CE) ports of the plurality of NVM chips and the NVM command processing unit is configured to send a chip enable or chip disable signal to one of the plurality of NVM chips by setting the CE extender.
According to a third aspect of the present invention, there is provided a third NVM interface controller according to the third aspect of the present invention, wherein a plurality of processing units are coupled to CE ports of a plurality of NVM chips through a plurality of CE extenders, and the plurality of processing units transmit a chip enable signal or a chip disable signal to a designated NVM chip by setting the corresponding CE extender.
According to the first to third NVM interface controllers of the third aspect of the present invention, there is provided the fourth NVM interface controller according to the third aspect of the present invention, wherein the IO command acquired from the command queue indicates a virtual LUN number, the virtual LUN number being used to indicate a virtual LUN, the virtual LUN including a plurality of physical LUNs.
According to the first to fourth NVM interface controllers of the third aspect of the present invention, there is provided a fifth NVM interface controller according to the third aspect of the present invention, wherein the NVM processing units are coupled to a plurality of physical LUNs, the NVM interface controller further being configured to select one of the plurality of processing units to process the IO command according to the virtual LUN number.
According to the first to fifth NVM interface controllers of the third aspect of the present invention, there is provided a sixth NVM interface controller according to the third aspect of the present invention, wherein each NVM chip comprises a plurality of physical LUNs, the processing unit being coupled to the plurality of physical LUNs through the CE extender; and the CE expander sends an effective chip enabling signal to a CE port of the physical LUN accessed by the IO command under the control of the processing unit.
According to a sixth NVM interface controller of a third aspect of the present invention, there is provided a seventh NVM interface controller of the third aspect of the present invention, wherein the CE extender further issues an invalid chip enable signal to a CE port corresponding to a physical LUN other than the physical LUN accessed by the IO command, among the plurality of physical LUNs coupled to the CE extender under the control of the processing unit.
According to the first to seventh NVM interface controllers of the third aspect of the present invention there is provided an eighth NVM interface controller according to the third aspect of the present invention wherein the processing unit performs its functions by executing a sequence of micro-instructions.
According to an eighth NVM interface controller of the third aspect of the present invention there is provided the ninth NVM interface controller according to the third aspect of the present invention wherein the microinstruction sequence has a plurality of execution contexts, one of which is utilized per execution of the microinstruction sequence.
According to the first to ninth NVM interface controllers of the third aspect of the present invention, there is provided the tenth NVM interface controller of the third aspect of the present invention, wherein the NVM command processing unit is further configured to obtain a virtual LUN number and/or a virtual block address from the IO command; and selecting a processing unit according to the virtual LUN number, wherein the processing unit determines the physical LUN accessed by the IO command and the physical block address on the physical LUN according to the virtual block address.
According to a tenth NVM interface controller of a third aspect of the present invention, there is provided the eleventh NVM interface controller of the third aspect of the present invention, wherein the NVM command processing unit accesses blocks of the virtual LUN through the virtual block address, and the number of blocks of the virtual LUN is equal to the sum of the number of blocks of the plurality of physical LUNs comprised by the virtual LUN.
According to the first to eleventh NVM interface controllers of the third aspect of the present invention, there is provided the twelfth NVM interface controller according to the third aspect of the present invention, wherein the NVM command processing unit is further configured to obtain the type of the IO command.
According to a twelfth NVM interface controller of the third aspect of the present invention, there is provided the thirteenth NVM interface controller of the third aspect of the present invention, wherein if the IO command is a reset command, the NVM command processing unit is further configured to obtain all physical LUNs indicated by the virtual LUN numbers, and send chip enable signals to the CE ports providing these physical LUNs by setting the CE extender; and issuing reset commands to the physical LUNs; and processing the reset command until the reset command is confirmed to be executed on all physical LUNs.
According to a twelfth NVM interface controller of the third aspect of the present invention, there is provided the fourteenth NVM interface controller of the third aspect of the present invention, wherein if the IO command is a reset command, the NVM command processing unit is further configured to obtain all physical LUNs indicated by the virtual LUN numbers, issue the reset command to one of the physical LUNs at a time, repeatedly issue the reset command to each physical LUN, and issue a chip enable signal to a corresponding CE port providing the physical LUNs; and processing the reset command until all physical LUNs in the virtual LUN are reset.
According to a twelfth NVM interface controller of the third aspect of the present invention, there is provided the fifteenth NVM interface controller of the third aspect of the present invention, wherein if the IO command is a program command, the NVM command processing unit is further configured to determine, according to the accessed virtual block address, a physical LUN to be accessed and a physical block address on the physical LUN, and send a chip enable signal to a CE port providing the physical LUN; and issuing a programming command to the physical LUN; and processing the programming command and acquiring the execution state of the programming command until the execution of the programming command is completed.
According to the first to fifteenth NVM interface controllers of the third aspect of the present invention, there is provided the sixteenth NVM interface controller according to the third aspect of the present invention, the NVM interface controller further storing a pending command set for recording the status of command execution.
According to a sixteenth NVM interface controller of the third aspect of the present invention, there is provided the seventeenth NVM interface controller according to the third aspect of the present invention, the NVM command processing unit is further configured to select one of the commands to be processed from the set of commands to be processed, and to obtain a status of the selected command, and to execute the selected command, wherein each execution of the command may be one phase of executing the command.
According to a sixteenth or seventeenth NVM interface controller of the third aspect of the present invention, there is provided the eighteenth NVM interface controller of the third aspect of the present invention, the NVM command processing unit is further configured to, in response to receiving the program command, process the program command on the corresponding physical LUN; pausing execution of the programming command, and recording the state of the programming command, which indicates the command processing progress, in the command set to be processed; and in response to execution of the resume program command, querying a processing progress of the program command on the corresponding physical LUN; if the processing of the programming command is not finished, continuing the processing of the programming command; and suspending processing of the program command again.
According to the sixteenth to eighteenth NVM interface controllers of the third aspect of the present invention, there is provided the nineteenth NVM interface controller of the third aspect of the present invention, wherein if there are at least two program commands in the command queue accessing the first virtual LUN, the NVM command processing unit is further configured to process the first program command; pausing the processing of the first programming command, and recording the state of the first programming command, which indicates the command processing progress, in the command set to be processed; and processing the second programming command if other second programming commands which are not started to be executed exist on the first virtual LUN.
According to a nineteenth NVM interface controller of the third aspect of the present invention, there is provided the twentieth NVM interface controller of the third aspect of the present invention, wherein if there is no other second command on the first virtual LUN that has not yet started to be executed, the NVM command processing unit is further configured to select a first program command from the set of commands to be processed, and obtain a status of the first program command; if the execution state of the first programming command indicates that the execution state of the first programming command is not completed, processing the first programming command; and querying an execution status of the first program command from the first physical LUN accessed by the first program command until the execution status of the first program command indicates that the processing is complete.
According to a nineteenth NVM interface controller of the third aspect of the present invention, there is provided the twenty-first NVM interface controller of the third aspect of the present invention, wherein if the execution status of the first program command indicates that the processing is complete, the NVM command processing unit is further configured to select a third program command from the set of commands to be processed.
According to the first to fourth NVM interface controllers of the third aspect of the present invention, there is provided the twenty-second NVM interface controller according to the third aspect of the present invention, wherein the IO command retrieved from the command queue indicates a logical LUN number, and wherein one or more physical LUNs coupled to different virtual LUNs, or a plurality of physical blocks provided by one or more physical LUNs coupled to different virtual LUNs, are organized as a logical LUN.
According to a twenty-second NVM interface controller of a third aspect of the present invention, there is provided the twenty-third NVM interface controller according to the third aspect of the present invention, wherein the NVM media interface controller maps the logical LUN to a plurality of virtual LUNs.
According to a twenty-second NVM interface controller of the third aspect of the present invention, there is provided a twenty-fourth NVM interface controller according to the third aspect of the present invention, wherein the logical LUNs correspond one-to-one to the physical LUNs.
According to a twenty-second NVM interface controller of a third aspect of the present invention, there is provided the twenty-fifth NVM interface controller according to the third aspect of the present invention, wherein the NVM media interface controller maps a plurality of logical blocks having consecutive logical block addresses within the same logical LUN to different virtual LUNs.
According to a twenty-second NVM interface controller of a third aspect of the present invention, there is provided the twenty-sixth NVM interface controller according to the third aspect of the present invention, wherein the NVM media interface controller maps a plurality of logical blocks having the same logical block address within different logical LUNs to different virtual LUNs.
According to the twenty-seventh NVM interface controller according to the third aspect of the present invention, the NVM command processing unit is further configured to obtain a logical LUN number and/or a logical block address from the IO command; obtaining the number of the virtual LUN corresponding to the logical LUN according to the logical LUN number and/or the logical block address; selecting a processing unit according to the number of the virtual LUN; the selected processing unit is used for sending an effective chip enabling signal to a CE port providing the physical LUN accessed by the IO command through the CE expander; and issuing the NVM interface command to the accessed physical LUN.
According to a fourth aspect of the present invention there is provided a solid state storage device according to the fourth aspect of the present invention, the solid state storage device comprising a control means for accessing a plurality of NVM chips, the NVM chips comprising one or more physical LUNs, the control means comprising an NVM interface controller according to the first to seventeenth aspects of the present invention, and one or more CE extenders, wherein the NVM interface controller is coupled to the plurality of NVM chips through the one or more CE extenders for issuing a chip enable signal to a CE port of the NVM chip providing the accessed physical LUN.
According to a fifth aspect of the present invention, there is provided a program including instruction codes according to the fifth aspect of the present invention, which, when loaded into a solid-state storage device and executed on a controller of the solid-state storage device, causes the controller to execute the IO command processing methods according to the first to nineteenth aspects of the present invention, and according to the first to seventh aspects of the present invention.
According to a sixth aspect of the present invention, there is provided a solid-state storage device according to the sixth aspect of the present invention, which includes one or more processors and a memory, the one or more processors executing the IO command processing methods according to the first to nineteenth aspects of the present invention, and according to the first to seventh aspects of the present invention by executing a program in the memory.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art memory system with a chip enable signal extension;
FIG. 2 is a block diagram of an NVM interface controller of a solid state hard disk controller according to an embodiment of the present invention;
FIG. 3 is a block diagram of an NVM interface controller of a solid state hard disk controller according to yet another embodiment of the present invention;
FIG. 4 is a schematic diagram of a virtual LUN according to an embodiment of the present invention;
FIG. 5 is a block diagram of an NVM interface controller of a solid state hard disk controller according to another embodiment of the present invention;
FIG. 6 is a flowchart of a NVM command processing unit processing commands according to an embodiment of the present invention;
FIG. 7 is a flowchart of an NVM command processing unit processing commands according to yet another embodiment of the present invention;
FIG. 8 is a flowchart of a thread processing command of an NVM command processing unit according to yet another embodiment of the present invention;
FIG. 9 is a block diagram of an NVM interface controller of a solid state hard disk controller according to yet another embodiment of the present invention;
FIG. 10 is a diagram of mapping tables of logical LUNs (and blocks) to virtual LUNs and physical LUNs, according to an embodiment of the invention.
FIG. 11 is a block diagram of an NVM interface controller of a solid state hard disk controller according to yet another embodiment of the present invention; and
FIG. 12 is a diagram of a mapping table of logical LUNs (and blocks) to virtual LUNs and physical LUNs according to another embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
FIG. 2 is a block diagram of an NVM interface controller of a solid state hard disk controller according to an embodiment of the present invention. The NVM interface controller of fig. 2 includes a command queue 201 and an NVM command processing unit 202. According to an embodiment of the present invention, the command queue 201 is used to receive commands from a user or an upper system. Commands from a user or upper system may include read, write, delete, mark as invalid, and may also include read NVM chip status, read or set NVM chip Feature (Feature), and may also include user-defined commands. The NVM command processing unit 202 is configured to obtain a command from the command queue 201, and send an NVM interface command conforming to the NVM chip interface standard to the NVM chip according to the command, or receive data or status from the NVM according to the NVM chip interface standard. NVM command processing unit 202 is coupled to multiple NVM chips. In the embodiment of FIG. 2, NVM command processing unit 202 is coupled to 4 NVM chips via 2 channels, each NVM chip including 2 LUNs. The NVM chips in channel 1 provide LUN0-LUN3, and the NVM chips in channel 2 provide LUN4-LUN 7. It will be appreciated that the NVM interface controller can couple more channels and access more NVM chips and more LUNs.
According to an embodiment of the present invention, multiple processing units are provided in NVM command processing unit 202 that access corresponding NVM chips by executing micro instruction sequences. Wherein a sequence of microinstructions that can be executed is referred to as a thread. Since the same micro instruction sequence has its own execution state at each execution, multiple threads can be created based on the same micro instruction sequence. Execution state is also stored in NVM command processing unit 202 for each thread. In an embodiment according to the invention, a thread is created or used based on the LUN to be accessed. For example, thread 1 is used to access LUN1, and/or thread 2 is used to access LUN 2.
Example two
FIG. 3 is a block diagram of an NVM interface controller of a solid state hard disk controller according to yet another embodiment of the present invention. The NVM interface controller of fig. 3 includes a command queue 201 and an NVM command processing unit 202. NVM processing unit 202 includes multiple processing units (not shown) that access corresponding NVM chips by executing micro instruction sequences. Wherein a sequence of microinstructions that can be executed is referred to as a thread. Also shown in FIG. 3 are a plurality of threads of execution that may be scheduled in the NVM interface controller. When a thread is scheduled to execute, NVM processing unit 202 accesses multiple NVM chips by setting up CE extenders.
In one example, referring to fig. 3, the NVM interface controller is coupled to the CE ports of the plurality of NVM chips through a CE extender and sets the CE extender to generate a chip enable signal or a chip disable signal to any one of the plurality of NVM chips (or one of the targets therein) by executing a microinstruction, the like other ports (e.g., DQ, DQs, ALE, CLE, etc.) of the plurality of NVM chips sharing a signal line. For example, by executing the Set _ CE microinstruction, the CE extender is notified that the NVM chip is to be accessed. For example, to access LUN3, thread 1 executes a Set _ CE microinstruction, which causes the CE extender to send a valid chip enable signal to the CE port of the NVM1 chip, and to generate an invalid chip signal to the CE ports of NVM 0, NVM2, and NVM3, thereby validating the NVM1 chip with the command issued by thread 1 to access the NVM chip. In this way, a thread can access multiple NVM chips, multiple LUNs, or multiple targets.
As another example, the NVM interface controller is coupled to the plurality of NVM chips through a plurality of CE extenders, and each CE extender is configured to send a chip enable signal or a chip disable signal to a designated NVM chip (or LUN or target) by executing a microinstruction.
EXAMPLE III
FIG. 4 is a schematic diagram of a virtual LUN according to an embodiment of the present invention. By way of example, thread 2 is coupled to 2 NVM chips through a CE extender, each NVM chip including two LUNs (for clarity, referred to as "physical LUNs"), so that thread 2 can access 4 physical LUNs. Referring to FIG. 4, each physical LUN includes 1024 physical blocks for storing data, and a virtual LUN is provided to represent 4 physical LUNs accessible by thread 2 through the CE extender, such that the virtual LUN includes 4096 physical blocks provided by the 4 physical LUNs. In an embodiment in accordance with the invention, the virtual LUN is accessed in an address space with a block address range of 0-4095, and thread 2 obtains the physical LUN (e.g., physical LUN3) that provides the block according to the block address (e.g., 4000) of the virtual LUN and instructs the CE extender to send an enable signal to the CE port of the NVM chip (e.g., NVM chip 1) where physical LUN3 is located and a disable signal to the other CE ports.
Example four
FIG. 5 is a block diagram of an NVM interface controller of a solid state hard disk controller according to another embodiment of the present invention. According to an embodiment of the present invention, the NVM interface controller receives a command (e.g., User _ CMD _ Post (LUN, block)) from a User or upper system through a command queue, indicating the LUN and block (block) to be accessed. The LUN indicated in the command is a virtual LUN, and the blocks are blocks provided by the virtual LUN. For example, a command accesses block 2047 of virtual LUN 3.
According to the embodiment of the invention, in response to receiving the IO command, the virtual LUN to be accessed is indicated in the command, the NVM command processing unit provides a thread for each virtual LUN, and when processing the command, the NVM command processing unit selects a corresponding thread according to the number of the virtual LUN. For example, a command to access virtual LUN3 is processed by thread 3. Thread 3 determines from the block (address 2047) accessed by the command that the accessed block is provided by a physical block with address 1023 of physical LUN3-2 (see fig. 5), provides a valid chip enable signal to the NVM chip or target providing physical LUN3-2 by setting (e.g., executing Set _ CE microinstruction) the CE extender, and issues the NVM interface command to physical LUN 3-2.
As described above, according to the embodiments of the present invention, by organizing a plurality of physical LUNs as virtual LUNs, the NVM interface controller can access more physical LUNs without increasing the number of threads (each thread manages access to one virtual LUN), thereby implementing a larger capacity solid state disk. And in the view of the upper layer system of the NVM interface controller, the accessing mode of the NVM interface controller is not changed, but the number of blocks included in the virtual LUN is increased, so that the accessing capability to more NVM chips is obtained without changing the upper layer system or with little change.
EXAMPLE five
FIG. 6 is a flowchart of an NVM command processing unit according to an embodiment of the present invention for processing an IO command in the fourth embodiment. According to an embodiment of the present invention, a command processing unit of an NVM interface controller obtains an IO command from a command queue, where the command indicates a command type, a virtual LUN number to be accessed, and/or information of a block address. The command types include program, erase, read, reset, etc.
In one example, the command processing unit obtains an IO command from the command queue, the command indicating that the type of the IO command is a reset command, and the command further indicating a virtual LUN number (e.g., LUN3) to be accessed. Optionally, the block address information is not included in the reset command (601). Next, the NVM command processing unit determines the type of the IO command (602) and determines the IO command as a reset command (613), and in response to receiving the reset command, the NVM command processing unit selects the corresponding thread 4 according to the virtual LUN number (614). Thread 4 is designated to process commands that access virtual LUN 3.
Next, the NVM command processing unit obtains all physical LUNs indicated by the virtual LUN number (615), and issues an enable signal to the NVM chip or the CE pin of the target providing all these physical LUNs by setting (e.g., executing Set _ CE microinstruction) the CE extender, and a reset command to all these physical LUNs (616). And processing the reset command on the physical LUNs and confirming that the reset command execution is complete (617).
Optionally, the NVM command processing unit issues a reset command to one of these physical LUNs at a time, and repeatedly issues a reset command to each physical LUN, and sends an enable signal on the corresponding CE pin that provides these physical LUNs by setting (e.g., executing Set _ CE microinstructions) the CE extender. And processing the reset command on each physical LUN until all physical LUNs in the virtual LUN are reset.
In yet another example, the command processing unit obtains an IO command from the command queue, the type of the IO command is indicated in the command as a program command, and a virtual LUN number (e.g., LUN3) and a block to be accessed are also indicated in the command, wherein the block is a block provided by the virtual LUN (601). Next, the NVM command processing unit determines the type of the IO command (602) and determines the IO command as a reset command (623), and in response to receiving the program command, the NVM command processing unit selects the corresponding thread 4 according to the virtual LUN number (624). Thread 4 determines the physical LUN accessed by the program command according to the block accessed by the command, the physical block address on the physical LUN, and the CE port corresponding to the NVM chip or die (625) providing the physical LUN.
EXAMPLE six
FIG. 7 is a flowchart of an NVM command processing unit processing a command according to yet another embodiment of the present invention. For processing IO commands. Because a virtual LUN includes multiple physical LUNs, which can be accessed in parallel, there is a need to provide parallel processing capability for commands that access different physical LUNs on the virtual LUN. And providing a command set to be processed to record the state indicating the processing progress of the IO command which does not occupy the flash memory channel temporarily.
In an embodiment according to the present invention, a command processing unit of an NVM interface controller obtains an IO command from a command queue (701), where the IO command indicates a command type, a virtual LUN number, and/or information of a block address of the IO command. The NVM command processing unit further records a status of the command indicating progress of command processing in the set of commands to be processed (702), and selects one of the commands to be processed from the set of commands to be processed (703), acquires the status of the selected command, and executes the selected command. Where each execution of a command may be one phase of executing the command (704).
For example, the command processing unit obtains an IO command from the command queue, the type of the IO command is indicated in the command as a program command, and a virtual LUN number (e.g., LUN3) and a block to be accessed are also indicated in the command, wherein the block is a block provided by the virtual LUN. In response to receiving the program command, the NVM command processing unit selects the corresponding thread 5 according to the virtual LUN number. Thread 5 determines the physical LUN accessed by the program command, and the physical block address on that physical LUN, and the NVM chip or die providing that physical LUN, from the block accessed by the command. Next, thread 5 sends an enable signal to the CE pin of the NVM chip or die that provides the physical LUN by setting (e.g., executing Set _ CE microinstruction) the CE extender and issues a program command to the physical LUN.
During the first phase of executing the program command, the NVM command processing unit sends the address of the program command and/or the data to be written to the physical LUN corresponding to the program command, and then records the status of the program command (e.g., processing progress, address accessed, and/or storage location of the data to be written) in the set of commands to be processed. And when the program command is executed, acquiring the program command from the command set to be processed, determining a second stage of executing the command by using the state of the program command provided by the command set to be processed, and then inquiring whether the processing of the program command by the physical LUN is finished.
Between the first stage and the second stage of executing the program command, the NVM command processing unit may obtain one or more IO commands from the command queue for processing, and may also obtain one or more IO commands from the set of commands to be processed for processing. Thereby providing multiple IO commands to the virtual LUN.
Preferably, each physical LUN processes only one IO command at a time. The NVM command processing unit also records whether an IO command has been issued to a physical LUN, and selects an IO command to access a physical LUN for which there is no IO command being processed to process.
EXAMPLE seven
FIG. 8 is a flowchart of a thread processing command of an NVM command processing unit according to yet another embodiment of the present invention for processing IO commands in a queue and processing two or more program commands present in the command queue accessing the same virtual LUN.
In one example, a command processing unit of the NVM interface controller obtains an IO command from a command queue (801), the IO command being indicated as a program command, and the virtual LUN number and a block to be accessed, wherein the block is a block provided by the virtual LUN, are also indicated in the command. In response to receiving the program command, the NVM command processing unit selects the corresponding thread 6 according to the virtual LUN number. Thread 6 determines the physical LUN accessed by the program command and the physical block address on the physical LUN according to the block accessed by the command. Next, thread 6 issues an enable signal to the NVM chip or CE pin of the target where the physical LUN to be accessed is located and issues a program command and/or data to the physical LUN to be accessed by setting (e.g., executing Set _ CE microinstruction) the CE extender. And processing the programming command on the corresponding physical LUN (802).
Next, the NVM command processing unit suspends processing of the current command (e.g., issues a program suspend command to the accessed physical LUN) and records a status indicating progress of command processing with respect to the current command in the pending command set (803). And determining whether there are other commands on the current virtual LUN that have not yet begun execution (804). If there are other IO commands that have not yet started to be executed on the current virtual LUN, repeating the above processing procedure to obtain the IO commands, processing the IO commands on the corresponding physical LUN, and optionally, suspending the processed IO commands.
If there are no other IO commands that have not yet started to be executed on the current virtual LUN, the NVM command processing unit selects one of the program commands in the set of commands to be processed (805), and obtains the status of the program command (e.g., extracts information indicating the command type, the virtual LUN number, and/or the block address), and then selects the corresponding thread 7 according to the virtual LUN number accessed by the program command. Thread 7 determines the physical LUN accessed by the program command, and the physical block address on that physical LUN, from the block accessed by the command (806). Next, the thread 7 sets (e.g., executes Set _ CE microinstruction) the CE extender, and issues an enable signal to the NVM chip or CE pin of the target where the physical LUN to be accessed is located, and issues an inquiry status command to the physical LUN to be accessed, and determines whether the current program command is processed completely (807). If the query status command indicates that execution of the corresponding command (e.g., program command) is complete, selection of other commands in the set of pending commands continues until all commands in the set of pending commands are processed (808). If the query status command indicates that the corresponding command (e.g., the program command) is not completed, the query status command is issued to the physical LUN to be accessed again according to the status information of the corresponding command.
Example eight
FIG. 9 is a block diagram of an NVM interface controller of a solid state hard disk controller according to yet another embodiment of the present invention. According to an embodiment of the present invention, the NVM interface controller receives a command from a user or an upper system through a command queue, the LUN and the block to be accessed being indicated in the command. The LUNs indicated in the command are logical LUNs, and the blocks are blocks provided by the logical LUNs. For example, the command accesses block 2047 of logical LUN 3.
In the embodiment of FIG. 9, the logical LUN is composed of physical LUNs coupled to different CE extenders, thereby facilitating multiple commands accessing the same logical LUN to be executed simultaneously on multiple physical LUNs.
In the embodiment of FIG. 9, a logical LUN consists of 4 physical LUNs. Each physical LUN provides 1024 blocks, so that block 2047 of logical LUN3 can be provided by the 2 nd physical LUN (denoted as logical LUN 3-1) that makes up logical LUN 3. Referring also to FIG. 10, logical LUN0 includes physical LUNs (physical LUN 0-0, physical LUN 1-0, physical LUN 2-0, and physical LUN 3-0) coupled to 4 CE extensions (virtual LUN0, virtual LUN1, virtual LUN2, and virtual LUN3, respectively), and logical LUN3 includes physical LUNs (physical LUN 0-3, physical LUN 1-3, physical LUN 2-3, and physical LUN 3-3), coupled to 4 CE extensions (virtual LUN0, virtual LUN1, virtual LUN2, and virtual LUN3, respectively). According to embodiments of the present invention, mappings of logical LUNs (and blocks) to virtual LUNs and physical LUNs, such as FIG. 10, are maintained by the NVM command processing unit. In response to fetching a command from the command queue, the command processing unit obtains a virtual LUN (or a thread for accessing the virtual LUN) and a physical LUN that provide the accessed block through a mapping table such as that shown in fig. 10, depending on the logical LUN number and the block address indicated in the command, and instructs the thread associated with the virtual LUN to process the command.
By way of example, in response to a received IO command, indicating a block address 2047 of logical LUN3 to be accessed in the command, the NVM command processing unit determines the block accessed by the physical LUN3 associated with thread 8 (see fig. 9, virtual LUN 1); if the received IO command indicates access to block 1023 of logical LUN3, the NVM command processing unit determines that the accessed block is provided by the physical LUN3 associated with thread 9 (see fig. 9, virtual LUN 0). According to an embodiment of the invention, thread 8 processes commands simultaneously with thread 9. Threads 8 and 9 provide valid CE enable signals to the NVM chip or target providing the physical LUN by setting (e.g., executing Set _ CE microinstruction) the CE extender depending on the physical LUN accessed, and issue NVM interface commands to the corresponding physical LUN. Since thread 8 accesses the CE extender corresponding to virtual LUN1 and thread 9 accesses the CE extender corresponding to virtual LUN0, thread 8 and thread 9 can do so simultaneously without resource conflict (e.g., CE extender, physical LUN, etc.) for the processing of IO commands.
As yet another example, the NVM media interface controller maps logical LUNs (and blocks) to virtual LUNs (and physical LUNs) in a different manner, such that accesses to consecutive blocks of a logical LUN are mapped to different virtual LUNs, thereby further increasing the parallelism of command processing.
As yet another example, the NVM media interface controller maps commands that access contiguous blocks within a logical LUN to different virtual LUNs, or maps commands that access blocks of the same address of multiple logical LUNs to different virtual LUNs.
As described above, by providing a logical LUN, commands are distributed by the NVM command processing unit to different threads depending on the logical LUN number and block address. The multiple threads process commands in parallel, and the access parallelism of the NVM interface controller to the NVM chip is enhanced.
Example nine
FIG. 11 is a block diagram of an NVM interface controller of a solid state hard disk controller according to yet another embodiment of the present invention. According to an embodiment of the present invention, the NVM interface controller receives a command from a user or an upper system through a command queue, the LUN and the block to be accessed being indicated in the command. The LUN indicated in the command is a logical LUN. In the embodiment of FIG. 11, the logical LUNs are the same size as the physical LUNs, and each logical LUN is provided by one physical LUN.
In the embodiment of FIG. 11, the logical LUN is composed of physical LUNs coupled to different CE extenders, thereby facilitating multiple commands accessing the same logical LUN to be executed simultaneously on multiple physical LUNs. Referring to FIG. 12, logical LUN0 through logical LUN3 are provided by physical LUN0 (denoted as physical LUN 0-0, physical LUN 1-0, physical LUN 2-0, and physical LUN 3-0, respectively) of each of virtual LUN0 through virtual LUN3 (where the preceding a in the notation "a-b" indicates a virtual LUN number and the following b indicates a physical LUN number in the virtual LUN), and logical LUN4 through logical LUN7 are provided by physical LUN2 (denoted as physical LUN 0-2, physical LUN 1-2, physical LUN 2-2, and physical LUN3-2, respectively) of each of virtual LUN0 through virtual LUN 3. By way of example, providing two physical LUNs per NVM chip, while the NVM interface controller maps a consecutive plurality of logical LUNs to physical LUNs from different NVM chips is advantageous because it can reduce the risk of data being unrecoverable when an NVM chip fails. And mapping the consecutive plurality of logical LUNs to NVM chip physical pages coupled to different CE extenders, such that commands accessing the consecutive plurality of logical LUNs can be processed simultaneously without resource (such as CE extender, physical LUN, etc.) conflicts.
According to embodiments of the present invention, mappings of logical LUNs (and blocks) to virtual LUNs and physical LUNs, such as FIG. 12, are maintained by the NVM command processing unit. In response to fetching a command from the command queue, the command processing unit obtains a virtual LUN (or a thread for accessing the virtual LUN) providing an accessed block and a physical LUN through a mapping table such as that shown in fig. 12 depending on the logical LUN number indicated in the command, and instructs a thread 10 associated with the accessed virtual LUN to process the command. According to an embodiment of the present invention, the thread 10 processes the command, and the thread 10 provides a valid CE enable signal to the NVM chip or target providing the physical LUN by setting (e.g., executing Set _ CE microinstruction) the CE extender according to the accessed physical LUN, and issues the NVM interface command to the physical LUN.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An IO command processing method, comprising:
obtaining an IO command from a command queue;
obtaining LUN number and/or block address from IO command; wherein the LUN number is used to indicate a virtual LUN or a logical LUN, the virtual LUN including a plurality of physical LUNs, the logical LUN including one or more physical LUNs from different virtual LUNs or a plurality of physical blocks provided by one or more physical LUNs from different virtual LUNs;
selecting one or more processing units from the plurality of processing units according to the LUN number;
each processing unit determines a physical LUN accessed by the IO command and a physical block address on the physical LUN according to the block address; sending an effective chip enabling signal to a CE port of a physical LUN accessed by the IO command; and issuing an NVM interface command to the accessed physical LUN, wherein,
each processing unit executes a plurality of IO commands in parallel; or
The plurality of processing units execute one or more IO commands in parallel.
2. An IO command processing method according to claim 1, wherein if the LUN number indicates a logical LUN, a virtual LUN number corresponding to the logical LUN is obtained according to the logical LUN number and/or the logical block address; selecting a processing unit according to the number of the virtual LUN and a physical LUN accessed by the IO command; sending an effective chip enabling signal to a CE port of a physical LUN accessed by the IO command; and issuing the NVM interface command to the accessed physical LUN.
3. An IO command processing method according to claim 1 or 2, wherein a processing unit is provided for each virtual LUN, so that when an IO command is processed, the corresponding processing unit is selected according to the virtual LUN number.
4. The IO command processing method of claim 3, wherein each processing unit executes a plurality of IO commands in parallel, comprising:
each processing unit records the state of the IO command in the command queue indicating the processing progress in the command set to be processed; when an IO command is executed, acquiring the state of the IO command from a command set to be processed, and executing the selected IO command according to the state of the IO command, wherein each execution of the IO command is one stage of command execution, one or more IO commands can be acquired from a command queue between two adjacent stages for processing, and the one or more IO commands are provided to the virtual LUN corresponding to the virtual LUN number.
5. An IO command processing method according to any of claims 1 to 4, wherein a logical LUN is mapped to a plurality of virtual LUNs; or mapping a plurality of logical blocks with continuous logical block addresses within the same logical LUN to different virtual LUNs; or multiple logical blocks with the same logical block address within different logical LUNs are mapped to different virtual LUNs.
6. An IO command processing method according to claim 5, wherein if the logical LUN is mapped to multiple virtual LUNs, the multiple processing units execute one or more IO commands in parallel, including:
responding to a plurality of received IO commands to indicate to access different logic blocks of the same logic LUN, wherein the different logic blocks correspond to different virtual LUNs, and a plurality of processing units corresponding to the different virtual LUNs execute the plurality of IO commands in parallel.
7. An IO command processing method according to claim 5 or 6, wherein if a plurality of logical blocks having consecutive logical block addresses within the same logical LUN are mapped to different virtual LUNs; or mapping a plurality of logical blocks with the same logical block address in different logical LUNs to different virtual LUNs, wherein the plurality of processing units execute one or more IO commands in parallel, and the method comprises the following steps:
and in response to the received IO command indicating to access a continuous logical block in the same logical LUN or indicating to access a plurality of logical blocks with the same logical block address in different logical LUNs, mapping the IO command to different virtual LUNs, wherein the plurality of processing units corresponding to the different virtual LUNs execute the IO command in parallel.
8. A solid-state storage device comprising a control unit and a plurality of NVM chips, the control unit for accessing the plurality of NVM chips, the NVM chips comprising one or more physical LUNs, wherein the control unit comprises an NVM interface controller, and one or more CE extenders, wherein the NVM interface controller is coupled to the plurality of NVM chips through the one or more CE extenders for issuing a chip enable signal to a CE port of the NVM chip providing the accessed physical LUN; and issuing NVM interface commands to the accessed physical LUNs; wherein the content of the first and second substances,
in response to receiving one or more IO commands, the NVM interface controller selecting one or more processing units from a plurality of processing units, each processing unit executing the plurality of IO commands in parallel; or multiple processing units execute one or more IO commands in parallel.
9. The solid-state storage device of claim 8, wherein the NVM interface controller further stores a set of pending commands for recording a status of command execution; selecting one of the commands to be processed from the set of commands to be processed, acquiring the state of the selected command, and executing the selected command, wherein each execution of the command may be one stage of executing the command, and one or more IO commands may be acquired from the command queue between two adjacent stages for processing.
10. A solid state storage device comprising one or more processors and memory, the one or more processors executing the IO command processing method of claims 1-7 by executing a program in the memory.
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| CN202111354827.9A CN113867650A (en) | 2016-12-23 | 2016-12-23 | IO command processing method and solid-state storage device |
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| CN111324414B (en) * | 2018-12-17 | 2024-03-26 | 北京忆芯科技有限公司 | NVM storage media emulator |
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| CN108241468A (en) | 2018-07-03 |
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