CN102792284A - Memory device wear-leveling techniques - Google Patents
Memory device wear-leveling techniques Download PDFInfo
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- CN102792284A CN102792284A CN2010800650391A CN201080065039A CN102792284A CN 102792284 A CN102792284 A CN 102792284A CN 2010800650391 A CN2010800650391 A CN 2010800650391A CN 201080065039 A CN201080065039 A CN 201080065039A CN 102792284 A CN102792284 A CN 102792284A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
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Abstract
The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits.
Description
Background technology
It is erasable that various types of storeies are designed to large tracts of land, is commonly called flash memory (flash memory).Such memory devices can only bear the erase cycles of limited quantity in the mission life scope.The erase cycles quantity that flash memory could bear and continue reliably working can be expressed as the permanance (endurance) of memory devices.As a rule, but at present the given memory cell of flash memory device before can not reliably working erasing times between 10,000 to 100,000.The permanance of memory devices can be depending on the framework in order to the semiconductor technology of making this equipment and this memory devices.
Flash memory is common in the various conditional electronic equipment.After the permanance that exceeds flash memory, flash memory and/or the performance that comprises the electronic equipment of this flash memory possibly affect adversely, even quit work.Thereby, always need improve permanance such as the memory devices of flash memory.
Summary of the invention
The embodiment of present technique is to memory devices loss equalization technology.In one embodiment, the loss equalization method comprises specifying the length of a plurality of logical page (LPAGE)s to translate to a plurality of physical addresss to visit one or more memory devices in LBA and this LBA.Each physical address includes device address, logical block address, block address and page address.
In another embodiment, the loss equalization Memory Controller is found lasting (persistent) state of one or more memory devices.If do not find permanent state for given memory devices, then Memory Controller also can be set up and buffer memory permanent state parameter for each logical block of this given memory devices.
Description of drawings
The embodiment of present technique in following accompanying drawing with example non-limiting mode explain, the similar similar element of numerical reference among the figure, wherein:
Fig. 1 shows the block diagram according to the demonstrative memorizer equipment of an embodiment of present technique.
Fig. 2 shows an embodiment according to present technique, comprises the block diagram of the exemplary electronic equipment of one or more memory devices.
Fig. 3 shows an embodiment according to present technique, is used for logical address is translated to the block diagram of the method for physical address.
Fig. 4 shows an embodiment according to present technique, the process flow diagram of the method for the one or more memory devices of initialization.
Embodiment
To the embodiment of present technique be described in detail now, its exemplary plot is shown in the drawings.Need explanation, when combining these embodiment that present technique is described, be not intended to limit the present invention on these embodiment.Opposite, the invention is intended to cover substitute, change and equivalents, these can be included in by in the defined scope of the present invention of the claims of enclosing.In addition, in the detailed description to present technique subsequently, with listing a large amount of specific details so that making much of present technique to be provided.Yet, need to prove that present technique possibly not have the enforcement of being able under the situation of these specific detail.In the other example, known method, process, assembly and circuit are not specifically described, in order to avoid cause unnecessary obscuring to the present technique each side.
With reference to Fig. 1, shown demonstrative memorizer equipment according to an embodiment of present technique.This demonstrative memorizer equipment 230 can be the piece programmable memory device, for example flash memory device etc.The piece programmable memory device comprises the memory cell that is arranged in array in a large number.Memory cell array is arranged in one or more logical blocks (LUN) 110.Each LUN 110 is made up of the set of (interleaved) physical block 120 that interweaves of memory cell.Each physical block 120 includes a plurality of pages 130 (for example, designation number destination memory location).In a kind of implementation, physical block 120 can comprise 2 an index page (for example, 32 a multiple page).The page 130 of memory cell can comprise an index memory cell (for example, a multiple bit of storage 8) of predefined 2.These pages can be perhaps more from 2 kilobyte to 512 megabyte, and typical sizes is that 4 kilobyte are to 64 kilobyte.Each memory cell is the one or more bits of storage usually.For example, single layer cell (single-level cell, the SLC) data of a bit of storage, and multilevel-cell (multi-level cell MLC) can store the data of two or more bits.
The circuit of such piece programmable storage and memory cell architectures make in the physical block of having wiped 120 of new data write-in block programmable storage 230.As a rule, if data will write in the physical block 120 that has comprised data, then this physical block 120 must be wiped before new data writes.The piece 120 of if block programmable storage 230 is to be write direct by software, and the anomaly number purpose that so skimble-scamble address pattern possibly cause striding more than 230 physical block 120 of storer is wiped.For example, if an address pattern is write by what continue, erasing times will finally exceed the permanance limit of given physical block 120 so.The permanance limit that exceeds piece 120 will reduce the mission life of piece programmable memory device 230.
According to the embodiment of present technique, the logical address that the loss equalization technology produces software is mapped to the physical address of piece programmable memory device.As time goes on this mapping makes that regardless of the software access pattern, all physical blocks in the piece programmable memory device all obtain the erase cycles of number much at one.The loss equalization technology has significantly improved the mission life of piece programmable memory device.In an implementation, for the flash memory device that meets open nand flash memory interface (ONFI) 2.0 standards is used the wear leveling technology.
Referring now to Fig. 2, shown example electronic device according to an embodiment of present technique, it comprises one or more memory devices.This electronic equipment 210 can be computing machine, notebook, cell phone, smart phone, portable music player (for example; The MP3 player), personal digital assistant, net book computing machine, e-book, game console, portable game machine, STB, DVB, navigational system, digital VTR (for example, DVR), server computer and/or like that.
Electronic equipment 210 comprises one or more processing unit 220, system storage 230, Memory Controller 240 and a plurality of programmable memory devices 250, through one or more communication bus 260 communicative couplings.Electronic equipment 210 also can comprise other circuit, for example input-output apparatus 270 or the like.In a kind of implementation, a plurality of programmable memory devices 250 can be flash memory devices.In a kind of implementation, Memory Controller 240 can enable the visit to other memory devices of system storage 230, piece programmable memory device 250 and electronic equipment 210.One or more programmable memory devices 250 can be positioned at the inside or the outside of electronic equipment 210.Memory Controller 240 can be the part of one or more other circuit of electronic equipment 210, perhaps can be separate devices.For example, Memory Controller can be the part of one or more memory devices, one or more processor, one or more other circuit (for example, north bridge chips, GPU) and/or can be discrete nonshared control unit.Memory Controller can adopt one or more modes to realize, for example hardware, firmware and/or computing equipment instructions (for example, software) and processing unit.In another implementation, electronic equipment 210 can comprise a plurality of Memory Controllers, and one in these Memory Controllers is special-purpose piece programmable storage controller 240.
Piece programmable memory device 250 can comprise one or more equipment with different operational factors.For example, memory devices 250 can comprise one or more different memory sizes (for example, the page) that have, and has the equipment of the piece of different numbers, different vacant (spare) piece, different clocking requirements or the like.
Piece programmable storage controller 240 comprises the buffer memory 280 that is used for one or more programmable memory devices of buffer memory 250 permanent state parameters.Piece programmable storage controller 240 can be one or more programmable memory devices 250 buffer memory permanent state parameters, for example be arranged in the bad block data structure bad block data, be arranged in the mapping (enum) data structure mapping (enum) data, be arranged in vacant blocks of data of vacant block data structure or the like.Permanent state parameter buffer memory 280 can be independently, perhaps can be the part of piece programmable storage controller 240.Piece programmable storage controller 240 utilizes the permanent state parameter 280 of institute's buffer memory to handle one or more memory access command; Comprise with LBA with in this LBA and specify the length of an integer logical page (LPAGE) to translate to a plurality of physical addresss to visit one or more memory devices 250, each physical address includes device address, logical block address, block address and page address.In addition, block address comprises one or more interleaving address position.Piece programmable storage controller 240 upgrades the permanent state parameter 280 of institute's buffer memorys and regular log record (journal) permanent state parameter in piece programmable storage 250 subsequently, to improve the loss equalization of piece programmable memory device 250.
Referring now to Fig. 3, according to the method that is used for logical address is translated to physical address of an embodiment of present technique.The address translation method can be implemented by Memory Controller.This method also may be embodied in the manufacturing that comprises the computing equipment instructions; This computing equipment instructions (for example is stored in one or more computing equipment computer-readable recording mediums; Storer), if performed by processing unit, then it comprises execution one or more processes of address translation.This method also may be embodied in the manufacturing that comprises firmware, and this firmware comprises one or more processes of address translation with execution in operation.
Use logical address with visit data to comprise LBA (LBA) and by the integer logical page (LPAGE) of length parameter appointment by software.Physical address comprises device identifier (for example, chip enable), logical block address, block address and page address.The low-order bit of block address comprises one or more interleaving address position.
Amount of physical memory generally includes a plurality of piece programmable memory devices as shown in Figure 2.Accordingly, Address Translator 310 can translate to the physical address of striding a plurality of object block programmable memory devices with the length 320 of LBA (LBA) 315 and a plurality of logical page (LPAGE)s of specifying logical address.In one embodiment, LBA 315 translates to N physical address, and wherein N is not less than the smallest positive integral (N=downwards round (length/page size)) of the length of appointment in the logical address divided by page size.In N physical address each all comprises device field (DFLD) 325, logical block field 330, piece field 335 and page field 340.For in N the physical address each, device field (DFLD) 325 is decoded to be used for of N chip enable of addressable memory equipment.LUN field 330 has been specified the address of given logical block in the addressing physical memory devices.Piece field 335 has been specified in specified LUN given interleaving address.Page field 340 has been specified the address of the page in specified piece.
With the loss equalization compared with techniques of routine, this translation method can be striden a plurality of programmable memory devices flexibly and created different mappings, to obtain higher Performance And Reliability.Except address translation, this method is also supported the initialization of piece programmable device and the discovery of permanent state, the detection of bad physical block and management, and vacant distribution, management and refuse collection, and can avoid the non-sequential of physical page in the piece to programme flexibly.
Referring now to Fig. 4,, shown one or more memory devices have been carried out initialized method according to embodiment of present technique.One or more memory devices are carried out initialized method can be implemented by Memory Controller.Memory Controller can be the part of one or more memory devices, one or more processor and/or one or more other circuit (for example, north bridge chips, GPU), perhaps can be nonshared control unit independently.This method may be embodied in the manufacturing that comprises the computing equipment instructions; This computing equipment instructions (for example is stored in one or more computing equipment computer-readable recording mediums; Storer); If performed by processing unit, then it comprises execution one or more processes of the one or more memory devices of initialization.This method also may be embodied in the manufacturing that comprises firmware, and this firmware comprises one or more processes of the one or more memory devices of initialization with execution in operation.
This method reads the parameter page of a plurality of programmable memory devices since 410 places.The parameter page comprises the parameter of each memory devices; The for example number of the vacant byte of the number of the piece of the number of LUN, each LUN, page size, each page, the ECC byte of being supported (for example, join formula option (strap option)) and/or like that.To each attached memory devices 414-425, the given physical block of each LUN in 430 place's fetch equipments.In a kind of implementation, what read is the piece 0 of each LUN.At 435 places, whether given block type sign checking each LUN confirm the initialization of this piece.
If the given initialization of each LUN will detect and buffer memory initiation parameter.In a kind of implementation, at 440 places, for each each LUN of attached equipment, detect nearest bad block table data structure and buffer memory in addition.At 445 places, for each each LUN of attached equipment, also detect nearest mapping table data structure and buffer memory in addition.At 450 places, for each each LUN of attached equipment, also detect vacant nearest list data structure and buffer memory in addition.To these parameters buffer memory in addition, make given of the store initialization parameter needn't in each parameter update, all write, thereby improved the loss equalization of memory devices.
If given of each LUN does not also have initialization, then LUN is carried out initialization and buffer memory initialization data.In a kind of implementation, detect bad piece at 455 places, and set up and buffer memory bad block table data structure.At 460 places, also foundation and buffer memory are mapped to LBA the mapping table data structure of physical block address.At 465 places, also set up and vacant list data structure of buffer memory.
At 470 places, can handle one or more memory access command.Also can carry out various background tasks at 475 places.Utilize above-mentioned address translation method that memory access command is handled with reference to Fig. 3.Background task possibly comprise refuse collection, upgrades mapping or vacant table, and erase block upgrades erase count, log record mapping, vacant and/or bad block table, or the like.To the log record of mapping table, vacant table and bad block table data structure is that the persistent storage of data is prepared.Utilize above-mentioned address translation method that the data structure is carried out log record with reference to Fig. 3.
According to the embodiment of present technique, the loss equalization technology has advantageously utilized the system memory map list structure to support high capacity (for example, G bytes up to a hundred) and high performance programmable storage, for example ONFI flash memory device.The mapping (enum) data structure also advantageously has flexible semanteme to support a plurality of instances of Memory Controller.This helps to make the firmware scale of implementing this loss equalization technology to minimize.According to this technological embodiment, the index (LBA, length) of virtual address tuple is had programmable hash function, this function is advantageously created variety of option, is used to stride identical or different target memory device and interweaves through the physical address of mapping.
Above-mentioned description to the present technique specific embodiment only is used for example and purpose of description.Be not intended exhaustive or limit the present invention to described definite form, clearly, possibly have multiple change and distortion according to above-mentioned instruction.Selecting and describe these embodiment is for the better principle and the practical application of explanation present technique, thereby makes others skilled in the art can better use present technique and the various embodiment that has carried out various changes for the unique application that is suitable for expecting.Intention defines scope of the present invention by claims of enclosing and equivalent thereof.
Claims (20)
1. store the computing equipment computer-readable recording medium of instruction on one or more its, if moved by one or more processing unit, the method that comprises following content is carried out in then said instruction:
The length of LBA and logical address is translated to a plurality of physical addresss to visit a plurality of memory devices, and wherein each physical address includes device address, logical block address, block address and page address.
2. one or more computing equipment computer-readable recording mediums according to claim 1, wherein, at least two in said a plurality of memory devices is different memory devices.
3. one or more computing equipment computer-readable recording mediums according to claim 1, wherein, said a plurality of memory devices comprise a plurality of flash memory devices.
4. one or more computing equipment computer-readable recording mediums according to claim 1, wherein, said method further comprises:
Read the parameter page of said one or more memory devices;
Read the given physical block of each logical block of each in said one or more memory devices;
Confirm said given initialization whether;
If said given initialization of given logical block then detects and the buffer memory initiation parameter for said given logical block;
If said given no initializtion of given logical block then set up and the buffer memory initiation parameter for said given logical block.
5. one or more computing equipment computer-readable recording mediums according to claim 4, wherein, said method further is included in the initiation parameter of regular log record institute buffer memory in corresponding one or more memory devices.
6. one or more computing equipment computer-readable recording mediums according to claim 4, wherein, detecting also, the buffer memory initiation parameter comprises:
Detect and the nearest bad block table data structure of buffer memory;
Detect and the nearest mapping table data structure of buffer memory; And
Detect and vacant nearest list data structure of buffer memory.
7. one or more computing equipment computer-readable recording mediums according to claim 4, wherein, setting up also, the buffer memory initiation parameter comprises:
Set up and buffer memory bad block table data structure;
Set up and buffer memory mapping table data structure; And
Set up and vacant list data structure of buffer memory.
8. store the computing equipment computer-readable recording medium of instruction on one or more its, if moved by one or more processing unit, the method that comprises following content is carried out in then said instruction:
Find the permanent state of one or more memory devices; And
If do not find permanent state, then set up and buffer memory permanent state parameter for each logical block of given memory devices for given memory devices.
9. one or more computing equipment computer-readable recording mediums according to claim 8, wherein, find that said permanent state comprises:
Read the parameter page of said one or more memory devices;
Read each the given physical block of each logical block of said one or more memory devices;
Detect and the nearest bad block table data structure of buffer memory;
Detect and the nearest mapping table data structure of buffer memory; And
Detect and vacant nearest list data structure of buffer memory.
10. one or more computing equipment computer-readable recording mediums according to claim 9, wherein, setting up also, buffer memory permanent state parameter comprises:
Set up and the said bad block table data structure of buffer memory;
Set up and the said mapping table data structure of buffer memory;
Set up and the said vacant list data structure of buffer memory.
11. one or more computing equipment computer-readable recording mediums according to claim 8; Wherein, Said method comprises that further utilize said permanent state parameter one or more handle one or more memory access command; Comprise the length parameter in LBA and the logical address is translated to a plurality of physical addresss to visit one or more memory devices; Each physical address includes device address, logical block address, block address and page address, and wherein, said block address comprises one or more interleaving address position.
12. one or more computing equipment computer-readable recording mediums according to claim 11, wherein, the said device address of said a plurality of physical addresss is striden a plurality of memory devices and is shone upon.
13. one or more computing equipment computer-readable recording mediums according to claim 12, wherein, at least two in said a plurality of memory devices is different memory devices.
14. one or more computing equipment computer-readable recording mediums according to claim 12, wherein, said a plurality of memory devices comprise a plurality of open nand flash memory interfaces (ONFI) memory devices.
15. one or more computing equipment computer-readable recording mediums according to claim 12, wherein, with one or more log records of said permanent state parameter in the flash memory device of correspondence.
16. an electronic equipment comprises:
Processor;
Communicative couplings is to one or more programmable memory devices of said processor; Wherein, Each piece programmable memory device includes one or more logical blocks, and each logical block includes a plurality of, and each piece includes a plurality of locked memory pages; And
Memory Controller; Comprise hash function able to programme; Translate to a plurality of physical addresss to visit said memory devices in order to the logical address that will comprise LBA and length; Each physical address includes device address, logical block address, block address and page address, in order to stride the physical address that identical or different memory devices interweaves and shone upon.
17. electronic equipment according to claim 16, wherein, said Memory Controller further comprises permanent state parameter buffer memory, and wherein the permanent state parameter of institute's buffer memory is in order to the processing memory visit order.
18. electronic equipment according to claim 17; Wherein, Said Memory Controller is found the permanent state of said one or more programmable memory devices; And if do not find permanent state for given memory devices, would then set up the permanent state parameter for each logical block of given memory devices.
19. electronic equipment according to claim 18, wherein, the permanent state parameter of said Memory Controller regular said given programmable memory device of log record in given programmable memory device.
20. electronic equipment according to claim 19, wherein, said permanent state parameter buffer memory comprises bad block data structure, mapping (enum) data structure and vacant block data structure.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/649,992 US20110161553A1 (en) | 2009-12-30 | 2009-12-30 | Memory device wear-leveling techniques |
| US12/649,992 | 2009-12-30 | ||
| PCT/US2010/057831 WO2011090547A2 (en) | 2009-12-30 | 2010-11-23 | Memory device wear-leveling techniques |
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| CN102792284A true CN102792284A (en) | 2012-11-21 |
| CN102792284B CN102792284B (en) | 2016-05-04 |
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| CN201080065039.1A Active CN102792284B (en) | 2009-12-30 | 2010-11-23 | Memory devices loss equalization technology |
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| US (1) | US20110161553A1 (en) |
| CN (1) | CN102792284B (en) |
| DE (1) | DE112010005074T5 (en) |
| GB (1) | GB2489355B (en) |
| WO (1) | WO2011090547A2 (en) |
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| CN110781102A (en) * | 2019-10-29 | 2020-02-11 | 江苏微锐超算科技有限公司 | Information storage and reading method of computing equipment and shared virtual medium bearing chip |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011090547A2 (en) | 2011-07-28 |
| GB201211590D0 (en) | 2012-08-15 |
| DE112010005074T5 (en) | 2012-12-27 |
| GB2489355A (en) | 2012-09-26 |
| WO2011090547A3 (en) | 2011-10-06 |
| CN102792284B (en) | 2016-05-04 |
| US20110161553A1 (en) | 2011-06-30 |
| GB2489355B (en) | 2017-08-16 |
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