CN110781102A - Information storage and reading method of computing equipment and shared virtual medium bearing chip - Google Patents
Information storage and reading method of computing equipment and shared virtual medium bearing chip Download PDFInfo
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- CN110781102A CN110781102A CN201911037341.5A CN201911037341A CN110781102A CN 110781102 A CN110781102 A CN 110781102A CN 201911037341 A CN201911037341 A CN 201911037341A CN 110781102 A CN110781102 A CN 110781102A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
Abstract
The invention relates to an information processing technology, in particular to an information storage and reading method of a computing device and a shared virtual medium bearing chip, wherein if the information storage and reading method is executed by one or more processing units, an instruction executes a method, which comprises the following steps: receiving a memory access request comprising a logical address; translating a virtual chip enable number from the logical address to a device identifier and determining one or more operating parameters using a virtual chip enable data structure; translating the virtual address into a physical address; and enabling an applicable memory device using the device identifier, routing the memory access request to the applicable memory device, and causing the applicable memory device to execute the memory access request using applicable operating parameters.
Description
Technical Field
The invention relates to an information processing technology, in particular to an information storage and reading method of computing equipment and a shared virtual medium bearing chip.
Background
Various types of memory are designed such that most of the memory is erasable and programmable, and are commonly referred to as flash memories. Such memory devices may withstand a limited number of erase cycles during their operational lifetime. The number of erase cycles that a flash memory can withstand and continue to operate reliably may be expressed as the endurance (endiurance) of the memory device. Typically, a given memory cell of current flash memory devices can be erased between 10,000 and 100,000 times before it can not operate reliably. The endurance of a memory device may depend on the semiconductor process used to manufacture the device and the architecture of the memory device.
Flash memory is common in a variety of conventional electronic devices. When the endurance of the flash memory is exceeded, the performance of the flash memory and/or the electronic device containing the flash memory may be adversely affected, or it may even stop operating. Accordingly, there is a continuing need to improve the endurance of memory devices, such as flash memory.
In addition, flash memory devices come in a variety of geometries and sizes, require different ECC protection, use different protocols, operate in Single Data Rate (SDR) and/or Double Data Rate (DDR) modes. Accordingly, there is a continuing need for improvements in controller interfaces to cooperate with different flash memory devices.
Disclosure of Invention
The invention aims to solve the technical defects and provides an information storage and reading method of a computing device and a shared virtual medium bearing chip.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: an information storage, reading method and a shared virtual medium carrier chip of a computing device, the instructions, if executed by one or more processing units, performing a method comprising: receiving a memory access request comprising a logical address; translating a virtual chip enable number from the logical address to a device identifier and determining one or more operating parameters using a virtual chip enable data structure; translating the virtual address into a physical address; and enabling an applicable memory device using the device identifier, routing the memory access request to the applicable memory device, and causing the applicable memory device to execute the memory access request using applicable operating parameters.
Preferably, a wear leveling algorithm is used to translate the virtual addresses to physical addresses.
Preferably, each of the plurality of memory devices is discovered; determining an operating parameter for each discovered memory device; and establishing the virtual chip enable data structure that maps one or more virtual chip enable numbers to the operating parameters of one or more discovered memory devices and corresponding memory devices.
Preferably, the virtual chip enable data structure comprises a plurality of virtual chip enable entries, each virtual chip enable entry comprising a virtual chip enable number, a device identifier and operating parameters of the respective memory device.
Preferably, wherein a given virtual chip enables to cover multiple physical memory devices.
Preferably, wherein a given plurality of virtual chips enables to overlay a single physical memory device.
The invention achieves the following beneficial effects: the information storage and reading method of the computing equipment and the shared virtual medium load-bearing chip of the invention convert the virtual chip enable number (enabler number) in the logic address into the physical chip enable by using the virtual chip enable data structure. One or more operating parameters are also determined from the virtual chip enable data structure. The virtual address is then translated into a physical address. Thereafter, the applicable memory device may be enabled using the physical chip enable, and the memory access request may be routed to the applicable memory device, whereupon the memory access request is executed using the applicable operating parameters.
Drawings
FIG. 1 shows a block diagram of an exemplary block programmable memory device, in accordance with one embodiment of the present technology.
FIG. 2 illustrates a block diagram of an exemplary electronic device, in accordance with one embodiment of the present technology.
FIGS. 3A and 3B illustrate a flow diagram of a method of enabling virtualization of a chip, according to one embodiment of the present technology.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in the figure: an information storage, reading method and a shared virtual medium carrier chip of a computing device, the instructions, if executed by one or more processing units, performing a method comprising: receiving a memory access request comprising a logical address; translating a virtual chip enable number from the logical address to a device identifier and determining one or more operating parameters using a virtual chip enable data structure; translating the virtual address into a physical address; and using the device identifier to enable an applicable memory device, route the memory access request to the applicable memory device, and cause the applicable memory device to execute the memory access request using applicable operating parameters; translating the virtual address to a physical address using a wear leveling algorithm; discovering each of the plurality of memory devices; determining an operating parameter for each discovered memory device; and establishing the virtual chip enable data structure that maps one or more virtual chip enable numbers to the operating parameters of one or more discovered memory devices and corresponding memory devices; wherein the virtual chip enable data structure comprises a plurality of virtual chip enable entries, each virtual chip enable entry comprising a virtual chip enable number, a device identifier, and operating parameters of the corresponding memory device; wherein a given virtual chip enables to overlay multiple physical memory devices; where a given plurality of virtual chips enables coverage of a single physical memory device.
The information storage and reading method of the computing equipment and the shared virtual medium load-bearing chip of the invention convert the virtual chip enable number (enable number) in the logic address into the physical chip enable by using the virtual chip enable data structure. One or more operating parameters are also determined from the virtual chip enable data structure. The virtual address is then translated into a physical address. Thereafter, the applicable memory device may be enabled using the physical chip enable, and the memory access request may be routed to the applicable memory device, whereupon the memory access request is executed using the applicable operating parameters.
Referring to FIG. 1, an exemplary block programmable memory device in accordance with one embodiment of the present technology is shown. The exemplary memory device 230 may be a flash memory device or the like. A block programmable memory device includes a large number of memory cells arranged in an array. The array of memory units may be arranged in one or more Logical Units (LUNs) 110. Each LUN 110 comprises a set of interleaved physical blocks 120 of memory cells. Each physical block 120 includes a plurality of pages 130 (e.g., a specified number of storage units). In one implementation, physical block 120 may include pages to the power of 2 (e.g., pages that are multiples of 32). The page of memory cells 130 may include memory cells that are power of 2 (e.g., store multiples of 8 bits). The page size may be from 2 kilobytes to 512 megabytes or more, and is typically 4 kilobytes to 64 kilobytes. Each memory cell typically stores one or more bits. For example, a single-level cell (SLC) may store one bit of data, and a multi-level cell (MLC) may store two or more bits of data.
Flash memory such a circuit and memory cell architecture enables new data to be written to erased physical blocks 120 of flash memory 230. Generally, if data is to be written to a physical block 120 that already contains data, then the physical block 120 must be erased before new data is programmed. If blocks 120 of flash memory 230 are accessed and written directly from software, a non-uniform address pattern may result in an irregular number of erasures across multiple physical blocks 120 of memory 230. For example, if the memory at an address is continuously written, the number of erasures will eventually exceed the endurance limit of a given physical block 120. Exceeding the endurance limit of the block 120 will shorten the operational life of the flash memory device 230.
Referring now to FIG. 2, an exemplary electronic device is shown, in accordance with one embodiment of the present technology. The electronic device 210 may be a computer, notebook computer, cellular telephone, smart phone, portable music player (e.g., MP3 player), personal digital assistant, netbook computer, ebook, game console, portable game player, set-top box, satellite receiver, navigation system, digital video recorder (e.g., DVR), server computer, and/or the like.
The electronic device 210 includes one or more processing units 220, a system memory 230, a memory controller 240, and a plurality of block programmable memory devices 250, communicatively coupled via one or more communication buses 260. The electronic device 210 may also include other circuitry, such as input/output devices 270 and the like. In one implementation, the plurality of block programmable memory devices 250 may be flash memory devices. The flash memory device may be an Open NAND Flash Interface (ONFI) compatible device. In one implementation, the memory controller 240 may enable access to the system memory 230, the block programmable memory device 250, and other memory devices of the electronic device 210. In another implementation, the electronic device 210 may include multiple memory controllers, where one of the memory controllers is a dedicated block programmable memory controller 240. The one or more block programmable memory devices 250 may be located internal or external to the electronic device 210. Memory controller 240 may be part of one or more other circuits of electronic device 210 or may be a separate device. For example, the memory controller may be part of one or more memory devices, one or more processors, one or more other circuits (e.g., north bridge chip, graphics processing unit), and/or may be a separate dedicated controller.
One or more of the block programmable memory devices 250 may have different operating parameters. For example, flash memory devices may have different storage capacities (e.g., pages, blocks, spare (spare) blocks), have different timing requirements, use different protocols, require different Error Correction Code (ECC) protections, operate in Single Data Rate (SDR) or Double Data Rate (DDR) modes, may be Single Level Cell (SLC) or multi-level cell (MLC) devices, and/or the like. The same electronic device 210 may sometimes be manufactured with one or more types of block programmable memory devices 250 and at another time with one or more different types of block programmable memory devices. The memory controller 240 may also be utilized in other electronic devices having the same or different block programmable memory devices.
Although embodiments of the present technology are described herein with reference to block programmable memory devices and more specifically with reference to flash memory devices, embodiments of the present technology may also be practiced with any other Integrated Circuit (IC) memory devices. Embodiments of the present technology may be used with a plurality of integrated circuit memory devices, where the memory devices may have non-uniform operating parameters.
The memory controller 240 may be implemented in one or more ways, such as hardware, firmware, and/or computing device readable instructions (e.g., software) and a processing unit (e.g., microcontroller), where the computing device readable instructions, when executed by the processing unit, cause the processing unit to perform one or more processes including Chip Enable (CE) virtualization. In one implementation, memory controller 240 is a non-volatile memory host controller interface (NVMCHI).
The memory controller 240 implements chip-enabled virtualization to support abstraction of multiple block programmable memory devices 250, which may be the same or different from one another 250. The memory controller 240 performs an operation enabled to a virtual Chip Enable (CE) instead of a physical chip. A Virtual Chip Enable (VCE) may be specified in the VCE data structure 280, which VCE data structure 280 is programmed by the memory controller 240 after the initial discovery process. Each VCE entry may include a VCE number (e.g., a tag), a device identifier, and one or more operating parameters of the block programmable memory device. The device identifier may identify a physical or logical device, or a physical or logical partition of a device. For example, the device identifier may be decoded to select a physical chip enable (CD) pin of the device, to select a Logical Unit (LUN) within the device, and/or the like. A given VCE may cover multiple physical memory devices. In addition, two VCEs may overlay a single physical memory device. Thus, virtual chip enables may be associated with one or more logical or physical partitions of one or more block programmable memory devices. The operating parameters of the block programmable memory device 250 may include information regarding pin mappings, geometry (e.g., page size, sector size, number of logical units, number of blocks per logical unit, number of pages per block, etc.), level of ECC protection, protocol usage, and/or the like. In one implementation, the firmware of the memory controller operates a Virtual Chip Enable (VCE) as a logical target, while the hardware of the memory controller enforces the correct routing and functions.
A memory controller, such as a non-volatile memory host interface controller (NVMHCI), may present the concept of a port to an Operating System (OS) to present a single storage entity. Thus, chip-enabled virtualization advantageously allows non-uniform block programmable memory devices to be grouped into a single NVMHCI port.
In an exemplary implementation, an electronic device may include both multi-level cells (MLC) and single-level cells (SLC) on the same flash die (die). The type of flash memory is determined by the address. However, wear leveling algorithms typically operate on a full Chip Enable (CE) or Logical Unit (LUN). Virtualization of chip enables allows wear leveling algorithms to be applied across multiple non-uniform block programmable memory devices. Chip-enabled virtualization allows for the maintenance of the same level of abstraction layer regardless of how the flash device is physically partitioned. In chip enable virtualization techniques, a single physical chip enable may be split into separate, completely independent virtual chip enables when presented to a memory controller. The memory controller utilizes the virtual chip enable data structure to apply the correct ECC, size operations, etc. to access the multi-level cell and single-level cell partitions without the operating system having to know the corresponding parameters of the flash memory device. In another implementation, the virtualized remapping of chip enables provides a way for a memory controller to manage more chip enables than there are hardware resources.
Referring now to fig. 3A and 3B, a method of chip enable virtualization in accordance with one embodiment of the present technology is shown. The method may be embodied in computing device readable instructions stored on one or more computing device readable media (e.g., memory) that, if executed by a processing unit, perform one or more processes including Chip Enable (CE) virtualization. The method may also be implemented in hardware and/or firmware. The method includes a setup phase and a memory access phase. In the setup phase, each of a plurality of block programmable memory devices is discovered 305. In one implementation, a memory controller of an electronic device discovers each of a plurality of block programmable memory devices of the electronic device. At 310, operating parameters are determined for each discovered block programmable memory device. In one implementation, a memory controller determines operating parameters for each block programmable memory device. The operating parameters of the block programmable memory device may include information regarding pin mapping, page size, sector size, number of logical units, number of blocks per logical unit, number of pages per block, level of ECC protection, protocol usage, and/or the like. At 315, a Virtual Chip Enable (VCE) data structure is established. In one implementation, a memory controller establishes a Virtual Chip Enable (VCE) data structure. The Virtual Chip Enable (VCE) data structure includes one or more Virtual Chip Enable (VCE) entries for one or more of the discovered block programmable memory devices. Each Virtual Chip Enable (VCE) entry may include a VCE number (e.g., a tag), a device identifier, and one or more operating parameters of the corresponding block programmable memory device. The device identifier may identify a physical or logical device, or a physical or logical partition of a device.
After the setup phase is complete, the memory controller may operate in a memory access phase. In the memory access phase, at 320, a memory access request including a logical address is received. The memory access request may be received by the memory controller from an application or operating system running on the electronic device. At 325, the VCE number in the logical address is translated to a device identifier of the one or more flash memory devices and the applicable operating parameters for the corresponding physical memory device are determined using the virtual chip enable data structure. In one implementation, the flash controller uses a virtual chip enable data structure to translate the VCE number to chip enable and determine applicable operating parameters. At 330, the logical address is translated to a physical address. A given wear leveling algorithm may be used to translate logical addresses to physical addresses across one or more physical or logical devices. In one implementation, the memory controller also utilizes page tables, translation look-aside buffers, and/or the like to translate logical addresses to physical addresses. At 335, the applicable block programmable memory device is enabled using physical chip enable, the memory access command is routed to the applicable memory device, and the applicable memory device then executes the memory access request using the applicable operating parameters. In one implementation, the memory controller uses the device identifier to enable the applicable block programmable memory device, routes the memory access command to the applicable memory device, and causes the applicable memory device to execute the memory access request using the applicable operating parameters.
Virtual chip enable is a construct that advantageously includes attributes that correspond to unique targets for the memory controller. These attributes may be utilized to access the corresponding memory device, implement a wear leveling algorithm, prepare for the operation of a non-volatile memory host control interface (NVMHCI), and so on. These embodiments advantageously allow block programmable memory devices operating at different rates, protocol standards, and/or the like to be mixed and matched on a system.
The above is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (6)
1. An information storage and reading method of a computing device and a shared virtual medium bearing chip are characterized in that: if executed by one or more processing units, the instructions perform a method comprising: receiving a memory access request comprising a logical address; translating a virtual chip enable number from the logical address to a device identifier and determining one or more operating parameters using a virtual chip enable data structure; translating the virtual address into a physical address; and enabling an applicable memory device using the device identifier, routing the memory access request to the applicable memory device, and causing the applicable memory device to execute the memory access request using applicable operating parameters.
2. The information storage and reading method of the computing device and the shared virtual medium bearing chip according to claim 1, wherein: a wear leveling algorithm is used to translate the virtual address to a physical address.
3. The information storage and reading method of the computing device and the shared virtual medium bearing chip according to claim 1, wherein: discovering each of the plurality of memory devices; determining an operating parameter for each discovered memory device; and establishing the virtual chip enable data structure that maps one or more virtual chip enable numbers to the operating parameters of one or more discovered memory devices and corresponding memory devices.
4. The information storage and reading method of the computing device and the shared virtual medium bearing chip according to claim 3, wherein: wherein the virtual chip enable data structure comprises a plurality of virtual chip enable entries, each virtual chip enable entry comprising a virtual chip enable number, a device identifier, and operating parameters of the corresponding memory device.
5. The information storage and reading method of the computing device and the shared virtual medium bearing chip according to claim 3, wherein: where a given virtual chip enables coverage of multiple physical memory devices.
6. The information storage and reading method of the computing device and the shared virtual medium bearing chip according to claim 3, wherein: where a given plurality of virtual chips enables coverage of a single physical memory device.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102782660A (en) * | 2009-12-31 | 2012-11-14 | 辉达公司 | Virtualization of chip enables |
| CN102792284A (en) * | 2009-12-30 | 2012-11-21 | 辉达公司 | Memory device wear-leveling techniques |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102792284A (en) * | 2009-12-30 | 2012-11-21 | 辉达公司 | Memory device wear-leveling techniques |
| CN102782660A (en) * | 2009-12-31 | 2012-11-14 | 辉达公司 | Virtualization of chip enables |
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