CN110908592A

CN110908592A - Memory management method and memory controller

Info

Publication number: CN110908592A
Application number: CN201811080044.4A
Authority: CN
Inventors: 萧又华; 谢宏志
Original assignee: Shenzhen Da Xin Electronic Technology Co Ltd
Current assignee: Shenzhen Da Xin Electronic Technology Co Ltd
Priority date: 2018-09-17
Filing date: 2018-09-17
Publication date: 2020-03-24
Anticipated expiration: 2038-09-17
Also published as: CN110908592B

Abstract

The invention provides a memory management method. The method comprises the following steps: storing the obtained first instruction to an instruction array, wherein in response to the fact that the first instruction is judged to be a refresh instruction, setting a refresh stage value of the refresh instruction and a corresponding second instruction according to a current refresh stage, calculating a refresh stage count value corresponding to the current refresh stage, and adjusting the current refresh stage; selecting a new target instruction from the instruction array, and executing the target instruction according to a target refresh stage value of the target instruction and a corresponding target refresh stage count value, wherein the target refresh stage count value which is not a preset value is adjusted; and judging whether the target refreshing instruction corresponding to the target refreshing stage value of the host system is completely executed or not according to the adjusted target refreshing stage count value.

Description

Memory management method and memory controller

Technical Field

The present invention relates to a memory management method, and more particularly, to a memory management method and a memory controller for a memory device configured with a rewritable nonvolatile memory module.

Background

A solid state hard disk (a storage device configured with a rewritable non-volatile memory module) of a conventional SATA (serial Advanced Technology attachment) Interface uses an Advanced Host Controller Interface (AHCI) standard, which allows software to communicate with the SATA storage device. In general, AHCI has a depth of 32 instructions, i.e., allows a host system to issue 32 instructions at a time.

However, with the development of hardware itself, the solid state disk of the SATA interface has also evolved into a solid state disk of a PCIe (peripheral component Interconnect express) interface, and the solid state disk of the PCIe interface uses a Non-Volatile Memory host controller interface (NVMe) standard. Generally, NVMe has a depth of 65536 instructions, i.e., the host system is allowed to issue 65536 instructions at the same time. That is, because the NVMe standard can provide nearly two thousand times the instruction depth, the number of instructions from the host system that the storage controller needs to manage also increases substantially.

Therefore, it is one of the topics studied by those skilled in the art how to manage a large number of received instructions under the NVMe standard, and further improve the efficiency of processing instructions by the solid state disk of the PCIe interface.

Disclosure of Invention

The present invention provides a memory management method (also called host command management method) and a memory controller, which can efficiently digest a plurality of commands in a command array and reduce resource robbery caused by a refresh command.

An embodiment of the invention provides a memory management method suitable for a storage device configured with a rewritable nonvolatile memory module. The method comprises the following steps: (1) fetching a new first instruction from an instruction buffer and determining whether the first instruction is a Flush Command, wherein in response to determining that the first instruction is the Flush instruction, performing step (2a), wherein in response to determining that the first instruction is not the Flush instruction, performing step (2 b); (2a) storing the refresh instruction into an instruction array (Command Queue), identifying one or more second instructions in the instruction array corresponding to the refresh instruction according to the refresh instruction, and counting a total number of the refresh instruction and the one or more second instructions to be a refresh stage count value corresponding to a current refresh stage; setting respective refresh phase values of the refresh command and the one or more second commands in the command array according to the current refresh phase, and adjusting the current refresh phase from a first refresh phase to a second refresh phase of a plurality of refresh phases; and performing step (1) or step (3) according to a total number of one or more refresh instructions in the instruction array and a remaining space of the instruction array; (2b) storing the first instruction to an instruction array and performing step (1) or step (3) according to the remaining space of the instruction array; (3) not fetching a new first instruction from the instruction buffer and performing step (4); (4) selecting a new target instruction from one or more non-refresh instructions of the instruction array, identifying a target refresh phase value of the target instruction and a target refresh phase count value corresponding to the target refresh phase value, wherein in response to the target instruction not having the target refresh phase value, performing step (5a), wherein in response to the target instruction having the target refresh phase value, performing step (5 b); (5a) executing the target instruction and, in response to completing execution of the target instruction, deleting the target instruction from the instruction array and performing step (1); (5b) changing the target refresh phase count value, and executing step (5a) or step (5c) according to the changed target refresh phase count value; (5c) and (3) executing the target command, responding to the completion of the target refresh command of the host system corresponding to the target refresh stage value, setting the target refresh stage count value as a preset value, and executing the step (1).

An embodiment of the present invention provides a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The storage controller includes: the device comprises a connection interface circuit, a memory interface control circuit, a host instruction management circuit unit and a processor. The connection interface circuit is used for being coupled to a host system. The memory interface control circuit is used for being coupled to the rewritable nonvolatile memory module. The processor is coupled to the connection interface circuit, the memory interface control circuit and the host command management circuit unit. The processor, wherein the processor is configured to instruct the host instruction management circuit unit to perform a host instruction management operation. The host command management operation comprises the following steps: (1) the host Command management circuit unit is configured to obtain a new first Command from a Command buffer, and determine whether the first Command is a Flush Command (Flush Command), wherein in response to determining that the first Command is the Flush Command, step (2a) is performed, wherein in response to determining that the first Command is not the Flush Command, step (2b) is performed; (2a) the host instruction management circuit unit is used for storing the refresh instruction into an instruction array (Command Queue), identifying one or more second instructions corresponding to the refresh instruction in the instruction array according to the refresh instruction, and counting the total number of the refresh instruction and the one or more second instructions to be a refresh stage count value corresponding to the current refresh stage; the host command management circuit unit is further configured to set respective refresh phase values of the refresh command and the one or more second commands in the command array according to the current refresh phase, and adjust the current refresh phase from a first refresh phase to a second refresh phase of a plurality of refresh phases; and the host command management circuit unit is further configured to perform step (1) or step (3) according to a total number of one or more refresh commands in the command array and a remaining space of the command array; (2b) the host instruction management circuit unit is used for storing the first instruction to an instruction array and executing the step (1) or the step (3) according to the remaining space of the instruction array; (3) the host instruction management circuit unit is used for not acquiring a new first instruction from the instruction buffer and executing the step (4); (4) the host command management circuit unit is configured to select a new target command from one or more non-refresh commands of the command array, identify a target refresh phase value of the target command and a target refresh phase count value corresponding to the target refresh phase value, wherein in response to the target command not having the target refresh phase value, perform step (5a), wherein in response to the target command having the target refresh phase value, perform step (5 b); (5a) the host instruction management circuitry to instruct the processor to execute the target instruction and, in response to completing execution of the target instruction, to delete the target instruction from the instruction array and to perform step (1); (5b) the host command management circuit unit is used for changing the target refresh phase count value and executing the step (5a) or the step (5c) according to the changed target refresh phase count value; (5c) the host command management circuit unit is configured to instruct the processor to execute the target command and respond that the target refresh command corresponding to the target refresh phase value of the host system has been executed, and the host command management circuit unit is further configured to set the target refresh phase count value to a preset value and execute step (1).

Based on the above, the memory management method and the memory controller provided in this embodiment can record, according to the current refresh phase, the corresponding refresh phase value to the refresh command in the command array and the plurality of commands corresponding to the refresh command when the command array receives the refresh command, record the corresponding refresh phase count value, and update the current refresh phase, but do not directly execute, according to the received refresh command, a non-refresh command that clears the refresh command in the command array. In addition, the recorded refresh stage count value is adjusted according to different conditions so as to manage the instructions corresponding to different refresh stages in the instruction array, and further the received refresh instructions are completed. That is, the memory management method and the memory controller provided in this embodiment can prevent the non-refresh command corresponding to the refresh command in the command array from having a special priority (avoid resource preemption of the non-refresh command), so as to avoid delaying the execution of other commands. Therefore, the memory device can be used for completing the received refresh command in the process of smoothly digesting (executing) all the commands in the command array, thereby improving the data access efficiency and the working efficiency of the memory device. In addition, the use of the refresh stage count value allows the memory controller to efficiently manage the plurality of instructions currently in the instruction array corresponding to different refresh stages.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.

Fig. 2A and 2B are flowcharts illustrating a memory management method according to an embodiment of the invention.

FIGS. 3A and 3B are diagrams illustrating an instruction buffer receiving instructions from a host system according to an embodiment of the invention.

Fig. 4A to 4D are schematic diagrams illustrating an exemplary management instruction array according to an embodiment of the invention.

Fig. 5A to 5C are schematic diagrams illustrating an array of management instructions according to another embodiment of the invention.

Description of reference numerals:

10: a host system;

20: a storage device;

110. 211: a processor;

120: a host memory;

130: a data transmission interface circuit;

210: a storage controller;

212: a data management circuit;

213: a memory interface control circuit;

214: an error checking and correcting circuit;

215: a host command management circuit unit;

2151: an instruction array management circuit;

2152: a refresh phase counter circuit;

216: a buffer memory;

217: a power management circuit;

220: a rewritable non-volatile memory module;

230: connecting an interface circuit;

2301: an instruction buffer;

s201, S203, S205, S207, S208, S209, S210, S211, S212, S213, S214: the flow steps of the memory management method;

A. b, C: a node;

n11, N21, N22, N31, N12, F1, F2, F3: instructions;

410. 411: refreshing the stage counting table;

A31-A33, A41-A46, A51-A57, D31-D34, D41-D44, D51-D53, R51, E51-E52: an arrow;

400-407: an instruction array;

410(1) to 410 (3): refreshing the phase count value;

P1-P3: a refreshing stage;

T1.1-T1.7, T2.1-T2.8, T3.1-T3.6: the time point.

Detailed Description

In this embodiment, the memory device includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a memory device controller (also referred to as a memory controller or a memory control circuit). Further, the storage device is used with a host system so that the host system can write data to or read data from the storage device.

Referring to fig. 1, a Host System (Host System)10 includes a Processor (Processor)110, a Host Memory (Host Memory)120, and a Data Transfer Interface Circuit (Data Interface Circuit) 130. In the present embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 are coupled to each other by a System Bus (System Bus).

The Memory device 20 includes a Memory Controller (Storage Controller)210, a Rewritable Non-Volatile Memory Module (Rewritable Non-Volatile Memory Module)220, and a connection interface Circuit (connection interface Circuit) 230. The Memory controller 210 includes a processor 211, a data management Circuit (DataManagement Circuit)212, and a Memory Interface Control Circuit (Memory Interface Control Circuit) 213.

In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of the data transmission interface circuits 130 may be one or more. The motherboard can be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid State Drive (SSD), or a wireless memory storage device. The wireless memory storage device can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, and the like through a System bus.

In the present embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the PCI Express (Peripheral Component Interconnect Express) standard. The data transmission interface circuit 130 and the connection interface circuit 230 transmit data using a Non-Volatile Memory interface (NVMe) protocol.

However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Serial Advanced Technology Attachment (SATA) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed (UHS-I) interface standard, Ultra High Speed (UHS-II) interface standard, memory stick (MemoryStick, MS) interface standard, Multi Chip Package (Multi-p Package) interface standard, Multi media memory Card (Multi, Card) interface standard, Flash memory standard (MC) interface, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. Furthermore, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in one chip, or the connection interface circuit 230 is disposed off the chip containing the memory controller 210.

In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present exemplary embodiment, the host Memory 120 may be a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may be other suitable memories.

The memory controller 210 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to commands of the host system 10.

More specifically, the processor 211 in the memory controller 210 is computing hardware for controlling the overall operation of the memory controller 210. Specifically, the processor 211 has a plurality of control commands, and the control commands are executed to write, read and erase data when the memory device 20 is in operation.

It should be noted that, in the embodiment, the Processor 110 and the Processor 211 are, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, and the invention is not limited thereto.

In one embodiment, the memory controller 210 further has a read only memory (not shown) and a random access memory (not shown). In particular, the rom has a boot code (bootstrap code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. Then, the processor 211 operates the control commands to perform data writing, reading, and erasing operations. In another embodiment, the control instructions of the processor 211 can also be stored in the form of program codes in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit dedicated to storing system data in the rewritable nonvolatile memory module 220.

In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the storage controller 210 may also be considered as operations performed by the storage controller 210.

The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving an instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., a write operation is performed according to a write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more memory cells of the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

The memory interface control circuit 213 is used to receive an instruction from the processor 211 (or the blank cell management circuit 215) and cooperate with the data management circuit 212 to perform a writing (also called Programming) operation, a reading operation or an erasing operation on the rewritable nonvolatile memory module 220. For example, a read operation for the memory cells of the rewritable nonvolatile memory module 220 is performed using a specific read voltage according to an instruction of the blank cell management circuit module 215.

For example, the processor 211 can execute a write command sequence to instruct the memory interface control circuit 213 to write data into the rewritable nonvolatile memory module 220; the processor 211 can execute a read instruction sequence to instruct the memory interface control circuit 213 to read data from one or more physical units of the rewritable nonvolatile memory module 220 corresponding to the read instruction; the processor 211 can execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding operations of writing, reading, and erasing. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.

In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format accepted by the rewritable nonvolatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 executes a write or read command to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the command sequences may include a write command sequence indicating to write data, a read command sequence indicating to read data, an erase command sequence indicating to erase data, and corresponding command sequences indicating various memory operations (e.g., wear leveling operation or garbage collection operation, etc.). The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (the memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), a three-dimensional NAND flash memory module (3D NAND flash memory), or a Vertical NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), or other flash memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.

In the embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each of the word lines includes a plurality of memory cells. Multiple memory cells on the same word line constitute one or more physical programming cells (physical pages). In addition, a plurality of physical programming units can be combined into one physical unit (a physical block or a physical erasing unit). In this embodiment, a physical programming unit can have different types of physical pages. For example, in one embodiment, for a triple cell NAND type flash memory module, one physical program cell of the triple cell NAND type flash memory module can have a first type physical page and a second type physical page. The first type entity Page is, for example, a Lower entity Page (Lower Physical Page) storing one bit value; the second type entity Page is, for example, a Middle entity Page (Middle Physical Page) and an Upper entity Page (Upper Physical Page) each storing one bit value. For another example, in one embodiment, for a triple-level cell NAND type flash memory module, one physical program cell of the triple-level cell NAND type flash memory module can have a first type physical page, a second type physical page, and a third type physical page. The first type entity page is, for example, a lower entity page storing one bit value; the second type entity page is, for example, a middle entity page storing one bit value; the third type entity page is, for example, an upper entity page storing one bit value. Generally, when data is to be written into the upper, middle and lower physical pages of a physical programming unit of a three-level cell NAND-type flash memory module, the data is sequentially written from the lower physical page, then written into the middle physical page, and finally written into the upper physical page.

In the present embodiment, the physical erase unit is the minimum unit of erase, i.e., each physical erase unit contains the minimum number of erased memory cells. Each physical erase cell has a plurality of physical program cells. A physical erase unit may refer to any number of physical program units, depending on the actual requirements.

In the following embodiments, a physical block is taken as an example of a physically erased cell (also referred to as a physical cell), and each physically programmed cell is regarded as a physical subunit. In addition, it should be understood that when the processor 211 groups the physical programming units (or physical units) in the rewritable non-volatile memory module 220 to perform corresponding management operations, the physical programming units (or physical units) are logically grouped, and their actual locations are not changed.

The memory controller 210 configures a plurality of logic units to the rewritable nonvolatile memory module 220. The host system 10 accesses the user data stored in the plurality of physical units through the configured logical unit. Here, each logical unit may be composed of one or more logical addresses. For example, a Logical unit may be a Logical block (Logical block), a Logical Page (Logical Page), or a Logical Sector (Logical Sector). In this embodiment, the logic units are logic blocks, and the logic sub-units are logic pages. Each logic unit has a plurality of logic sub-units. One logical unit may be mapped to one physical unit and one logical sub-unit may be mapped to one physical sub-unit.

In addition, the memory controller 210 establishes a Logical To Physical address mapping table (Logical To Physical address mapping table) and a Physical To Logical address mapping table (Physical To Logical address mapping table) To record a mapping relationship between a Logical address (e.g., Logical block, Logical page, or Logical sector) and a Physical address (e.g., Physical erase unit, Physical program unit, Physical sector) allocated To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may look up the physical address mapped by the logical unit through the logical-to-physical address mapping table, and the memory controller 210 may look up the logical address mapped by the physical address through the physical-to-logical address mapping table. However, the technical concepts related to mapping logical addresses and physical addresses are conventional in the art and will not be described herein.

In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the ECC and ECC circuit 214 generates an Error Correction Code (ECC) and/or an EDC (EDC) for data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 220. Thereafter, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the corresponding error correction code and/or error check code is simultaneously read, and the error checking and correcting circuit 214 performs an error checking and correcting process on the read data according to the error correction code and/or error check code. In addition, after the error checking and correcting process, if the read data is successfully decoded, the error checking and correcting circuit 214 may return an error bit value (also referred to as an error bit number) to the processor 211.

In one embodiment, the memory controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data for managing the storage device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and is used to control the power of the memory device 20.

It should be noted that, in the present embodiment, the connection interface circuit 230 has a Command Buffer 2301 for temporarily storing commands (also called host commands) from the host system 10. The temporarily stored host command is then transmitted to the command array managed by the host command management circuit unit 215 for further management. The instruction Buffer (Command Buffer)2301 is, for example, a static random access memory or other similar memory/storage circuit.

In the present embodiment, the host command management circuit unit 215 includes a command array management circuit 2151 and a refresh phase counter circuit 2152. The processor 211 instructs the host command management circuit unit 215 to perform host command management operations. The operations performed by the components of the host command management circuit unit 215 may also be considered as operations performed by the host command management circuit unit 215. The host instruction management circuit unit 215 (or the instruction array management circuit 2151) is configured to manage an instruction array configured to store host instructions received from the instruction buffer 2301 according to an instruction reception order. In addition, the host command management circuit unit 215 (or the refresh phase counter circuit 2152) may also record and manage information about host commands in the command array, such as refresh phase and refresh phase counter values corresponding to the received host commands, or a refresh phase counter table.

The details of how the host command management circuit unit 215 performs host command management operations and the functions of the command array management circuit 2151 and the refresh phase counter circuit 2152 are described in detail below with reference to several figures.

Fig. 2A and 2B are flowcharts illustrating a memory management method according to an embodiment of the invention. It should be noted that the memory management method shown in fig. 2A and 2B may also be referred to as a host command management method. In addition, node A, B, C is only used to follow the flow for clarity of explanation and is not intended to limit the invention. Referring to fig. 1, fig. 2A and fig. 2B, in step S201, the instruction array management circuit 2151 fetches a new first instruction from the instruction buffer 2301. The first instruction fetched will be stored in the instruction array (Command Queue) of instruction array management circuit 2151.

Specifically, the processor 110 of the host system 10 may issue commands (also referred to as host commands) to the memory device via the data transfer interface circuit. The host instruction is temporarily stored in the instruction buffer 2301. The host Command can be classified into a Flush Command and a Command that is not a Flush Command (also referred to as a non-Flush Command). The flush instruction corresponding to an identified location (or corresponding Thread, or corresponding Namespace) is used to indicate that a plurality of non-flush instructions corresponding to the identified location are to be removed from the instruction array. The present invention is not limited to the identification cell corresponding to the refresh command. For example, in another embodiment, the identification unit includes, and is not limited to: (1) a Client (Client); (2) terminal (Terminal); (3) entity (Entity).

The non-refresh instructions include, and are not limited to: (1) instructions for accessing data, such as a Read Command (Read Command), a write Command (WriteCommand), and the like; and (2) a Trim Command (Trim Command), a power on Command, a power off Command, a hibernation Command, and the like, for controlling the memory device.

The following describes a process of receiving a command from a host system by a command buffer with reference to fig. 3A and 3B.

FIGS. 3A and 3B are diagrams illustrating an instruction buffer receiving instructions from a host system according to an embodiment of the invention. Referring to FIG. 3A, for convenience of illustration, it is assumed that the instruction buffer 2301 has only space for storing 3 instructions. At time T1.1, the processor 110 of the host system 10 issues command N11 to the command buffer 2301 via the data transfer interface circuit 130 (as indicated by arrow D31). "N" in the instruction N11 is used to indicate that this instruction is a non-refresh instruction; the first "1" of "11" is used to indicate that the instruction is the "1" corresponding to the identification unit "1", and the second "1" of "11" is used to indicate that the instruction is the "1" th instruction corresponding to the identification unit "1". The identification code of the identification unit "1" is, for example, "ID 1".

Next, at time T1.2, the instruction buffer 2301 stores the received instruction N11 In a First-In-First-Out (FIFO) manner (as indicated by arrow A31). That is, the instructions stored in the instruction buffer 2301 are arranged chronologically, and the instruction stored earlier is read (fetched) earlier.

Next, at time T1.3, the processor 110 of the host system 10 issues command N21 to the command buffer 2301 via the data transmission interface circuit 130 (as indicated by arrow D32). At time T1.4, the instruction buffer 2301 stores the received instruction N21 in a first-in-first-out manner (as indicated by arrow A32). The instruction N21 is arranged after instruction N11.

Referring to FIG. 3B, at time T1.5, the processor 110 of the host system 10 issues a command F2 to the command buffer 2301 via the data transmission interface circuit 130 (as indicated by arrow D33). "F" in the instruction F1 is used to indicate that this instruction is a refresh instruction; "2" is used to indicate that this instruction corresponds to identification cell "2". The identification code of the identification unit "2" is, for example, "ID 2".

At time T1.6, the instruction buffer 2301 stores the received instruction F2 in a first-in-first-out manner (as indicated by arrow A33). The instruction F2 is arranged after instruction N21. Both instructions N21, F2 correspond to the same identification cell "2". The refresh command F2 is used to indicate that all specific commands of the corresponding identical identification cell "2" prior to the refresh command F2 are deleted (e.g., the refresh command F2 is used to indicate the delete command N21). Further, it should be noted that, in the present embodiment, the specific command corresponding to the refresh command F2 belongs to the write command. For example, assume that the host system sequentially sends a read command, a write command, and a refresh command (all three commands correspond to the same identification cell) to the command buffer 2301. In this example, the flush command is only used to indicate that the write command is to be deleted (and not to indicate that the read command is to be deleted). For convenience of description, the non-refresh commands in the following embodiments are all write commands.

Next, at time T1.7, the processor 110 of the host system 10 issues command N12 to the command buffer 2301 via the data transmission interface circuit 130 (as indicated by arrow D34). Since the instruction buffer 2301 does not have any space (is full), the instruction N12 cannot be stored in the instruction buffer 2301. At this time, the processor 211 may instruct the host command management circuit unit 215 to perform a host command management operation to digest the commands received from the host system stored in the command buffer 2301, so that the command buffer 2301 may clear the space to receive the command N12.

Fig. 4A to 4D are schematic diagrams illustrating an exemplary management instruction array according to an embodiment of the invention. Referring to FIG. 4A, at time point 2.1, as shown by arrow D41, following the above example, the host command management circuit unit 215 fetches a new command (also referred to as a first command) N11 from the command buffer 2301. That is, instruction N11 is transferred (read) to instruction array management circuit 2151 of host instruction management circuit unit 215, and instruction array management circuit 2151 stores instruction N11 to instruction array 400. The refresh phase counter circuit 2152 records a plurality of refresh phase counter values 410(1) to 410(3) corresponding to the plurality of refresh phases P1 to P3. In the embodiment, the plurality of refresh period counts 410(1) -410 (3) have been initialized to a predetermined value (e.g., "0"). In another embodiment, the preset value may be initialized to "-1", a NULL value (i.e., NULL), or other suitable value.

In the present embodiment, the refresh phase counter circuit 2152 may record the plurality of refresh phase counter values 410(1) to 410(3) corresponding to the plurality of refresh phases P1 to P3, respectively, by using the refresh phase counter table 410. The refresh phases P1-P3 are arranged according to a Round Robin (Round Robin) scheme. That is, the refresh phase P2 is arranged after the refresh phase P1; the refresh phase P3 is arranged after the refresh phase P2; the refresh phase P1 is arranged after the refresh phase P3. In addition, the refresh phase counter circuit 2152 records a current refresh phase, which indicates that the current refresh phase is one of the plurality of refresh phases P1-P3. In the present embodiment, in response to a specific event (e.g., the first command received from the command buffer 2301 is a refresh command), the refresh phase counter circuit 2152 switches (adjusts) the current refresh phase from a refresh phase (also referred to as the first refresh phase) to a refresh phase (also referred to as the second refresh phase) arranged after the first refresh phase according to the refresh phases P1-P3 arranged in a round-robin manner. For example, the current refresh phase may be adjusted from the refresh phase P1 to the refresh phase P2; the current refresh phase may be adjusted from the refresh phase P2 to the refresh phase P3; the current refresh phase may be adjusted from the refresh phase P3 to the refresh phase P1. The current refresh phase is initialized, for example, to refresh phase P1. The recorded current refresh phase may be integrated into the refresh phase count table (e.g., a specific field is used to mark the current refresh phase as one of the plurality of refresh phases P1-P3). The refresh phases P1-P3 are switched (adjusted) according to a plurality of refresh commands received successively.

Referring back to fig. 2A, in step S202, the command array management circuit 2151 determines whether the first command is a refresh command. It is decided to execute step S203(S202 → no) or S208(S202 → yes) according to the acquired first instruction. In step S203, instruction array management circuit 2151 stores the first instruction to the instruction array.

For example, referring to FIG. 4A, the command array management circuit 2151 determines that command N11 is not a refresh command, and stores the command N11 in the command array 401 (time point 2.2) as indicated by arrow A41. Note that at this point, the refresh phase value of instruction N11 has not yet been set (blanked).

Next, in step S204, the instruction array management circuit 2151 determines whether the instruction array has a remaining space. Wherein, in response to determining that the instruction array has a remaining space, executing step S201; in response to determining that the instruction array does not have room, step S205 is performed.

For example, as shown in FIG. 4A, instruction array 400 has 5 remaining spaces; instruction array 401 has 4 remaining spaces (one remaining space has been used to store instruction N11). After storing the instruction N11 in the instruction array 401, the instruction array management circuit 2151 determines that the instruction array 401 has a remaining space, and performs step S201 to continue fetching another instruction (new first instruction) from the instruction buffer 2301. For example, referring to FIG. 4B, at time T2.3, instruction N21 is fetched from instruction buffer 2301 as indicated by arrow D42. At a time point T2.4, as shown by an arrow a42, the instruction array management circuit 2151 determines that the instruction N21 is not a refresh instruction, and stores the instruction N21 to the instruction array 402 and is arranged after the instruction N11.

Next, since instruction array management circuit 2151 determines that instruction array 402 has a remaining space, instruction array management circuit 2151 performs step S201 to continue fetching another instruction (new first instruction) from instruction buffer 2301. As shown in fig. 4C, at the time point T2.5, as indicated by an arrow D43, a new command F2 is fetched, the command array management circuit 2151 judges the command F2 as a refresh command, and proceeds to step S208.

In step S208, the instruction array management circuit 2151 stores the refresh instruction into the instruction array, identifies one or more second instructions corresponding to the refresh instruction in the instruction array according to the refresh instruction, and counts the total number of the refresh instruction and the one or more second instructions to become a refresh stage count value corresponding to the current refresh stage.

Specifically, at time point T2.6, the refresh command F2 is stored into the command array 403, as indicated by arrow A43. Further, in response to determining that the received first command F2 is a refresh command, the command array management circuit 2151 identifies one or more second commands in the command array 403 corresponding to the refresh command F2 according to the refresh command F2. In detail, the instruction array management circuit 2151 may identify that the refresh instruction F2 corresponds to identification cell "2", and identify that the refresh instruction F2 is one or more write instructions to delete the corresponding identification cell "2" in the instruction array 403. Accordingly, the command array management circuit 2151 determines that command N21 is the second command corresponding to the refresh command F2 (because command N21 is the write command corresponding to identification cell "2"). The refresh phase counter circuit 2152 counts the total number of the refresh command F2 and the second command N21 in the current command array to become the refresh phase counter value corresponding to the current refresh phase (i.e., the first refresh phase P1). That is, after receiving the refresh command, the command array management circuit 2151 determines that the refresh command and the corresponding second command belong to the same refresh phase, and the refresh phase counting circuit 2152 counts the total number of the refresh command and the corresponding second command, and records the total number as the refresh phase count value corresponding to the refresh phase.

Next, in step S209, the command array management circuit 215 sets the respective refresh phase values of the refresh command and the one or more second commands in the command array according to the current refresh phase, and the refresh phase counter circuit 2152 adjusts the current refresh phase from a first refresh phase to a second refresh phase of a plurality of refresh phases.

For example, referring to fig. 4C, the command array management circuit 215 sets the refresh phase values of the refresh command F2 and the corresponding second command N21 in the command array 403 according to the current refresh phase "P1", i.e., marks the refresh phase values of the refresh command F2 and the corresponding second command N21 in the command array 403 as "P1". It should be noted that since instruction N11 does not correspond to the refresh instruction F2 (instruction N11 does not correspond to identification cell "2". The instruction array management circuit 215 does not set the refresh phase value of instruction N11 (i.e., the refresh phase value of instruction N11 remains blank).

The refresh phase counter circuit 2152 then adjusts the current refresh phase from the first refresh phase P1 to the second refresh phase P2 (as indicated by arrow a 44) of the plurality of refresh phases. In addition, the refresh phase count circuit 2152 also modifies the refresh phase count value 410(1) corresponding to the first phase P1 (the current refresh phase is "P1") from a preset value to "2". In other words, the refresh phase count table is updated from the refresh phase count table 410 to the refresh phase count table 411. It should be noted that the preset value may also be set to other values than 0.

The present invention is not limited to the above-described method of setting the refresh phase value via the current refresh phase. For example, in another embodiment, the command array management circuit 2151 sets the refresh stage values (both being the same identification code) of the refresh command and one or more second commands corresponding to the refresh command in the command array by using the identification code of the identification unit as the refresh stage value according to the identification unit common to the refresh command and the one or more second commands corresponding to the refresh command. For example, assume that instructions F2, N21 both correspond to identification cell "2". The instruction array management circuit 2151 may directly set the refresh phase value of the instruction F2, N21 to "ID 2". In addition, the refresh phase counter circuit 2152 may also record that the refresh phase value corresponding to the refresh phase "ID 2" is "2" (since the total number of commands F2, N21 is two). In other words, the original "P1" can be replaced by the ID2 "of the identification cell of the instruction F2, N21.

Referring back to fig. 2A, in step S210, the instruction array management circuit 2151 determines whether the total number of one or more refresh instructions in the instruction array is greater than the phase upper limit. Wherein, in response to determining that the total number of the one or more refresh instructions in the instruction array is greater than the phase upper limit, instruction array management circuit 2151 performs step 205; in response to determining that the total number of the one or more refresh instructions in the instruction array is not greater than the phase upper limit value, the instruction array management circuit 2151 performs step S204.

Specifically, in the present embodiment, the phase upper limit value is a value obtained by subtracting one from the total number of the plurality of refresh phases P1 to P3 (i.e., 3-1 to 2). That is, the phase ceiling value is used to limit the total number of refresh phase values that are marked into the instruction array to a maximum of the total number of all recordable refresh phase count values (3). That is, if the refresh stage count values of all refresh stages are used (the total number of used refresh stage values is 3), the command array management circuit 2151 performs step S205 to stop fetching the new first command.

For example, as shown in the lower example of FIG. 4C, instruction array management circuit 2151 may determine that the refresh instructions in instruction array 403 are only instruction F2, i.e., the total number of all refresh instructions (i.e., 1) in instruction array 403 is not greater than the phase upper limit. Then, the whole process continues to step S204 to determine whether the instruction array has a remaining space for storing new instructions.

At this time, in step S204, the instruction array management circuit 2151 determines that the instruction array 403 has 2 remaining spaces, and proceeds to step S201. Referring to FIG. 4D, assume that the command buffer 2301 receives 3 commands N12, F1, N31 from the host system 10. From time T2.7, as illustrated in the above flow, instructions N12 and F1 are fetched sequentially (as indicated by arrow D44) and instructions N12 and F1 are stored in the instruction array 404 (as indicated by arrow A45).

In addition, since the command F1 is a refresh command, the command array management circuit 2151 identifies a plurality of commands N11, N12 corresponding to the refresh command F1, and the command array management circuit 2151 sets the refresh phase value of the refresh command F1 in the command array 404 to "P2" and sets the refresh phase value of the second commands N11, N12 corresponding to the refresh command to "P2" according to the current refresh phase "P2". The refresh phase counter circuit 2152 records the refresh count value 410(2) corresponding to the refresh phase "P2" as "3" (no longer a preset value) according to the total number of the refresh command F1 and the corresponding second commands N11, N12, and adjusts the current refresh phase to "P3" (as indicated by arrow 46).

Then, the process continues to step S210. At this point, in step 210, instruction array management circuit 2151 determines that the total number of one or more refresh instructions in the instruction array is not greater than the phase upper limit value. Then, the whole process continues to step S204. However, at this time, the instruction array management circuit 2151 determines that the instruction array 404 does not have any remaining space, and performs step S205. In step S205, the instruction array management circuit 2151 does not fetch a new first instruction from the instruction buffer 2301. Next, in step 206, the instruction array management circuit 2151 selects a new target instruction from one or more non-refresh instructions of the instruction array, identifies a target refresh phase value of the target instruction and a target refresh phase count value corresponding to the target refresh phase value. Wherein, in response to the target instruction having the target refresh phase value, executing step S211; in response to the target instruction not having the target refresh phase value, step S207 is performed. The following description will be made with reference to fig. 5A to 5C.

Referring to FIG. 5A, for example, at time point 3.1, the command array management circuit 2151 identifies one or more non-refresh commands in the command array 404, i.e., commands N11, N21, N12. The ISA 2151 selects one of the instructions N11, N21, N12 as a target instruction according to predetermined rules. For convenience of description, the predetermined rule is a first-in first-out manner. That is, the non-refresh command that is first stored in the command array of the commands N11, N21, and N12 is first selected as the new target command. In the example of fig. 5A, as indicated by arrow E51, the command N11 is selected as the target command, and the command array management circuit 2151 identifies the refresh phase value (also referred to as the target refresh phase value) of the command N11 as "P2". Based on the target refresh phase value "P2", the command array management circuit 2151 identifies "3" based on the refresh phase count value 410(2) recorded by the refresh phase counter circuit 2152 corresponding to the refresh phase "P2" (e.g., the target refresh phase count value is found to be "3" based on the target refresh phase and refresh phase count table).

Referring to fig. 2B, in step S211, the refresh phase counter circuit 2152 decrements the target refresh phase counter value by one. For example, at time T3.2, in response to the target instruction having the target refresh phase value, refresh phase count circuit 2152 decrements the target refresh phase count value by 1, i.e., refresh phase count value 410(2) of corresponding refresh phase P2 is adjusted from "3" to "2" (as indicated by arrow A51).

After subtracting 1, instruction array management circuit 2151 determines whether the target refresh phase count value is equal to 1. Responding to the target refresh stage count value being equal to 1, continuing to step S212; in response to the target refresh period count value not being equal to 1, proceed to step S207.

For example, in the above example, since the target refresh phase count value is "2", it is not equal to 1. Therefore, flow continues to step S207 where instruction array management circuit 2151 directs processor 211 to execute the target instruction, and in response to completing execution of the target instruction, instruction array management circuit 2151 deletes the target instruction from the instruction array. As shown by the arrow D51 in FIG. 5A, the instruction N11 is transmitted to the processor 211, so that the processor 211 performs corresponding operations according to the instruction N11. It should be noted that the invention is not limited to the details of the processor 211 executing instructions. Next, as indicated by arrow A52, the instruction array management circuit 2151 deletes the target instruction N11 and the corresponding target refresh phase value "P2" from the instruction array 404. At this point, the instruction array 405 has a free space (due to the deletion of the target instruction N11 and the corresponding target flush phase value "P2").

Then, the whole flow returns to step S201. Referring to FIG. 5B, for example, assume that the instruction buffer 2301 has 3 host instructions N31, F3, N13. At time point T3.3, instruction N31 is fetched as shown by arrow D52. At time T3.4, instruction N31 is stored in instruction array 406 as indicated by arrow A53. at this time, the process continues with steps S205 and S206 since there is no more space in instruction array 406.

For example, referring to FIG. 5C, at time T3.5, as indicated by arrow E52, the instruction array management circuit 2151 selects instruction N21 as the target instruction and decrements the corresponding target refresh phase count value 410(1) from "2" to "1" (as indicated by arrow A54). At this time, as shown by the arrow a55, in response to the target refresh period count value 410(1) being equal to 1, the method proceeds to step S212. In step 212, instruction array management circuit 2151 directs processor 211 to execute the target instruction, deleting the target instruction in the instruction array in response to completing execution of the target instruction. Step S212 is similar to step S207, and details thereof are not repeated (as indicated by arrow D53). For example, at time T3.6, the command N21 and the corresponding refresh phase value "P1" are deleted as indicated by arrow A56. However, unlike step S201 following step S207, the instruction array management circuit 2151 proceeds to step S213 after step S212. That is, the command array management circuit 2151 also deletes the target refresh command in the command array and responds that the target refresh command corresponding to the target refresh phase value has been executed by the host system. Since all instructions to be deleted (e.g., instruction N21) indicated by the flush instruction F2 have been deleted. Therefore, as indicated by arrow R51, the command array management circuit 2151 indicates to the processor 211 (or the command array management circuit 2151 itself) that the refresh command F2 has been executed in response to the host system 10.

It should be noted that, as can be seen from the above example, the refresh command F2 itself is not executed and other non-refresh commands (e.g., command N11) that do not correspond to the refresh command F2 are also executed during the period after receiving the refresh command F2 and before responding to the completion of the refresh command F2. In addition, after the second command corresponding to the refresh command F2 is executed, the host system 10 can directly receive a response that the refresh command F2 has been executed. In other words, the host command management operation of the embodiment does not rob the execution sequence of the non-refresh command prior to the refresh command, which is not corresponding to the refresh command, by receiving the refresh command, thereby avoiding the resource robbing phenomenon caused by the refresh command.

Continuing to step S214, the refresh phase counter circuit 2152 sets the target refresh phase counter value to a preset value. For example, as shown by the arrow A57, after the refresh command F2 corresponding to the target refresh phase value "P1" has been executed, the target refresh phase count value 410(1) is set to a predetermined value (e.g., "0"). The overall flow then returns to step 201.

It should be noted that in response to neither the instruction buffer 2301 nor the instruction array having any instructions, the host instruction management circuit unit 215 ends all steps of the memory management method. In addition, in response to receiving an instruction from the host system 10 via the empty instruction buffer 2301, the processor 211 may instruct the host instruction management circuit unit 215 to start executing the step S201. If the instruction buffer 2301 does not have the new first instruction that can be fetched (e.g., the instruction buffer 2301 is empty) during the step S201, step S206 is performed.

In summary, the memory management method and the memory controller provided in this embodiment can record, according to the current refresh phase, the corresponding refresh phase value to the refresh instruction in the instruction array and the plurality of instructions corresponding to the refresh instruction when the instruction array receives the refresh instruction, record the corresponding refresh phase count value, and update the current refresh phase, but will not directly execute and clear the non-refresh instruction corresponding to the refresh instruction in the instruction array according to the received refresh instruction. In addition, the recorded refresh stage count value is adjusted according to different conditions so as to manage the instructions corresponding to different refresh stages in the instruction array, and further the received refresh instructions are completed. That is, the memory management method and the memory controller provided in this embodiment can prevent the non-refresh command corresponding to the refresh command in the command array from having a special priority (avoid resource preemption of the non-refresh command), so as to avoid delaying the execution of other commands. Therefore, the memory device can be used for completing the received refresh command in the process of smoothly digesting (executing) all the commands in the command array, thereby improving the data access efficiency and the working efficiency of the memory device. In addition, the use of the refresh stage count value allows the memory controller to efficiently manage the plurality of instructions currently in the instruction array corresponding to different refresh stages.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory management method is suitable for a storage device configured with a rewritable nonvolatile memory module, and comprises the following steps:

(1) fetching a new first instruction from an instruction buffer and determining whether the first instruction is a refresh instruction, wherein in response to determining that the first instruction is the refresh instruction, performing step (2a), wherein in response to determining that the first instruction is not the refresh instruction, performing step (2 b);

(2a) storing the refresh instruction into an instruction array, identifying one or more second instructions in the instruction array corresponding to the refresh instruction according to the refresh instruction, and counting the total number of the refresh instruction and the one or more second instructions to be a refresh stage count value corresponding to a current refresh stage;

setting respective refresh phase values of the refresh command and the one or more second commands in the command array according to the current refresh phase, and adjusting the current refresh phase from a first refresh phase to a second refresh phase of a plurality of refresh phases; and

performing step (1) or step (3) according to a total number of one or more refresh instructions in the instruction array and a remaining space of the instruction array;

(2b) storing the first instruction to an instruction array and performing step (1) or step (3) according to the remaining space of the instruction array;

(3) not fetching a new first instruction from the instruction buffer and performing step (4);

(4) selecting a new target instruction from one or more non-refresh instructions of the instruction array, identifying a target refresh phase value of the target instruction and a target refresh phase count value corresponding to the target refresh phase value, wherein in response to the target instruction not having the target refresh phase value, performing step (5a), wherein in response to the target instruction having the target refresh phase value, performing step (5 b);

(5a) executing the target instruction and, in response to completing execution of the target instruction, deleting the target instruction from the instruction array and performing step (1);

(5b) changing the target refresh phase count value, and executing step (5a) or step (5c) according to the changed target refresh phase count value;

(5c) and (3) executing the target command, responding to the completion of the target refresh command of the host system corresponding to the target refresh stage value, setting the target refresh stage count value as a preset value, and executing the step (1).

2. The memory management method of claim 1, wherein the command buffer is configured to receive commands from the host system, wherein the method further comprises:

ending all steps of the memory management method in response to neither the instruction buffer nor the instruction array having any instructions; and

in response to receiving a command from the host system via the empty command buffer, beginning to perform step (1) above,

wherein the step of fetching the new first instruction from the instruction buffer of step (1) above comprises performing step (4) in response to the instruction buffer not having the new first instruction available to be fetched.

3. The memory management method according to claim 1, wherein the command array is maintained in a host command management circuit unit, all commands of the command array are respectively marked with corresponding refresh phase values, wherein a refresh phase count table is maintained in the host command management circuit unit, and the refresh phase count table records a plurality of refresh phases and a plurality of refresh phase count values respectively corresponding to the plurality of refresh phases, wherein the step (4) comprises:

selecting the target instruction from the one or more non-refresh instructions of the instruction array in a first-in-first-out manner; and

and identifying the marked target refresh stage value of the target instruction from an instruction array, and searching a corresponding target refresh stage count value from the refresh stage count table according to the target refresh stage value.

4. The memory management method of claim 1, wherein said step (5b) comprises:

in response to the target instruction having the target refresh phase value, decrementing the target refresh phase count value by one to change the target refresh phase count value;

determining whether the changed target refresh period count value is equal to 1, wherein in response to the target refresh period count value not being equal to 1, executing step (5a),

wherein step (5c) is performed in response to the target refresh phase count value being equal to 1,

wherein the step (5c) comprises:

in response to completing execution of the target instruction, deleting the target instruction and the target flush instruction in the instruction array.

5. The memory management method of claim 1, wherein the refresh command is used to instruct deletion of the one or more second commands of the command array, and the refresh command and the one or more second commands both correspond to the same identification unit, wherein the step (2a) comprises:

not executing the one or more second instructions according to the refresh instruction and not deleting the one or more second instructions;

recording the refresh phase count value to correspond to the first refresh phase of the plurality of refresh phases,

wherein the plurality of refresh phases are arranged in a cyclic manner and the second refresh phase is arranged after the first refresh phase.

6. The memory management method of claim 5, wherein the step of step (2a) above according to the total number of the one or more refresh instructions in the instruction array and a remaining space of the instruction array comprises:

determining whether a total number of the one or more refresh instructions in the instruction array is greater than a phase ceiling value,

wherein in response to determining that the total number of the one or more refresh instructions is greater than the phase ceiling value, performing step (3),

wherein in response to determining that the total number of the one or more refresh instructions is not greater than the phase ceiling, determining whether the instruction array has the remaining space, wherein in response to determining that the instruction array does not have the remaining space, performing step (3), wherein in response to determining that the instruction array has the remaining space, performing step (1).

7. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:

the system comprises a connection interface circuit, a processor, a memory and a control circuit, wherein the connection interface circuit is used for being coupled to a host system and comprises an instruction buffer used for temporarily storing instructions from the host system;

a memory interface control circuit for coupling to the rewritable nonvolatile memory module;

a host command management circuit unit; and

a processor coupled to the connection interface circuit, the memory interface control circuit and the host command management circuit unit, wherein the processor is configured to instruct the host command management circuit unit to perform a host command management operation, the host command management operation comprising the steps of:

(1) the host command management circuit unit is configured to fetch a new first command from a command buffer and determine whether the first command is a refresh command, wherein in response to determining that the first command is the refresh command, step (2a) is performed, wherein in response to determining that the first command is not the refresh command, step (2b) is performed;

(2a) the host instruction management circuit unit is used for storing the refresh instruction into an instruction array, identifying one or more second instructions corresponding to the refresh instruction in the instruction array according to the refresh instruction, and counting the total number of the refresh instruction and the one or more second instructions to form a refresh stage count value corresponding to the current refresh stage;

the host command management circuit unit is further configured to set respective refresh phase values of the refresh command and the one or more second commands in the command array according to the current refresh phase, and adjust the current refresh phase from a first refresh phase to a second refresh phase of a plurality of refresh phases; and

the host instruction management circuit unit is further used for executing the step (1) or the step (3) according to the total number of one or more refresh instructions in the instruction array and the remaining space of the instruction array;

(2b) the host instruction management circuit unit is used for storing the first instruction to an instruction array and executing the step (1) or the step (3) according to the remaining space of the instruction array;

(3) the host instruction management circuit unit is used for not acquiring a new first instruction from the instruction buffer and executing the step (4);

(4) the host command management circuit unit is configured to select a new target command from one or more non-refresh commands of the command array, identify a target refresh phase value of the target command and a target refresh phase count value corresponding to the target refresh phase value, wherein in response to the target command not having the target refresh phase value, perform step (5a), wherein in response to the target command having the target refresh phase value, perform step (5 b);

(5a) the host instruction management circuitry to instruct the processor to execute the target instruction and, in response to completing execution of the target instruction, to delete the target instruction from the instruction array and to perform step (1);

(5b) the host command management circuit unit is used for changing the target refresh phase count value and executing the step (5a) or the step (5c) according to the changed target refresh phase count value;

(5c) the host command management circuit unit is configured to instruct the processor to execute the target command and respond that the target refresh command corresponding to the target refresh phase value of the host system has been executed, and the host command management circuit unit is further configured to set the target refresh phase count value to a preset value and execute step (1).

8. The storage controller of claim 7, wherein the instruction buffer is to receive instructions from the host system, wherein

In response to neither the instruction buffer nor the instruction array having any instructions, the host instruction management circuit unit terminates all steps of the memory management method; and

in response to receiving a command from the host system via the empty command buffer, the host command management circuit unit starts executing the step (1),

9. The memory controller of claim 7, wherein the command array is maintained in the host command management circuit unit, all commands of the command array are each marked with a corresponding refresh phase value, wherein a refresh phase count table is maintained in the host command management circuit unit, and the refresh phase count table records the plurality of refresh phases and a plurality of refresh phase count values respectively corresponding to the plurality of refresh phases, wherein the step (4) comprises:

the host instruction management circuit unit selects the target instruction from the one or more non-refresh instructions of the instruction array according to a first-in-first-out manner; and

the host instruction management circuit unit identifies the marked target refresh stage value of the target instruction from an instruction array, and searches a corresponding target refresh stage count value from the refresh stage count table according to the target refresh stage value.

10. The storage controller of claim 7, wherein said step (5b) comprises:

in response to the target instruction having the target refresh phase value, the host instruction management circuit unit decrements the target refresh phase count value by one to change the target refresh phase count value;

the host command management circuit unit determines whether the changed target refresh period count value is equal to 1, wherein in response to the target refresh period count value not being equal to 1, step (5a) is performed,

wherein the step (5c) comprises:

in response to completion of execution of the target instruction, the host instruction management circuit unit deletes the target instruction and the target refresh instruction in the instruction array.

11. The memory controller of claim 7, wherein the refresh command is configured to instruct deletion of the one or more second instructions of the instruction array, and the refresh command and the one or more second instructions all correspond to a same identification cell, wherein step (2a) comprises:

the host instruction management circuit unit does not execute the one or more second instructions according to the refresh instruction and does not delete the one or more second instructions;

the host command management circuit unit records the refresh phase count value to correspond to the first refresh phase of the plurality of refresh phases,

12. The memory controller of claim 11, wherein the step of step (2a) above according to the total number of the one or more refresh instructions in the instruction array and a remaining space of the instruction array comprises:

the host command management circuitry unit determines whether a total number of the one or more refresh commands in the command array is greater than a phase ceiling value,

wherein in response to determining that the total number of the one or more refresh instructions is not greater than the phase ceiling value, the host instruction management circuitry unit determines whether the instruction array has the remaining space, wherein in response to determining that the instruction array does not have the remaining space, step (3) is performed, wherein in response to determining that the instruction array has the remaining space, step (1) is performed.