CN115576867A - Extended address space for memory devices - Google Patents
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- CN115576867A CN115576867A CN202211289621.7A CN202211289621A CN115576867A CN 115576867 A CN115576867 A CN 115576867A CN 202211289621 A CN202211289621 A CN 202211289621A CN 115576867 A CN115576867 A CN 115576867A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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Abstract
An extended address space of a storage device is provided. A method for accessing an extended address space of a storage device is provided, comprising: acquiring a write expansion area command for accessing an expansion address space; writing data corresponding to the command for writing the extended area into a first physical address; generating a mirror image area writing command according to the extended area writing command; writing data corresponding to the mirror image area writing command into a second physical address; and indicating that write extent command processing is complete.
Description
Technical Field
The present application relates to storage devices, and in particular, to managing and using an extended address space of a storage device.
Background
FIG. 1 illustrates a block diagram of a solid-state storage device. The solid state storage device 102 is coupled to a host for providing storage capability to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.
NAND flash Memory, phase change Memory, feRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.
The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.
The memory Target (Target) is one or more Logic Units (LUNs) that share CE (Chip Enable) signals within the NAND flash package. One or more dies (Die) may be included within the NAND flash memory package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other.
Data is typically stored and read on a storage medium on a page-by-page basis. And data is erased in blocks. A block (also referred to as a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on the storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. Physical pages may also have other sizes.
In the solid-state storage device, mapping information from logical addresses to physical addresses is maintained using FTL (Flash Translation Layer). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented using an intermediate address modality in the related art. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.
A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.
The FTL table includes a plurality of FTL table entries (or table entries). In one case, each FTL table entry records a correspondence relationship between one logical page address and one physical page. In another case, each FTL table entry records the correspondence relationship between the continuous multiple logical page addresses and the continuous multiple physical pages. In yet another case, each FTL table entry records a correspondence relationship between logical block addresses and physical block addresses. In still another case, the mapping relationship between the logical block address and the physical block address and/or the mapping relationship between the logical page address and the physical page address are recorded in the FTL table.
Disclosure of Invention
In addition to the storage space provided by the logical addresses, the storage device according to embodiments of the present application stores other data by extending the address space, such as, for example, s.m.a.r.t. (Self-Monitoring, analysis, and Reporting Technology) information according to industry standards, metadata inside the storage device, a working log of the storage device, and the like. And managing the logical address space and the extended address space using a single address mapping mechanism by integrating the extended address space with the logical address space.
According to a first aspect of the present application, there is provided a first method for accessing an extended address space of a storage device according to the first aspect of the present application, including: acquiring a write extension area command for accessing an extension address space;
writing data corresponding to the command for writing the extended area into a first physical address; generating a mirror image area writing command according to the extended area writing command; writing data corresponding to the mirror image area writing command into a second physical address; and indicating that the write extent command processing is complete.
According to a first method for accessing an extended address space of a storage device in a first aspect of the present application, a second method for accessing an extended address space of a storage device in a first aspect of the present application is provided, which further includes: acquiring a write command for accessing a logical address space; writing data corresponding to the write command into a third physical address; and indicating that write command processing is complete.
According to a second method of accessing an extended address space of a storage device according to the first aspect of the present application, there is provided a third method of accessing an extended address space of a storage device according to the first aspect of the present application, wherein the extended address space and the logical address space are mapped to a logical address area and an extended area of an intermediate address space, respectively.
According to a third method of accessing an extended address space of a storage device according to the first aspect of the present application, there is provided a fourth method of accessing an extended address space of a storage device according to the first aspect of the present application, wherein an address of a write extent command accessing the extended address space is mapped to a first address of an extent; the mirror image writing command accesses a second address, and the second address belongs to a mirror image area of an intermediate address space; the second address is calculated from the first address.
According to a third or fourth method of accessing an extended address space of a storage device according to the first aspect of the present application, there is provided a fifth method of accessing an extended address space of a storage device according to the first aspect of the present application, wherein the write command accesses a third address, the third address belonging to a logical address area of the intermediate address space.
According to the fourth or fifth method for accessing an extended address space of a storage device in the first aspect of the present application, there is provided the sixth method for accessing an extended address space of a storage device in the first aspect of the present application, wherein in response to writing data corresponding to a write extent command into a first physical address, a correspondence between the first physical address and a first address accessed by the write extent command is recorded; and writing the data corresponding to the command of writing the mirror image area into the second physical address, and recording the corresponding relation between the second address accessed by the command of writing the mirror image area and the second physical address.
According to one of the first to sixth methods for accessing an extended address space of a storage device of the first aspect of the present application, there is provided a seventh method for accessing an extended address space of a storage device of the first aspect of the present application, wherein data corresponding to the write mirror area command is the same as data corresponding to the write extended area command.
According to one of the fourth to sixth methods for accessing an extended address space of a storage device in the first aspect of the present application, there is provided a method for accessing an extended address space of a storage device in the eighth aspect of the present application, wherein a physical address of a storage medium of a first type is allocated to an address of a logical address area; allocating the physical address of a second type storage medium to the address of the expansion area; and the second type of storage medium has a lower access latency than the first type of storage medium.
According to one of the first to eighth methods for accessing an extended address space of a storage device in the first aspect of the present application, there is provided a ninth method for accessing an extended address space of a storage device in the first aspect of the present application, further comprising: responding to the command of acquiring the write expansion area, and distributing one or more cache units for the command of the write expansion area; wherein the write mirror command is processed using the one or more cache units.
According to a ninth method for accessing an extended address space of a storage device in the first aspect of the present application, there is provided a tenth method for accessing an extended address space of a storage device in the first aspect of the present application, further comprising: and releasing the one or more second cache units in response to writing the data corresponding to the writing mirror area command into the second physical address.
According to a ninth or tenth method of accessing an extended address space of a memory device of the first aspect of the present application, there is provided the eleventh method of accessing an extended address space of a memory device of the first aspect of the present application, further comprising: in response to obtaining a write command, one or more cache units are allocated for the write command.
According to the first to eleventh methods for accessing an extended address space of a memory device of the first aspect of the present application, there is provided a twelfth method for accessing an extended address space of a memory device of the first aspect of the present application, further comprising: acquiring a read extension area command for accessing an extension address space; acquiring a first physical address according to a first address of the read extension area command, and reading data from the first physical address; in response to an error in reading data from the first physical address; generating a mirror image area reading command; acquiring a second physical address according to the second address of the mirror image area reading command, and reading data from the second physical address; and responding to the read expansion area command by reading the data from the second physical address.
According to a second aspect of the present application, there is provided a method for accessing an extended address space of a storage device according to the second aspect of the present application, including: acquiring a read extension area command for accessing an extension address space; acquiring a first physical address according to a first address of the read extension area command, and reading data from the first physical address; in response to an error in reading data from the first physical address; generating a mirror image area reading command; acquiring a second physical address according to the second address of the mirror image area reading command, and reading data from the second physical address; and responding to the read extension area command by reading the data from the second physical address.
According to a first method for accessing an extended address space of a storage device in a second aspect of the present application, there is provided a second method for accessing an extended address space of a storage device in a second aspect of the present application, further comprising: acquiring a read command for accessing a logical address space; acquiring a third physical address from a third address of the write command, and reading data from the third physical address; and reading data from the third address as a response to the read command.
According to a second method of accessing an extended address space of a storage device of the second aspect of the present application, there is provided a third method of accessing an extended address space of a storage device of the second aspect of the present application, wherein the extended address space and the logical address space are mapped to a logical address area and an extended area of an intermediate address space, respectively.
According to a third method of accessing an extended address space of a storage device according to the second aspect of the present application, there is provided a fourth method of accessing an extended address space of a storage device according to the second aspect of the present application, wherein a read extent command accesses an address of the extended address space mapped to a first address of an extent; the mirror image reading command accesses a second address, and the second address belongs to a mirror image area of an intermediate address space; the second address is calculated from the first address.
A method of accessing an extended address space of a memory device according to the fifth aspect of the present application is provided according to the third or fourth method of accessing an extended address space of a memory device of the second aspect of the present application, wherein the read command accesses a third address, the third address belonging to a logical address area of the intermediate address space.
According to the fourth or fifth method for accessing an extended address space of a storage device in the second aspect of the present application, there is provided a method for accessing an extended address space of a storage device in the sixth aspect of the present application, wherein in response to acquiring the read extent command, a first physical address is obtained by querying an FTL table according to a first address accessed by the read extent command; and responding to the generated mirror image area reading command, and inquiring an FTL (flash translation layer) table to obtain a second physical address according to a second address accessed by the mirror image area reading command.
According to a fifth method for accessing an extended address space of a storage device in the second aspect of the present application, there is provided a seventh method for accessing an extended address space of a storage device in the second aspect of the present application, wherein a physical address corresponding to a third address of a logical address area is from a first type of storage medium; the physical address corresponding to the address of the expansion area comes from the second type storage medium; and the second type of storage medium has a lower access latency than the first type of storage medium.
According to one of the first to seventh methods for accessing an extended address space of a storage device in the second aspect of the present application, there is provided a method for accessing an extended address space of a storage device in the eighth aspect of the present application, further comprising: responding to the command of acquiring the read expansion area, and distributing one or more cache units for the command of reading the expansion area; wherein the read mirror command is processed using the one or more cache units.
According to an eighth method for accessing an extended address space of a storage device of the second aspect of the present application, there is provided a ninth method for accessing an extended address space of a storage device of the second aspect of the present application, further comprising: releasing the one or more second cache units in response to the read data from the first physical address being correct.
According to an eighth method for accessing an extended address space of a storage device in the second aspect of the present application, there is provided a tenth method for accessing an extended address space of a storage device in the second aspect of the present application, further comprising: and releasing the one or more second cache units in response to the data read from the second physical address being correct.
According to one of the eighth to tenth methods of accessing an extended address space of a memory device of the second aspect of the present application, there is provided the eleventh method of accessing an extended address space of a memory device of the second aspect of the present application, further comprising: in response to fetching the read command, one or more cache locations are allocated for the read command.
According to a third aspect of the present application, there is provided a first storage device according to the third aspect of the present application, comprising a control section and an NVM storage medium; the control unit executes one of the method of accessing an extended address space of a storage device according to the first aspect of the present application and the method of accessing an extended space of a storage device according to the second aspect of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a block diagram of a solid-state storage device in the related art;
FIG. 2A illustrates a diagram of address space mapping according to an embodiment of the present application;
FIG. 2B illustrates a schematic diagram of address space mapping according to yet another embodiment of the present application;
FIG. 3 is a block diagram of a storage device processing a write extent command according to an embodiment of the present application;
FIG. 4 is a flow diagram of processing a write extent command according to an embodiment of the application;
FIG. 5 is a block diagram of a storage device processing a read extent command according to an embodiment of the present application; and
FIG. 6 is a flow diagram of processing a read extent command according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments obtained by a person skilled in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
FIG. 2A shows a schematic diagram of address space mapping according to an embodiment of the present application.
According to an embodiment of the application, the storage device provides a logical address space 210 to a host or user. The user accesses the logical address space 210 provided by the storage device based on the logical address.
The storage device maintains the LTA space 220. The elements of the LTA space are referred to as LTA addresses. According to the FTL table of the storage device in the embodiment of the present application, the mapping relationship between the LTA address and the physical address is recorded.
The LTA space includes a plurality of zones. In FIG. 2A, the LTA space 220 includes a logical address area 222, an extension area 224, and a mirror area 226. By way of example, the logical address space 210 is mapped directly to the logical address region 222 of the LTA space 220, such that the logical address space 210 has the same number of elements as the logical address region 222. Optionally, the elements of the logical address space 210 have the same values as the corresponding elements of the logical address region 222.
The extent 224 of the LTA space 220 is used to record other data of the storage device, such as s.m.a.r.t. information, metadata internal to the storage device, a working log of the storage device, and the like. S.m.a.r.t. information 212 is mapped to an extent 224 and log area 214 is also mapped to extent 224. The address space representing the s.m.a.r.t. information 212 and the log area 214 is referred to as an extended address space.
As an example, the host accesses the s.m.a.r.t. information, and the storage device obtains the address of the corresponding extension area 224 according to the accessed s.m.a.r.t. information. The log area 214 records metadata internal to the storage device and/or a working log of the storage device for use by the firmware of the storage device. Optionally, the storage device also maintains s.m.a.r.t. information or a mapping of the log area 214 to the extension area 224. Thus, the respective addresses of the s.m.a.r.t. Information and log area, as well as the address of the extension area 224, may correspond to different data unit sizes. For example, the data units of the s.m.a.r.t. information access by byte, daily area have a size of 512 bytes or 1KB, while the LTA address has a size of, for example, 4 KB. Still alternatively, the firmware of the storage device may access metadata and/or a working log of the storage device directly using the LTA address, thereby eliminating address mapping of the log area 214 to the extent area 224. Alternatively, the address of the log area plus a specified offset (e.g., an offset equal to the logical address area size) results in the LTA address of the extension area 224.
According to embodiments of the present application, mirrored region 226 provides a mirror or copy of extension region 224. The LTA address of the mirror area 226 corresponds one-to-one to the LTA address of the extension area 224. The LTA address of the mirror area 226 is obtained by, for example, the LTA address of the extension area 224, plus a specified offset (e.g., an offset equal to the extension area size).
The host or storage device firmware that accesses the s.m.a.r.t. information, metadata internal to the storage device, or a working log of the storage device need not be aware of the storage of the mirrored region 226. Such that the extension area is used only to access s.m.a.r.t. information, metadata internal to the storage device, or a working log of the storage device, while the mirror area 226 is used by internal or underlying services of the storage device to provide mirroring services for the extension area 224.
In fig. 2A, "0" of the LTA space 220 indicates a start address of the LTA space 220, and "LastLTA" indicates an end address of the LTA space.
According to the storage device of the embodiment of the present application, the LTA space is mapped to the physical storage space 230 provided by the NVM storage medium through the FTL (flash translation layer) table. The address to access the NVM storage media is referred to as the physical address.
The capacity of the physical storage space 230 is typically greater than the capacity of the LTA space. The FTL (flash translation layer) applies garbage collection, wear leveling, etc. techniques as needed to manage the mapping of LTA space 220 to physical memory space 230.
FIG. 2B illustrates a diagram of address space mapping according to yet another embodiment of the present application.
In contrast to fig. 2A, in the embodiment shown in fig. 2B, the LTA space is mapped to different kinds of physical storage space provided by the NVM storage medium or to different kinds of NVM storage medium through FTL table according to different areas of the LTA space. By way of example, in fig. 2B, the logical address area 222 of the LTA space is mapped to a TLC (cable Level Cell) type NVM storage medium, and the extension area 224 and the mirror area 226 are mapped to an SLC (Single Level Cell) type NVM storage medium. TLC type of NVM storage media has lower cost per capacity, while SLC type of NVM storage media has higher reliability and lower access latency.
Still alternatively, different areas of LTA space are served by other types of storage media. For example, logical address area 222 is mapped to NAND flash memory, while extension area 224 and mirror area 226 are mapped to byte-addressable non-volatile storage media.
Alternatively, or in addition, the FTL (flash translation layer) performs garbage collection and/or wear leveling on the logical address area 222, the expansion area 224 and/or the mirror area 226, respectively. Still alternatively, the FTL (flash translation layer) performs garbage collection and/or wear leveling only on the logical address area 222, and does not perform garbage collection and/or wear leveling on the extension area 224 and the mirror area 226.
FIG. 3 is a block diagram of a storage device processing a write extent command according to an embodiment of the application.
The control section shown in fig. 3 includes a host interface 310, a BU allocation unit 320, a command processing unit 330, a command completion unit 340, and a media interface 350 for accessing the NVM chip. The host interface 310, BU allocation unit 320, command processing unit 330, command completion unit 340, and media interface 350 may each be implemented by a CPU, dedicated hardware, or a combination thereof.
The command to write to the extent may come from a command from the host, for example, to update s.m.a.r.t. information, or from an access request by the firmware to update metadata of the storage device and/or a working log of the storage device. The host interface 310 provides host commands to the BU allocation unit by receiving the commands from the host through the host interface 310. And an access request of the storage device firmware is also sent to the BU allocation unit for processing of the write extent command. A host command to write data to an extent or an access request to update metadata of a storage device and/or a work log of the storage device is collectively referred to as a write extent command. Commands provided by the host to the storage device to write data to the logical address space are referred to as write commands.
According to an embodiment of the present application, the storage device includes a plurality of Buffer Units (BU) 362. The buffer unit is used for accommodating data to be written into the storage device or data read out from the storage device.
The BU allocation unit 320 manages use of a buffer unit and allocates the buffer unit for a write command or a write extent command. By way of example, the cache units have a specified size. One or more cache units are allocated for each write command or write extent command to accommodate data to be written to the storage device.
Taking the write extent command as an example, the write extent command to which the buffer unit is allocated is added to the command set 360. By setting the command set 360, the operations of the bu allocation unit 320 and the command processing unit 330 do not have to occur in synchronization. After adding a write extent command (or write command, write mirror command) to the command set, the BU allocation unit continues to process other commands.
The command processing unit 330 retrieves, for example, a write extent command from the command set 360 and instructs the media interface 350 to issue one or more programming operations to the NVM chip to store the data indicated by the write extent command in the NVM chip. Optionally, command processing unit 330 also assigns a physical address for data to be written to the NVM chip. By way of example, command processing unit 330 sequentially assigns physical addresses of the NVM chips for data in an append manner. Still by way of example, for a write extent command, command processing unit 330 allocates a physical address of a designated region of the NVM chip (e.g., a physical address region configured in SLC mode) for the data, or allocates a physical address of an SLC type storage medium for the data.
The media interface 350 provides the results of the programming operation of the NVM chip to the command completion unit 340. In response to the successful execution of the program operation, the command completion unit 340 records a correspondence relationship between an LTA address accessed by a command (write command, write extent command, or write mirror command) corresponding to the program operation and a physical address accessed by the program operation in the FTL table 364.
According to an embodiment of the present application, the command completion unit 340 further identifies in which area of the LTA space the LTA address accessed by the command (write command, write extent command, or write mirror area command) corresponding to the program operation whose processing is completed is located. If a command accesses an extension area of the LTA space (see fig. 2A, 2B, extension area 224), meaning the command is a write extension area command, the command completion unit 340 generates a write mirror area (see fig. 2A, 2B, mirror area 226) command from the write extension area command. And the generated mirror area writing command is used for rewriting the data of the command for writing the expansion area into the mirror area. For example, the LTA address of the write mirror area command is obtained by adding the LTA address of the write extension area command to the size of the extension area. The command completion unit 340 provides the write mirror area command to, for example, the BU allocation unit 320.
Alternatively, in response to receiving the write mirror area command from the command completion unit 340, the BU allocation unit 320 reuses the buffer unit previously allocated to the write extension area command, allocates the buffer unit to the write mirror area command corresponding to the write extension area command, updates the LTA address of the write extension area command corresponding to the buffer unit to the LTA address of the write mirror area command, and does not change the data to be written to the extension area recorded in the buffer unit to rewrite the same data to the mirror area.
Still alternatively, in response to completion of the write extent command processing, the command completion unit 340 instructs to release the cache unit occupied by the write extent command. And the BU distribution unit redistributes the buffer unit for the write mirror area command corresponding to the write extension area command.
Alternatively, the command completion unit 340 generates a corresponding write mirror area command without passing through the BU allocation unit 320 in response to the write extension area command processing being completed. The command completion unit 340 obtains the LTA address of the write mirror command from the LTA address of the write extent command, and uses the buffer unit allocated to the write extent command as the buffer unit of the write mirror command. The generated write mirror area command is also added directly to the command set 360.
If the command completion unit 340 recognizes that the LTA address accessed by the command (write command, write extent command, or write mirror command) corresponding to the processed and processed program operation is located in the mirror area, it means that the command is a write mirror command. In response to the write mirror area command processing completion, the command completion unit 340 instructs the BU allocation unit 320 to release the data unit allocated to the write mirror area command.
If the command completion unit 340 recognizes that the LTA address accessed by the command (write command, write extent command, or write mirror area command) corresponding to the processed and processed program operation is located in the logical address area, it means that the command is a write command. In response to the write command processing being completed, command completion unit 340 instructs BU allocation unit 320 to release the data unit allocated to the write command.
Therefore, for the command of writing the extension area generated by the host or the firmware, the embodiment according to the application not only processes the command of writing the extension area, but also generates the command of writing the mirror image area according to the command of writing the extension area so as to write mirror image data which is used as backup of the extension area into the mirror image area. In the FTL table, the corresponding relationship between the LTA address obtained according to the command for writing the extension area and the physical address is recorded, and the corresponding relationship between the LTA address obtained according to the command for writing the mirror area and the physical address is also recorded. And the LTA address of the expansion area and the LTA address of the corresponding mirror image area have a specified mapping relation, so that the LTA address of the mirror image area is obtained according to the LTA address of the expansion area. Therefore, in response to failure in reading data from the extension area, the storage device according to the embodiment of the present application obtains a corresponding mirror area address from the address of the extension area to be read, and reads data from the mirror area address as a response to a command for reading the extension area.
According to the embodiment of the application, all parts of the storage device process the write command, the write expansion area command and the write mirror area command in the same way, and the complexity of the storage device is also reduced.
Alternatively or additionally, if command completion unit 340 identifies that the processing of the completed programming operation failed, command completion unit 340 instructs BU allocation unit 320 to reprocess the command corresponding to the programming operation, regardless of which region of the LTA address space the write command corresponding to the programming operation accessed. And optionally, reusing the buffer unit allocated to the command corresponding to the programming operation by the BU allocation unit.
FIG. 4 is a flow diagram of processing a write extent command according to an embodiment of the application.
The storage device obtains a write extent command (410). The write extent command is from, for example, a host updating s.m.a.r.t. information, or a firmware updating metadata of the storage device and/or a working log of the storage device.
One or more buffer units (420) are allocated for the write extent command to temporarily hold data to be written by the write extent command. For example, the buffer unit is allocated for the write extent command by the BU allocation unit 320 shown in fig. 3. Optionally, if the number of available buffer units of the storage device is not enough to accommodate the data to be written by the write extent command, the processing of the write extent command is suspended until a sufficient number of buffer units are available for allocation to the write extent command.
The write extent command with the allocated cache unit is added to a command set (e.g., command set 360 of FIG. 3) (430).
Periodically or in response to the command set being added with a command, a command processing unit (e.g., command processing unit 330 of FIG. 3) retrieves the command from the command set and sends a program operation to the NVM chip according to the command (440). Optionally, the command processing unit assigns a physical address to the data unit of the command obtained from the command set, and instructs, for example, the media interface (see fig. 3, media interface 350) to send a program operation to the NVM chip to write the data of the buffer unit to the assigned physical address of the NVM chip. Optionally, the command processing unit further identifies which region of the LTA space the command acquired from the command set accesses. For a command to access an extension area or a mirror area, a physical address of a designated area is allocated. The designated area is a storage medium such as an SLC type NVM chip, a nonvolatile memory, a phase change memory, a resistance change memory, or the like. For commands to access the logical address region, the physical address of the NVM chip, such as TLC type, is assigned.
In response to one or more programming operations corresponding to the write extent command being processed, the FTL table is updated (450). The correspondence relationship of the LTA address of the extension area accessed by the write extension area command and the allocated physical address for the programming operation is recorded in the FTL table. In some examples, the write expand command accesses a plurality of LTA addresses (e.g., each LTA address corresponds to one of the cache units), and also records the corresponding relationship between each LTA address and the physical address of the write expand command in the FTL table.
Whether the command is a write extent expand command, a write command, or a write mirror command is identified, depending on, for example, whether the LTA address of the command access is located in an extent or a mirror (460). It will be appreciated that in FIG. 5, for purposes of clarity, the term write extent command is used in the description of steps 410-460. And for the command processing unit 330 or the command completion unit 340, for example, it recognizes that the command is a write command, a write extent command, or a write mirror command by, for example, recognizing the value of the LTA address accessed by the command or the identification carried in the command.
In step 460, for the command of writing the extension area, a corresponding command of writing the mirror area is generated according to the command of writing the extension area, so as to copy the data written in the extension area to the mirror area. The generated write mirror area command indicates the same cache unit as the write extension area command and indicates to write the data of the cache unit into the mirror area address. The corresponding mirror area address is obtained by adding, for example, a specified offset value to the extension area address (480). And returning to step 430, adding the generated write mirror area command to the command set by borrowing the step of adding the write extension area command to the command set.
In step 460, the buffer location allocated for the write mirror command, or alternatively, the write command, is released in response to the write mirror command or write command processing being completed (470).
FIG. 5 is a block diagram of a storage device processing a read extent command according to an embodiment of the application.
The control section shown in fig. 5 includes a host interface 510, a BU assigning unit 520, an address translation unit 525, a command processing unit 530, a command completion unit 540, and a media interface 550, which may be implemented by a CPU, dedicated hardware, or a combination thereof.
The command to read the extent may come from a command from the host to access s.m.a.r.t. information, for example, or from an access request by firmware to access metadata of the storage device and/or a working log of the storage device.
A command from the host is received through the host interface 510, and the host interface 510 provides the host command to the BU dispensing unit 520. And an access request of the storage device firmware is also sent to the BU allocation unit 520 to perform the processing of the read extent command. Host commands to read data from the extents or access requests to obtain metadata for the storage device and/or a working log for the storage device are collectively referred to as read extent commands. Commands that are provided by the host to the storage device to retrieve data from the logical address space are referred to as read commands.
The storage apparatus includes a plurality of Buffer Units (BU) 562.BU allocation unit 520 manages the use of buffer units and allocates buffer units for read commands or read extent commands.
The read extent command indicates the LTA address to be accessed. Optionally, to read the s.m.a.r.t. information, the metadata of the storage device, and/or the working log of the storage device, the LTA address to be accessed is also obtained according to the read object. In processing the read extent command, the FTL table 564 is queried by the address translation unit 525 to translate the LTA address to a physical address. Similarly, to handle the read mirror area address, the LTA address is also translated to a physical address by the address translation unit 525. To process the read command, optionally, the LTA address is derived from the logical address indicated by the read command, and is converted into a physical address by the address conversion unit 525. In some cases, the logical address is the same as the LTA address.
Continuing with FIG. 5, taking the read extent command as an example, the read extent command that is assigned a cache location and gets a corresponding physical address is added to the command set 560.
The command processing unit 530 retrieves, for example, a read extension command from the command set 560, and instructs the media interface 550 to issue one or more read operations to the NVM chip according to the physical address to read data indicated by the read extension command from the NVM chip. Data read from the NVM chip is buffered in a buffer unit allocated to the read extent command.
By way of example, for a read extent command, the physical address looked up from the FTL is the physical address of a designated region of the NVM chip (e.g., a physical address region configured in SLC mode), or the physical address of an SLC type storage medium.
The media interface 550 provides the results of the read operation of the NVM chip to the command completion unit 540. In response to successful execution of the read operation, command completion unit 540 instructs BU allocation unit 520 to release the buffer unit allocated for the command (read command, read extent command, or read mirror command) corresponding to the read operation.
In response to a failure in the execution of the read operation, the command completion unit 540 further identifies in which area of the LTA space the LTA address accessed by the command (read command, read-extended area command, or read-mirror area command) corresponding to the read operation that is completed is located, and performs different subsequent processes. If a command accesses an extent of the LTA space (see FIGS. 2A, 2B, extent 224), meaning the command is a read extent command, command completion unit 540 generates a read mirror (see FIGS. 2A, 2B, mirror 226) command based on the read extent command. And generating a read mirror area command for attempting to read data to be read by the read extension area command again from the mirror area. For example, the LTA address of the read mirror command is obtained by adding the LTA address of the read extension command to the size of the extension. And the command completion unit 540 provides the read mirror area command to the BU allocation unit 520 to be processed.
Optionally, the BU allocation unit 320 reuses the buffer unit previously allocated to the read extent command, allocates the reused buffer unit to the read mirror area command corresponding to the read extent command, and updates the LTA address of the read extent command corresponding to the buffer unit to the LTA address of the read mirror area command.
Still alternatively, in response to a processing failure of the read extent command, the command completing unit 540 instructs to release the cache unit occupied by the read extent command. And BU allocation unit 520 reallocates the buffer units for the read mirror region commands corresponding to the read extension region commands. The BU allocation unit 520 also instructs the address translation unit 525 to obtain the physical address corresponding to the LTA address of the read mirror command.
Still alternatively, in response to a failure in processing the command to read the extended area, the command completion unit 540 generates a LTA address of the mirror area corresponding to the LTA address of the extended area according to the LTA address of the command to read the extended area, and directly instructs the address translation unit 525 to obtain the physical address according to the LTA address of the mirror area. The command completion unit 540 directly generates a read mirror area command from the mirror area LTA address and the corresponding physical address and adds to the command set 560 without going through the BU allocation unit 520.
If the command completion unit 540 recognizes that the LTA address accessed by the command (read command, read extent command, or read mirror command) corresponding to the processed and processed read operation is located in the mirror area, it means that the command is a read mirror command. In response to a read mirror region command processing failure, optionally, a read extension region command processing failure is indicated to the host or firmware that generated the corresponding read extension region command.
Therefore, for the command for reading the extension area generated by the host or the firmware, if the read operation corresponding to the command for reading the extension area fails, the embodiment according to the application generates the command for reading the mirror area according to the command for reading the extension area, so as to read the mirror data as backup for the extension area from the mirror area as a response to the command for reading the extension area.
Optionally, for a read command generated by the host or the firmware, if the read operation corresponding to the read command fails to be processed, another error processing procedure is also executed. For example, the command processing unit 530 instructs the media interface to initiate a Read-redo (Read-Retry) command or a soft decoding process of the error decoding unit; the command completion unit 540 initiates a data recovery flow using, for example, a RAID mechanism. Still optionally, for the command of reading the extension area or the command of reading the mirror area, the other error handling procedures are also executed if the corresponding read operation fails.
FIG. 6 is a flow diagram of processing a read extent command according to an embodiment of the present application.
The storage device obtains a read extent command (610). The read extent command comes from, for example, a host accessing s.m.a.r.t. information, or firmware reading metadata of the storage device and/or a working log of the storage device.
One or more buffer units (620) are allocated for read extent commands to temporarily hold data read from the NVM chip in response to the read extent command. For example, the buffer unit is allocated for the read extent command by the BU allocation unit 320 shown in fig. 3.
According to the LTA address indicated by the read extent command, the corresponding physical address is obtained through, for example, an FTL table (630).
The read extent command with the allocated cache unit is added to a command set (e.g., command set 360 of FIG. 3) (640). The read extent command in the command set carries the LTA address to be accessed and the physical address corresponding to the LTA address.
Periodically or in response to the command set being added with a command, a command processing unit (e.g., command processing unit 330 of FIG. 3) retrieves the command from the command set and sends a read operation to the NVM chip according to the command (650).
In response to one or more read operations corresponding to the read extent command being processed, it is identified whether the read data is correct (660). For example, by error correction decoding the read data to identify whether the read data is correct. If the read data is correct (no errors are present or can be corrected correctly), the read data is used as the result of the processing of the read extent command (675). And also freeing one or more cache locations allocated to the read extent command.
If the read data cannot be decoded to obtain correct data by error correction decoding, step 660 further identifies whether the LTA address accessed by the command is located in an extension area or a mirror area (670), so as to identify whether the command is a read command, a read extension area command, or a read mirror area command. It is to be understood that steps 610-660 and 675 of FIG. 6 are also applicable to processing read commands that read the logical address space. In step 670, it is necessary to recognize whether the command is a read command, a read extension command, or a read mirror command by, for example, recognizing the value of the LTA address accessed by the command or the identification carried in the command.
In step 680, for the read extent command, a corresponding read mirror region command is also generated according to the read extent command, so as to try to obtain the correct data to be read by the read extent command. The LTA address of the mirror area is obtained by, for example, adding the size of the extension area according to the LTA address of the read extension area command. Then, returning to step 630, the physical address corresponding to the LTA address of the mirror area is obtained for the newly generated command to read the mirror area, and the subsequent steps such as step 640 are continuously performed.
If the command is a read mirror area step in step 670, then step 690 is entered for error handling. For example, the requestor of the read extent command is indicated that the data has been corrupted and cannot be recovered. And also freeing one or more cache locations allocated to the read extent command. Optionally, at step 690, a series of further data recovery processes are performed.
It is to be understood that although in the embodiments according to fig. 3 and 5 respective operations performed by the host interface, the BU assigning unit, the command processing unit, the command completion unit, the media interface, and/or the address translation unit are provided, these operations may be performed by different components, and may also be performed by one or more program segments running on the CPU.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method of accessing an extended address space of a storage device, comprising:
obtaining a write extended area command for accessing an extended address space, wherein the extended address space is different from a logical address space;
writing data corresponding to a write expansion area command into a first physical address, and recording the corresponding relation between an LTA address accessed by the write expansion area command and the first physical address in an FTL (flash translation layer) table;
generating a mirror image area writing command according to the extended area writing command;
writing data corresponding to the command of the writing mirror image area into a second physical address, and recording the corresponding relation between the LTA address accessed by the command of the writing mirror image area and the second physical address in an FTL table; and
indicating that the write extent command processing is complete.
2. The method of claim 1, further comprising:
acquiring a write command for accessing a logical address space;
writing data corresponding to the write command into a third physical address, and recording the corresponding relation between the LTA address accessed by the write command and the third physical address in an FTL table; and
indicating that the write command processing is complete.
3. The method of claim 2, wherein
The extended address space is mapped to an extension area of the LTA address space; wherein the firmware of the storage device accesses the extension area directly according to the LTA address.
4. A method according to any one of claims 1 to 3, wherein
In response to the command for obtaining the write expansion area, mapping an address for accessing an expansion address space to a first LTA address of an expansion area, and allocating a corresponding first physical address for the first LTA address indicated by the command for writing the expansion area;
and calculating to obtain a second LTA address according to the first LTA address, generating the write mirror area command based on the second LTA address, and allocating a corresponding second physical address to the second LTA address, wherein the second LTA address belongs to a mirror area of an LTA address space.
5. The method of claim 4, wherein
The second LTA address indicated by the write mirror area command is obtained based on the first LTA address indicated by the write extension area command plus a specified offset.
6. The method according to any one of claims 3 to 6, wherein
The logical address space is mapped to a logical address area of the LTA space; wherein the logical address area is mapped to a first type of storage medium and the extension area is mapped to a second type of storage medium according to the FTL table, wherein the second type of storage medium has a lower access latency than the first type of storage medium.
7. A method of accessing an extended address space of a storage device, comprising:
obtaining a read extended area command for accessing an extended address space, wherein the extended address space is different from a logical address space;
inquiring an FTL (flash translation layer) table according to a first address of a read expansion area command to obtain a first physical address, and reading data from the first physical address;
in response to an error in reading data from the first physical address;
generating a mirror image area reading command;
inquiring an FTL table according to a second address of the mirror image area reading command to obtain a second physical address, and reading data from the second physical address;
and responding to the read expansion area command by reading the data from the second physical address.
8. The method of claim 7, wherein
Responding to the command of acquiring the read expansion area, and distributing one or more cache units for the command of reading the expansion area; wherein the read mirror command is processed using the one or more cache units.
9. The method of claim 8, further comprising:
responding to the failure of the read operation corresponding to the read expansion area command, reusing the cache unit allocated to the read expansion area command, allocating the reused cache unit to the read mirror area command corresponding to the read expansion area command, and updating the LTA address of the read expansion area command corresponding to the cache unit to the LTA address indicated by the read mirror area command.
10. A storage device includes a control section and an NVM storage medium;
the control unit performs the method according to one of claims 1 to 9.
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| US6116768A (en) * | 1993-11-30 | 2000-09-12 | Texas Instruments Incorporated | Three input arithmetic logic unit with barrel rotator |
| CN100557716C (en) * | 1999-04-27 | 2009-11-04 | 松下电器产业株式会社 | Semiconductor memory card and control method thereof |
| JP4301849B2 (en) * | 2003-03-31 | 2009-07-22 | 株式会社日立製作所 | Information processing method and its execution system, its processing program, disaster recovery method and system, storage device for executing the processing, and its control processing method |
| JP2009049208A (en) * | 2007-08-20 | 2009-03-05 | Spansion Llc | Semiconductor device and method for manufacturing the same |
| US8806101B2 (en) * | 2008-12-30 | 2014-08-12 | Intel Corporation | Metaphysical address space for holding lossy metadata in hardware |
| EP3696676B1 (en) * | 2009-10-09 | 2023-12-06 | Violin Systems LLC | Memory system with multiple striping of raid groups and method for performing the same |
| CN103597451B (en) * | 2011-03-31 | 2017-06-13 | 英特尔公司 | Memory image and redundancy generation for high availability |
| US8539008B2 (en) * | 2011-04-29 | 2013-09-17 | Netapp, Inc. | Extent-based storage architecture |
| CN102662607B (en) * | 2012-03-29 | 2014-10-29 | 华中科技大学 | RAID6 level mixed disk array, and method for accelerating performance and improving reliability |
| CN103092727B (en) * | 2013-01-18 | 2015-08-26 | 大唐移动通信设备有限公司 | Data error-correcting method in flash storage medium and device |
| CN203191967U (en) * | 2013-03-11 | 2013-09-11 | 北京忆恒创源科技有限公司 | Computer system |
| US10078269B2 (en) * | 2015-10-02 | 2018-09-18 | Nikon Corporation | Array of encoders for alignment measurement |
| CN107797760B (en) * | 2016-09-05 | 2021-06-11 | 北京忆恒创源科技有限公司 | Method and device for accessing cache information and solid-state drive |
| CN106445691A (en) * | 2016-11-25 | 2017-02-22 | 郑州云海信息技术有限公司 | Memory optimization method oriented to virtual cloud computing platform |
| CN108241468B (en) * | 2016-12-23 | 2021-12-07 | 北京忆芯科技有限公司 | IO command processing method and solid-state storage device |
| CN108037932B (en) * | 2017-12-07 | 2021-01-15 | 北京兆易创新科技股份有限公司 | SPI-NAND configuration file acquisition method and device |
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