TWI651646B - Data storage device and task sequencing method - Google Patents

Data storage device and task sequencing method

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Publication number
TWI651646B
TWI651646B TW106114698A TW106114698A TWI651646B TW I651646 B TWI651646 B TW I651646B TW 106114698 A TW106114698 A TW 106114698A TW 106114698 A TW106114698 A TW 106114698A TW I651646 B TWI651646 B TW I651646B
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TW
Taiwan
Prior art keywords
task
tasks
data storage
executed
storage device
Prior art date
Application number
TW106114698A
Other languages
Chinese (zh)
Other versions
TW201738730A (en
Inventor
謝兆魁
Original Assignee
慧榮科技股份有限公司
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Priority to TW106114698A priority Critical patent/TWI651646B/en
Publication of TW201738730A publication Critical patent/TW201738730A/en
Application granted granted Critical
Publication of TWI651646B publication Critical patent/TWI651646B/en

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Abstract

A data storage device and a task sorting method thereof. The data storage device includes a data storage medium and a control unit. The control unit is configured to electrically connect and control the data storage medium, and switch to the command queue mode to receive the queue instruction including the at least one task sent by the host, and determine whether the task included in the queue instruction is to be executed. The task sorts the tasks to be executed and selectively responds to the queue status information to the host. The queue status information includes the number of tasks corresponding to the task to be executed and the task number corresponding to the sorted task to be executed.

Description

Data storage device and task scheduling method thereof

The present invention relates to a related art structure, and more particularly to a data storage device, a control unit for controlling the data storage device, and a task sequencing method.

In the prior art, a host (such as a computer or a mobile phone) sends a specific command to a data storage device (such as a flash memory or the like) electrically connected thereto according to an industrial specification, and the data storage device responds to the command. The reply host has which tasks are ready to be executed, and then the host will then send an access command to notify the data storage device that it is going to read or write.

However, although the prior art data storage device can reply to a plurality of tasks to be executed to the host, the host cannot judge the execution order of the tasks to be executed. For example, a data storage device can perform a certain task efficiently, but the host actually requires the data storage device to perform another task, so that the data storage device must rearrange the appropriate system resources to perform the task. Therefore, how to enable the host and the data storage device to communicate more efficiently and arrange the execution of the task is a subject that those skilled in the art would like to explore.

The present invention provides a data storage device that can communicate with a host more efficiently.

The present invention further provides a control unit that enables the host to more efficiently access data stored by the data storage device.

The present invention further provides a task ordering method suitable for the above data storage device.

A data storage device provided by the present invention includes a data storage medium and a control unit. The control unit is configured to electrically connect and control the data storage medium, and switch to the command queue mode to receive the queue instruction including the at least one task sent by the host, and determine whether the task included in the queue instruction is to be executed. The task sorts the tasks to be executed and selectively responds to the queue status information to the host. The queue status information includes the number of tasks corresponding to the task to be executed and the task number corresponding to the sorted task to be executed.

A control unit further proposed by the present invention includes control logic, interface logic, and a microprocessor. The microprocessor is electrically connected to the control logic and the interface logic, and is configured to access the data in the data storage medium through the control logic, and is further configured to receive, by the interface logic, the queue instruction sent by the host, the queue instruction includes at least one task, and Determining whether the task included in the queue instruction is a task to be executed, and sorting the task to be executed, and selectively replying the queue status information to the host, and the queue status information includes the number of tasks corresponding to the task to be executed and corresponding The task number to the task to be executed after sorting.

The invention further provides a task sorting method suitable for a data storage device, comprising the steps of: switching to an instruction queue mode; receiving a queue instruction from a host, the queue instruction comprising at least one task; The tasks included; determine whether the tasks listed are tasks to be executed; rank the tasks to be executed; and selectively reply to the queue status The information to the host, the queue status information includes the number of tasks corresponding to the task to be executed and the task number corresponding to the sorted task to be executed.

The data storage device of the present invention can respond to the host's queue command to reply to the host including the number of tasks to be executed and the queue status information of the task number, so that the host can determine how many tasks to be executed. And the tasks to be executed are sequentially executed according to the order of sorting, thereby improving the efficiency of task execution.

100‧‧‧Host

200‧‧‧ data storage device

210‧‧‧Control unit

220‧‧‧Data storage media

212‧‧‧Interface logic

214‧‧‧Microprocessor

216‧‧‧Control logic

230‧‧‧ Status information

CMD44, CMD45, CMD13, CMD46, CMD47‧‧‧ instructions

Steps S501, S502, S503, S504, S505, S506, S507‧‧

1 is a schematic diagram of a data storage device and a host electrically connected thereto according to an embodiment of the present invention.

Figure 2 is a schematic diagram of a general instruction queue process.

FIG. 3 is a schematic structural diagram of data of queue status information according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a data structure of a conventional queue state information.

FIG. 5 is a flowchart of a task scheduling method according to an embodiment of the present invention.

1 is a schematic diagram of a data storage device and a host electrically connected thereto according to an embodiment of the present invention. As shown in FIG. 1 , the host 100 is electrically connected to the data storage device 200 . The host 100 is implemented, for example, by a computer, a mobile phone, a tablet, a camera, or other handheld electronic device with computing functions. The data storage device 200 includes a control unit 210 and a data storage medium 220. Control unit 210 includes interface logic 212, microprocessor 214, and control logic 216. The microprocessor 214 is electrically coupled to the interface logic 212 and the control logic 216. The microprocessor 214 is configured to access the data in the data storage medium 220 through the control logic 216. The microprocessor 214 is configured to receive the queue command sent by the host 100 through the interface logic 212, and respond to the queue status information of the present invention to the master according to the received queue command. The machine 100 notifies the host 100 to access the data stored in the data storage medium 220 according to the task order specified in the queue status information of the present invention. The data storage medium 220 is implemented by non-volatile memory, such as flash memory, magnetoresistive RAM, and ferroelectric RAM. Such as a memory device with long-term data storage to achieve. The interface logic 212 is a SATA interface (Serial Advanced Technology Attachment), a Universal Serial Bus (USB), a Peripheral Component Interconnect Express (PCI Express), and a non-volatile memory storage device (NVMe). , Non-Volatile Memory Express), Universal Flash Storage (UFS, Universal Flash Storage), Embedded Multimedia Memory Card (eMMC), or SDIO interface (Secure Digital Input/Output) standard interface logic.

The following description of the present invention will be made with eMMC version 5.1 and issue date of February 2015, but is not limited thereto. The eMMC can support a queue of up to 32 data transfer tasks, wherein the data transfer task (or simply a task) can correspond to a data read command or a data write command. Figure 2 is a schematic diagram of a general instruction queue process. After enabling or switching to the command queue mode, the host 100 sends a queue command to transmit a plurality of tasks to the data storage device 200 for queue. The queue instruction includes a 44th type instruction (Command 44) and a 45th type instruction (Command 45), wherein the 44th type instruction is a queued instruction parameter, and the content includes: a number of data blocks (blocks), a task number, and a data. Transmission direction, priority, etc., wherein the task numbers are not repeated; the 45th type of instruction is a queued instruction address, and the content thereof is a logical data block address (LBA, Logical Block Address) corresponding to the task. After the task is queued, the host 100 sends a Type 13 command (Command 13) to query the status of the task queue, and then the data storage device 200 replies to the queue status information 230 to the host 100. Optionally, the queue status information 230 is preferably the status information of the present invention, and may also be the traditional status information. The data storage device 200 is based on the 13th. The requirements of the class instructions determine the contents of the queue status information 230. The queue status information of the present invention provides a better (or suggested) execution order of the tasks to be executed in addition to providing which tasks in the queue are ready for execution tasks, and the data storage device 200 This order to perform the tasks to be performed will be more efficient. Upon receipt of the queue status information 230, the host 100 may send a 46th type of command (Command 46) or a 47th type of command (Command 47) to the data storage device 200 to perform the task to be executed in the queue.

FIG. 3 is a schematic structural diagram of data of queue status information according to an embodiment of the present invention. As shown in FIG. 3, the queue state information of the present invention includes 32 bits arranged in order from bit 0 to bit 31. The host 100 sends a Type 13 command to obtain the queue status information of the present invention that is replied to by the data storage device 200. As shown in FIG. 4, the data structure of the traditional queue state information is one bit to indicate whether the corresponding task is a task to be executed, for example, if task 0, task 6, task 15, and task 21 are To be executed, in the traditional data structure, bit 0, bit 6, bit 15, and bit 21 are represented by a binary one, and the host 100 can know that these are tasks to be executed. For other tasks, the corresponding bit is represented by a binary zero.

However, the traditional queue state information cannot indicate the execution order of the tasks to be executed, and the execution sequence may cause the data storage device 200 to take longer and more system resources to complete the task execution, which will result in System performance is low. Different from the traditional queue state information, the queue state information of the present invention includes the number of tasks of the task to be executed and the task numbers of the plurality of tasks to be executed arranged according to the preferred task execution order, and the task to be executed The number and the task number of the task to be executed are each represented by a plurality of bits. Referring to FIG. 3, in this embodiment, the number of tasks of the task to be executed is represented by 3 bits, such as bits 0~2 of 32 bits, and the minimum number of tasks in this embodiment is 0. The maximum value is 7. For example, three bits, such as bit 0~2, are used to indicate that the number of tasks to be executed is four, and the task numbers of each task to be executed are each represented by 5 bits and are sequentially arranged from bit 4. example For example, if the data storage device 200 is to inform the host 100 that the preferred task execution order is four tasks to be executed, such as tasks 21, 6, 15, 0, etc., 5 bits such as bits 4-8 are used to represent The first task to be executed is task 21, and 5 bits such as bits 9~13 are used to indicate that the second task to be executed is task 6, and five bits such as bits 14~18 are used to represent The third task to be executed is task 15, and 5 bits such as bits 19~23 are used to indicate that the fourth task to be executed is task 0.

Specifically, the queue status information of the present invention designed according to the above data structure can provide up to five task numbers of tasks to be executed, which is limited by the length of the queue status information 230 being 32 bits. Assuming that the data storage device 200 can reply to the plurality of queue status information of the present invention to the host 100, all tasks to be executed can be sequentially provided to the host 100 according to their preferred execution order. Assuming that the length of the queue status information 230 can be extended to 64 bits or 128 bits, in accordance with the spirit of the present invention, the queue status information of the present invention will provide task numbers for more than five tasks to be executed. Similarly, if 4 bits are reserved instead of 3 bits, the number of tasks representing the task to be executed can be up to 15. The number of tasks of the task to be executed and the task number of the task to be executed arranged according to the task order are not limited to the number of bits exemplified in the above embodiment, and can be changed by the technician in view of the needs of the visual design. In addition, in this embodiment, the bit 3 and the bits 29 to 31 are reserved bits (the state is 0), and the position and number of the reserved bits are not limited to those mentioned above, and the technology is required for visual design. The personnel change their own functions. The function of retaining the bits can be defined by the technicians and therefore will not be described here.

In addition, the length of the 13th type instruction sent by the host 100 is 16 bits. If the bit 14-15 is represented by a binary "01", the data storage device 200 will reply to the traditional queue status information. Host 100; assuming that the bit 14-15 is represented by a binary "11", the data storage device 200 will reply to the host state information of the present invention. In other words, the data storage device 200 can be based on the thirteenth class. The contents of the instruction are selected and the appropriate queue status information is returned to the host 100.

FIG. 5 is a flowchart of a task scheduling method according to an embodiment of the present invention, which includes steps S501 to S507. In step S501, the data storage device 200 switches to the command queue mode. In step S502, the data storage device 200 receives the queue command from the host 100, wherein the queue command includes a plurality of tasks. In step S503, the data storage device 200 lists the plurality of tasks it receives. In step S504, the data storage device 200 determines whether the plurality of queue tasks are a plurality of tasks to be executed. Since it is a known skill to determine whether the queue task is a task to be executed, no description is made. Step S505, the data storage device 200 sorts a plurality of tasks to be executed, wherein the data storage device 200 can according to the size of the task number, the priority or not, the reading or writing of the same logical data block address, and the logical data area. Conditions such as continuity of block addresses determine the execution order of a plurality of tasks to be executed. In step S506, the data storage device 200 receives a query command from the host 100, for example, a thirteenth type of command. In step S507, the data storage device 200 replies to the queue status information according to the query command. The data storage device 200 can selectively reply the queue status information or the traditional queue status information to the host 100 according to the request of the query instruction.

In summary, the present invention provides the queue status information of the preferred task execution sequence, thereby providing the task information that the host 100 has scheduled, so that the host 100 can determine the number of tasks to be executed according to the queue status information. The task number of the executed task is used to execute the task sequentially, thereby improving the efficiency of task execution.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

Claims (12)

  1. A data storage device comprising: a non-volatile memory for storing data; and a control unit for controlling the operation of the non-volatile memory, the control unit arranging a plurality of tasks from a host and determining the Whether the tasks are plural tasks to be executed, and selectively replying to a list of status information to the host, wherein the queue status information includes a number of tasks and a plurality of task numbers.
  2. The data storage device of claim 1, wherein the task numbers are arranged according to a sequence of execution of the tasks to be executed.
  3. The data storage device of claim 1, wherein the number of tasks is the number of tasks to be executed.
  4. The data storage device of claim 1, wherein the control unit selectively replies to another queue status information to the host, and the other queue status information displays each of the arrays Whether the task is pending.
  5. The data storage device of claim 1, wherein the queue status information is used to respond to a query command from the host.
  6. For example, the data storage device described in claim 2, wherein the sequence is still determined according to a logical data block address.
  7. A task sequencing method includes: transmitting a queue instruction to a remote end, the queue instruction includes a plurality of tasks; transmitting a query instruction to the remote end; and receiving a queue status information from the remote end, wherein the Column status information includes a number of tasks and a plurality of task numbers.
  8. The task sorting method described in claim 7, wherein the task numbers are arranged according to a sequence of execution of the plurality of tasks to be executed.
  9. The task sorting method described in claim 7, wherein the number of tasks is a plurality of tasks to be executed.
  10. The task sorting method according to claim 9, wherein the tasks to be executed are selected from the tasks.
  11. For example, the task sorting method described in claim 8 of the patent scope, wherein the order is still determined according to a logical data block address.
  12. The task sorting method of claim 7, further comprising: transmitting another query command to the remote end; and receiving another queue state information from the remote end, wherein the another queue state information is displayed Whether the tasks in each of these queues are pending.
TW106114698A 2016-04-21 2016-04-21 Data storage device and task sequencing method TWI651646B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040049628A1 (en) * 2002-09-10 2004-03-11 Fong-Long Lin Multi-tasking non-volatile memory subsystem
US20080195833A1 (en) * 2007-02-13 2008-08-14 Samsung Electronics Co., Ltd. Systems, methods and computer program products for operating a data processing system in which a file system's unit of memory allocation is coordinated with a storage system's read/write operation unit
US20100262979A1 (en) * 2009-04-08 2010-10-14 Google Inc. Circular command queues for communication between a host and a data storage device
US20120311197A1 (en) * 2011-05-31 2012-12-06 Micron Technology, Inc. Apparatus including memory system controllers and related methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040049628A1 (en) * 2002-09-10 2004-03-11 Fong-Long Lin Multi-tasking non-volatile memory subsystem
US20080195833A1 (en) * 2007-02-13 2008-08-14 Samsung Electronics Co., Ltd. Systems, methods and computer program products for operating a data processing system in which a file system's unit of memory allocation is coordinated with a storage system's read/write operation unit
US20100262979A1 (en) * 2009-04-08 2010-10-14 Google Inc. Circular command queues for communication between a host and a data storage device
US20120311197A1 (en) * 2011-05-31 2012-12-06 Micron Technology, Inc. Apparatus including memory system controllers and related methods

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