CN110908717B - Instruction processing method and memory controller using the same - Google Patents
Instruction processing method and memory controller using the same Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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Abstract
The invention provides an instruction processing method and a memory controller. The instruction processing method comprises the following steps: an instruction merge process is performed on a plurality of instructions received sequentially from an instruction queue. The instruction merge procedure includes an initialization step and a plurality of iterations. The initialization step comprises the following steps: transmitting the instruction in the instruction queue to the continuity check pool, transmitting the initial instruction of the instruction in the continuity check pool to the continuity list, and setting the range of the continuity list. Each iteration includes: transmitting the instruction in the instruction queue to the continuity check pool; judging whether the range of the instruction of the continuity check pool and the range of the continuity list meet the continuity condition or not; and when the first instruction and the range of the instructions meet the continuous condition, attaching the first instruction to the continuous list and resetting the range of the continuous list according to the first instruction.
Description
Technical Field
The present invention relates to an instruction processing method and a memory controller using the same, and more particularly, to an instruction processing method capable of ordering instructions accessing consecutive addresses in advance and a memory controller using the same.
Background
A typical storage controller typically executes commands in the order of commands received from a host when processing host commands. When the host computer is to access the file, a single input/output command can be transmitted to correspond to the total transmission size of the file, or a plurality of input/output commands can be transmitted to respectively correspond to smaller file transmission sizes. A single i/o instruction may allow firmware to more easily manage the required data buffers than multiple i/o instructions.
In the view of accessing a storage medium, data having consecutive logical block addresses is often stored at consecutive or adjacent physical addresses of the storage medium. When the host transfers data to the storage device, the more logical block continuity allows the storage device to have shorter media access latency and less media data management burden.
In a system architecture that supports out of order instruction execution, a memory controller may execute commands out of order from commands received from a host. Therefore, it is an objective of those skilled in the art to rearrange host commands to increase the continuity of logical blocks accessed by the commands.
Disclosure of Invention
The invention provides an instruction processing method and a memory controller using the same, which can increase the continuity of a logic block accessed by a host command.
The invention provides an instruction processing method which is suitable for a memory controller. The storage controller is used for accessing the storage medium and is coupled to the host system. The instruction processing method comprises the following steps: the instruction queue is selected from the read instruction queue and the write instruction queue, and the instruction merging procedure is performed on the plurality of instructions sequentially received by the instruction queue. The instruction includes a start logical block address and an end logical block address. The instruction merge procedure includes an initialization step and a plurality of iterations. The initialization step comprises the following steps: the instruction in the instruction queue is transmitted to the continuity check pool, the initial instruction of the instruction in the continuity check pool is transmitted to the continuous list, and the range of the continuous list is set as the start logic block address and the end logic block address of the initial instruction. Each iteration includes: transmitting the instruction in the instruction queue to the continuity check pool; judging whether the range of the instruction of the continuity check pool and the range of the continuity list meet the continuity condition or not; and when the first instruction of the above instructions meets the continuous condition with the above range, attaching the first instruction to the continuous list and resetting the range of the continuous list according to the first instruction.
In an embodiment of the present invention, when the start logical block address of the first instruction is equal to the end logical block address of the consecutive list plus one, or the end logical block address of the first instruction is equal to the start logical block address of the consecutive list minus one, the range of the first instruction and the consecutive list meets the consecutive condition.
In an embodiment of the present invention, the instruction processing method further includes: when the instruction merge process is completed, the sequential list of instructions is executed sequentially.
In an embodiment of the present invention, the completion conditions of the instruction merging procedure are: in one of the iterations, the instructions of the continuity check pool are not continuous with the scope of the continuous list.
In an embodiment of the present invention, the completion conditions of the instruction merging procedure are: one of the iterations is completed and the cumulative number of iterations is equal to the predetermined number.
In an embodiment of the present invention, the completion conditions of the instruction merging procedure are: the timer expires, wherein the timer begins when the instruction merge process begins.
In an embodiment of the present invention, in each iteration, the number of instructions transferred to the continuity check pool is less than the maximum number of instructions of the continuity check pool minus the number of instructions stored in the continuity check pool.
The invention provides a storage controller for accessing a storage medium and coupling the storage medium to a host system. The memory controller includes: an instruction dispatcher for dispatching a plurality of read instructions to the read instruction queue and dispatching a plurality of write instructions to the write instruction queue; an instruction scheduler coupled to the instruction dispatcher; an arbiter coupled to the instruction scheduler; and a processor coupled to at least one of the instruction dispatcher, the instruction scheduler, and the arbiter. The arbiter selects an instruction queue from the read instruction queue and the write instruction queue, and the instruction scheduler performs an instruction merging process on a plurality of instructions sequentially received by the instruction queue. The instruction includes a start logical block address and an end logical block address. The instruction merge procedure includes an initialization step and a plurality of iterations. The initialization step comprises the following steps: the instruction in the instruction queue is transmitted to the continuity check pool through the instruction scheduler, the initial instruction of the instruction in the continuity check pool is transmitted to the continuous list, and the range of the continuous list is set as the start logic block address and the end logic block address of the initial instruction. Each iteration includes: transmitting the instruction in the instruction queue to the continuity check pool through the instruction scheduler; judging whether the range of the instruction of the continuity check pool and the range of the continuity list meet the continuity condition or not; and when the first instruction of the instructions meets the continuous condition with the range, attaching the first instruction to the continuous list and resetting the range of the continuous list according to the first instruction.
In an embodiment of the present invention, when the start logical block address of the first instruction is equal to the end logical block address of the consecutive list plus one, or the end logical block address of the first instruction is equal to the start logical block address of the consecutive list minus one, the range of the first instruction and the consecutive list meets the consecutive condition.
In an embodiment of the present invention, the instruction processing method further includes: when the instruction merge process is complete, the processor sequentially executes the instructions of the sequential list.
In an embodiment of the present invention, the completion conditions of the instruction merging procedure are: in one of the iterations, the instructions of the continuity check pool are not continuous with the scope of the continuous list.
In an embodiment of the present invention, the completion conditions of the instruction merging procedure are: one of the iterations is completed and the cumulative number of iterations is equal to the predetermined number.
In an embodiment of the present invention, the completion conditions of the instruction merging procedure are: the timer expires, wherein the timer begins when the instruction merge process begins.
In an embodiment of the present invention, in each iteration, the number of instructions transferred to the continuity check pool is less than the maximum number of instructions of the continuity check pool minus the number of instructions stored in the continuity check pool.
Based on the above, the instruction processing method and the memory controller using the method of the present invention will dispatch the instruction received from the host to the read instruction queue and the write instruction queue, and select an instruction queue from the read instruction queue and the write instruction queue to perform the instruction merging process. In the initialization step of the instruction merge process, the initial instruction is transferred to the sequential list and the range of the sequential list is set as the start logical block address and the end logical block address of the initial instruction. In a plurality of iterations of the instruction merge process, when an instruction meets a continuation condition with respect to a range of the continuation list, the instruction is attached to the continuation list and the range of the continuation list is reset according to the instruction. When the instruction merge process is completed, the processor sequentially executes the instructions of the sequential list to access sequential logical block addresses.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention;
FIG. 2 is a flow chart of an instruction merge procedure according to an embodiment of the invention;
FIG. 3 is an example of an instruction merge process according to one embodiment of the present invention;
FIG. 4A is a diagram illustrating the instruction continuity of a conventional instruction processing method;
FIG. 4B is an instruction continuity of an instruction processing method according to an embodiment of the present invention;
FIG. 4C is an instruction continuity of an instruction processing method according to another embodiment of the present invention.
Reference numerals illustrate:
10: host system
20: storage device
100: host memory
200: memory controller
201. 202: processor and method for controlling the same
210: instruction input device
220: instruction dispatcher
230: read instruction scheduler
231: read instruction queue
232: continuity check pool
233: continuous inventory
234: continuous information recorder
240: write instruction scheduler
241: write instruction queue
242: continuity check pool
243: continuous inventory
244: continuous information recorder
250: arbitrator
260: data transmission circuit
270: data buffer
280: storage medium interface circuit
300: dynamic random access memory
400_0 to 400_n: storage medium
S201, S210 to S213, S220 to S225, S230: steps of instruction processing method
Detailed Description
Generally, a storage device includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a storage device controller (also referred to as a storage controller or a storage control circuit). Typically, storage devices are used with host systems so that the host systems can write data to or read data from the storage devices.
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.
Referring to fig. 1, a Host System (Host System) 10 includes a Host processor (not shown), a Host Memory (Host Memory) 100, and a data transmission interface circuit (Data Transfer Interface Circuit) (not shown). In this embodiment, the data transmission interface circuit is coupled (also referred to as electrically connected) to the host processor and the host memory 100. In another embodiment, the host processor, the host memory 100, and the data transfer interface circuit are coupled to each other using a System Bus (System Bus).
The memory device 20 includes a memory controller (Storage Controller) 200, a dynamic random access memory (Dynamic Random Access Memory, DRAM) 300, storage Media (Storage Media) 400_0 to 400—n, and a connection interface circuit (Connection Interface Circuit) (not shown in the figure). The storage media 400_0 to 400—n may be Rewritable nonvolatile memory modules (Rewritable Non-Volatile Memory Module).
In this embodiment, the host system 10 performs the data access operation through the connection interface circuit of the data transmission interface circuit and the storage device 20 (also referred to as the host interface of the storage device 20) to the storage device 20. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit.
In the present embodiment, the host processor, the host memory 100 and the data transmission interface circuit can be disposed on a motherboard of the host system 10. The number of data transfer interface circuits may be one or more. The motherboard may be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit. The storage device 20 may be, for example, a flash drive, a memory card, a solid state disk (Solid State Drive, SSD), or a wireless memory storage device. The wireless memory storage device may be, for example, a near field communication (Near Field Communication, NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) or the like based on a variety of wireless communication technologies. In addition, the host system 10 may also be coupled to various I/O devices such as a global positioning system (Global Positioning System, GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.
In this embodiment, the data transmission interface circuit and the connection interface circuit are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. And, the data transmission interface circuit and the connection interface circuit use protocols such as Non-volatile memory (Non-Volatile Memory express, NVMe) controller interface, advanced host controller interface (Advanced Host Controller Interface, AHCI) or PCIe architecture queue interface (PCIe architecture Queuing Interface, PQI) to transmit data and can have out-of-order execution (OOE) function. Wherein the flash nonvolatile memory protocol may have an Input/Output commit Queue (Input/Output Submission Queue, IOSQ) and an Input/Output completion Queue (Input/Output Completion Queue, IOCQ) architecture, the advanced host controller interface protocol may have (Native Command Queue, NCQ) instruction support, and the PCIe fabric Queue interface protocol may have an Input Queue (IQ) and an Output Queue (OQ) architecture.
However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit and the connection interface circuit may also be a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, an Ultra High Speed-I (UHS-I) interface standard, an Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, a Multi-Chip Package (Multi-Media Card) interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an emp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. In addition, in another embodiment, the connection interface circuit may be packaged with the memory controller 200 in a chip, or the connection interface circuit may be disposed outside a chip including the memory controller 200.
In the present embodiment, the host memory 100 is used for temporarily storing instructions or data executed by the host processor. For example, in the present exemplary embodiment, the host memory 100 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), or the like. However, it should be understood that the present invention is not limited thereto and that host memory 100 may be other suitable memory.
In this embodiment, memory controller 200 includes a processor 201, an instruction inputter 210, an instruction dispatcher 220, a read instruction scheduler 230, a write instruction scheduler 240, and an arbiter 250. The processor 201 is responsible for processing of host input and output instructions. In addition to processor 201, memory controller 200 may include one or more processors 202 responsible for processing instructions other than host input output instructions.
When instruction inputter 210 receives a plurality of instructions from host memory 100, instruction inputter 210 will pass the instructions to instruction dispatcher 220. The instruction dispatcher 220 divides the instruction into a read instruction and a write instruction, and dispatches the read instruction and the write instruction to the read instruction queue 231 of the read instruction scheduler 230 and the write instruction queue 241 of the write instruction scheduler 240, respectively. The arbiter 250 selects a read instruction group from the read instruction scheduler 230 or a write instruction group from the write instruction scheduler 240 according to a predetermined arbitration scheme, and executes the selected read instruction group or write instruction group.
The following describes a method of selecting a write instruction group. When the arbiter 250 selects the write instruction group, the write instruction scheduler 240 starts the instruction merge process. The write instruction scheduler 240 loads the write instructions in the write instruction queue 241 into the continuity check pool (Continuity Checking Pool, CCP) 242. The continuity check pool 242 may be a buffer memory, and the write instructions stored in the continuity check pool 242 are not sequentially separated. The write command scheduler 240 then checks whether the write command in the Continuity check pool 242 can be attached (applied) to a Continuity List (CL) 243. The continuous list 243 records one or more consecutive write commands with logical block addresses, and the continuous information recorder (Continuity Information Recorder, CIR) 244 records the start logical block address (Starting Logic Block Address, SLBA) and the end logical block address (Ending Logic Block Address, SLBA) of the consecutive write commands in the continuous list 243. If there is a write instruction in continuity check pool 242 that can be attached to either before continuous list 243 or after continuous list 243, then write instruction scheduler 240 attaches the write instruction to continuous list 243 and updates the start logical block address and end logical block address of continuous information recorder 244.
For example, when a write command is attached to the list 243, the start logical block address of the continuous information recorder 244 is updated to the start logical block address of the write command attached to the list 243. When a write command is attached to the consecutive list 243, the ending logical block address of the consecutive information recorder 244 is updated to the ending logical block address of the write command attached to the consecutive list 243.
It should be noted that when there is no write command in the continuous list 243, the write command scheduler 240 may randomly select a write command from the continuity check pool 242 to transfer to the continuous list 243, and initialize the start logical block address and the end logical block address of the continuous information recorder 244 to the start logical block address and the end logical block address of the randomly selected write command. In another embodiment, when there is no write instruction in the continuous list 243, the write instruction scheduler 240 may also select the write instruction from the continuity check pool 242 that was first issued (pop) from the write instruction queue 241 to be transferred to the continuous list 243.
After the write instruction of continuity check pool 242 is attached to continuity list 243 and continuity information recorder 244 is updated, an iteration is completed. The write instruction scheduler 240 may perform a number of iterations to transfer consecutive write instructions in the continuity check pool 242 to the continuity list 243. In one embodiment, the instruction merge process is complete when the write instruction scheduler 240 no longer finds a write instruction in the continuity check pool 242 that can be attached to the continuous list 243. The processor 201 sequentially executes the write instructions of the continuous list 243 and initiates the data transfer corresponding to the write instructions. In another embodiment, the condition for completion of the instruction merge process may be set such that one iteration is completed and the cumulative number of iterations is equal to a predetermined number. In another embodiment, the condition for completion of the instruction merge process may be set to expiration of a timer, wherein the timer begins at the start of the instruction merge process.
The selection method of the read instruction group is similar to the selection method of the write instruction group, and therefore will not be described again.
In this embodiment, the memory controller 200 further includes a data transmission circuit 260, a data buffer 270, and a memory medium interface circuit 280. When the instructions are executed, the data transmission circuit 260 is configured to receive an instruction from the processor 201 to transmit data with the host memory 100. For example, data is read from the host system 10 (e.g., the host memory 100) via the connection interface circuit, the data read from the host system 10 is buffered in the data buffer 270, and then the read data is written into the storage media 400_0 to 400—n via the storage media interface circuit 280. For another example, data is read from the storage media 400_0 to 400—n via the storage media interface circuit 280, and the read data is written into the host system 10 (e.g., the host memory 100) via the connection interface circuit. The storage medium interface circuit 280 is used for receiving the instruction of the processor 201, and performing writing (i.e. Programming) and reading operations on the data of the storage media 400_0 to 400—n in cooperation with the data transmission circuit 260. The memory medium interface circuit 280 may also perform erase operations on the memory media 400_0 through 400—n. In addition, the data written into the memory media 400_0 to 400—n through the memory media interface circuit 280 may be temporarily stored in the dynamic random access memory 300 first, and the data read out from the memory media 400_0 to 400—n by the memory media interface circuit 280 may also be temporarily stored in the dynamic random access memory 300.
It is noted that the instruction inputter 210, the instruction dispatcher 220, the read instruction scheduler 230, the write instruction scheduler 240, and the arbiter 250 may be implemented by hardware circuits or firmware.
FIG. 2 is a flow chart of an instruction merge procedure according to an embodiment of the invention.
Referring to fig. 2, in step S201, the arbiter 250 selects the next instruction group. The instruction groups herein may correspond to the read instruction groups in the read instruction scheduler 230 or the read instruction groups in the write instruction scheduler 240, respectively.
In step S210, an initialization step is performed.
In step S211, the continuity check pool is reloaded (reloaded).
In step S212, it is determined whether or not there is an instruction in the continuity check pool. If there is an instruction in the continuity check pool, the process proceeds to step S213. If no instruction is in the continuity check pool, the process returns to step S201.
In step S213, an instruction is selected from the continuity check pool, the continuity list and the continuity information recorder are updated according to the instruction, and the instruction is removed from the continuity check pool.
In step S220, an iteration step is performed.
In step S221, the continuity check pool is reloaded.
In step S222, whether there is an instruction in the continuity check pool for which continuity has not been checked. If there is no instruction in the continuity check pool that has not been checked for continuity, the process proceeds to step S230, where data transmission of the continuity list instruction is started. If there is an instruction in the continuity check pool that has not been checked for continuity, the flow proceeds to step S223.
In step S223, an instruction for which continuity has not been checked is selected to exist in one of the continuity check pools, and continuity of the instruction is checked.
In step S224, whether the instruction meets the continuity condition. If the instruction does not meet the continuity condition, the process returns to step S222. If the instruction meets the continuity condition, the process proceeds to step S225.
In step S225, the continuity list and the continuity information recorder are updated according to the instruction meeting the continuity condition, and the instruction is removed from the continuity check pool.
Table 1 shows 10 instructions C received sequentially from command dispatcher 220 by an instruction queue (read instruction queue 231 or write instruction queue 241) 0 、C 1 、…、C 9 . The logical block address (Logic Block Address, LBA) of each instruction ranges from 1 to 3. Table 1 lists the start logical block address (Starting Logic Block Address, SLBA) information, the number of logical blocks (Number of Logic Blocks, NLB) information, and the end logical block address (Ending Logic Block Address, ELBA) information for each instruction.
TABLE 1
| SLBA | NLB | ELBA | |
| C 0 | 8 | 1 | 9 |
| C 1 | 5 | 0 | 5 |
| C 2 | 10 | 1 | 11 |
| C 3 | 2 | 1 | 3 |
| C 4 | 6 | 1 | 7 |
| C 5 | 13 | 1 | 14 |
| C 6 | 12 | 0 | 12 |
| C 7 | 17 | 2 | 19 |
| C 8 | 1 | 0 | 1 |
| C 9 | 14 | 2 | 16 |
FIG. 3 is an example of an instruction merge process according to an embodiment of the invention.
In fig. 3, the instruction buffer size of the continuity check pool is 4. That is, the continuity check pool can temporarily store 4 instructions at most.
Please refer to fig. 3 and table 1. First, after the arbiter 250 selects the instruction group and starts the instruction merge process, instruction C- 0 、C 1 、C 2 Sequentially transmitted to the instruction queue.
In the initialization step, C- 0 、C 1 、C 2 Is transferred to a continuity check pool. The continuous list is initialized to C 0 And the SLBA field and ELBA field of the continuous information recorder are initialized to C respectively 0 That is, 8 and 9. At the same time, the instruction queue receives a new instruction C 3 。
In iteration 1, C 3 Is loaded from the instruction queue into the continuity check pool (i.e., reloaded into the continuity check pool). Due to C 2 Meets the condition of continuity, therefore C 2 Removed from the continuity check pool and attached after the continuity manifest. The ELBA field of the continuous information recorder is updated to 11. At the same time, the instruction queue receives a new instruction C 4 、C 5 、C 6 、C 7 、C 8 。
It is noted that in this embodiment, when the SLBA of an instruction is equal to ELBA+1 of the continuous information recorder or the ELBA of an instruction is equal to SLBA-1 of the continuous information recorder, the instruction meets the continuity condition.
In iteration 2, C 4 、C 5 Is loaded from the instruction queue into the continuity check pool. Due to C 4 Meets the condition of continuity, therefore C 4 Removed from the continuity check pool and attached before the continuity manifest. The SLBA field of the continuous information recorder is updated to 6. At the same time, the instruction queue receives a new instruction C 9 。
In the 3 rd iteration, C 6 Is loaded from the instruction queue into the continuity check pool. Due to C 1 、C 6 Meets the condition of continuity, therefore C 1 Removed from the continuity check pool and attached before the continuity manifest, and C 6 Removed from the continuity check pool and attached after the continuity manifest. The SLBA field of the continuous information recorder is updated to 5 and the SLBA field is updated to 12. It should be noted that although in the embodiment of fig. 2, only one instruction is attached to the continuous list in one iteration, the invention is not limited thereto. In another embodiment, two instructions may also be attached to a continuous manifest in one iteration. For example, in the 3 rd iteration of this example, due to C 1 、C 6 All meet the continuity condition, therefore C 1 And C 6 Attached before and after the continuous list, respectively.
In the 4 th iteration, C 7 、C 8 Is loaded from the instruction queue into the continuity check pool. Due to C 5 Meets the condition of continuity, therefore C 5 Removed from the continuity check pool and attached after the continuity manifest. The ELBA field of the continuous information recorder is updated to 14.
In the 5 th iteration, C 9 Is loaded from the instruction queue into the continuity check pool. Since no instruction in the continuity check pool meets the continuity condition, the instruction merge process ends and the processor 201 initiates a data transfer corresponding to instructions in the continuous list.
Fig. 4A to 4C are instruction continuity comparisons of the conventional instruction processing method and the instruction processing method according to the embodiment of the present invention.
In FIG. 4A, instruction C 0 To C 9 Are sequentially executed, which causes a discontinuity in the addresses of logical blocks accessed by the instructions during execution.
In FIG. 4B, instruction C is shown when the size of the continuity check pool (i.e., the number of instructions that the continuity check pool can temporarily store) is set to 4 0 To C 9 The instruction groups are divided into 3 groups with consecutive logical block addresses. This may increase the efficiency of instruction execution. P represents the P-th instruction merge procedure.
In FIG. 4C, instruction C is shown when the continuity check pool size is set to 2 0 To C 9 The instruction groups are divided into 6 groups with consecutive logical block addresses. As can be seen from a comparison of fig. 4B and 4C, if more resources are used to increase the size of the continuity check pool, the execution effect of the instruction merge program can be increased.
In summary, the instruction processing method and the memory controller using the method of the present invention distribute the instruction received from the host to the read instruction queue and the write instruction queue, and select an instruction queue from the read instruction queue and the write instruction queue to perform the instruction merging process. In the initialization step of the instruction merge process, the initial instruction is transferred to the sequential list and the range of the sequential list is set as the start logical block address and the end logical block address of the initial instruction. In a plurality of iterations of the instruction merge process, when an instruction meets a continuation condition with respect to a range of the continuation list, the instruction is attached to the continuation list and the range of the continuation list is reset according to the instruction. When the instruction merge process is completed, the processor sequentially executes the instructions of the sequential list to access sequential logical block addresses. By the instruction processing method and the memory controller using the method, the chance of continuous logic block addresses during data transmission can be increased, thereby obtaining shorter media access delay and less media data management burden.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (14)
1. An instruction processing method suitable for a storage controller for accessing a storage medium and coupled to a host system, the instruction processing method comprising:
selecting an instruction queue from a read instruction queue and a write instruction queue, and executing an instruction merge procedure on a plurality of instructions sequentially received from the instruction queue, the plurality of instructions including a start logical block address and an end logical block address, the instruction merge procedure including an initialization step and a plurality of iterations,
wherein the initializing step comprises: transmitting the plurality of instructions in the instruction queue to a continuity check pool, transmitting an initial instruction of the plurality of instructions in the continuity check pool to a continuous list, setting a range of the continuous list as the start logical block address and the end logical block address of the initial instruction,
wherein each of the plurality of iterations comprises: transmitting the plurality of instructions in the instruction queue to the continuity check pool; judging whether the plurality of instructions of the continuity check pool and the range of the continuous list meet a continuous condition or not; and when a first instruction of the plurality of instructions meets the continuous condition with the range, attaching the first instruction to the continuous list and resetting the range of the continuous list according to the first instruction.
2. The instruction processing method of claim 1, wherein the range of the first instruction and the consecutive list meets the consecutive condition when the starting logical block address of the first instruction is equal to the ending logical block address of the consecutive list plus one or the ending logical block address of the first instruction is equal to the starting logical block address of the consecutive list minus one.
3. The instruction processing method according to claim 1, further comprising: when the instruction merge process is complete, the plurality of instructions of the sequential manifest are executed sequentially.
4. The instruction processing method according to claim 3, wherein the completion condition of the instruction merge program is: at one of the plurality of iterations, the plurality of instructions of the continuity check pool are not continuous with the range of the continuous list.
5. A method of processing instructions according to claim 3, wherein the completion condition of the instruction merge program is: one of the plurality of iterations is completed and the cumulative number of the plurality of iterations is equal to a predetermined number.
6. A method of processing instructions according to claim 3, wherein the completion condition of the instruction merge program is: a timer expires, wherein the timer begins when the instruction merge procedure begins.
7. The instruction processing method of claim 1, wherein in each of the plurality of iterations, the number of the plurality of instructions transferred to the continuity check pool is less than a maximum number of instructions of the continuity check pool minus the number of the plurality of instructions stored in the continuity check pool.
8. A storage controller for accessing a storage medium and coupling to a host system, the storage controller comprising:
an instruction dispatcher for dispatching a plurality of read instructions to the read instruction queue and dispatching a plurality of write instructions to the write instruction queue;
an instruction scheduler coupled to the instruction dispatcher;
an arbiter coupled to the instruction scheduler; and
a processor coupled to at least one of the instruction dispatcher, the instruction scheduler, and the arbiter, wherein
The arbiter selects an instruction queue from the read instruction queue and the write instruction queue, and the instruction scheduler performs an instruction merge procedure on a plurality of instructions sequentially received from the instruction queue, the plurality of instructions including a start logical block address and an end logical block address, the instruction merge procedure including an initialization step and a plurality of iterations,
wherein the initializing step comprises: transmitting, by the instruction scheduler, the plurality of instructions in the instruction queue to a continuity check pool, transmitting an initial instruction of the plurality of instructions in the continuity check pool to a continuous list, and setting a range of the continuous list to the start logical block address and the end logical block address of the initial instruction,
wherein each of the plurality of iterations comprises: transmitting, by the instruction scheduler, the plurality of instructions in the instruction queue to the continuity check pool; judging whether the plurality of instructions of the continuity check pool and the range of the continuous list meet a continuous condition or not; and when a first instruction of the plurality of instructions meets the continuous condition with the range, attaching the first instruction to the continuous list and resetting the range of the continuous list according to the first instruction.
9. The memory controller of claim 8, wherein the first instruction meets the continuation condition with the range of the consecutive list when the starting logical block address of the first instruction is equal to the ending logical block address of the consecutive list plus one or the ending logical block address of the first instruction is equal to the starting logical block address of the consecutive list minus one.
10. The memory controller of claim 8, wherein the processor sequentially executes the plurality of instructions of the sequential manifest when the instruction merge process is complete.
11. The memory controller of claim 10, wherein the completion condition of the instruction merge program is: at one of the plurality of iterations, the plurality of instructions of the continuity check pool are not continuous with the range of the continuous list.
12. The memory controller of claim 10, wherein the completion condition of the instruction merge program is: one of the plurality of iterations is completed and the cumulative number of the plurality of iterations is equal to a predetermined number.
13. The memory controller of claim 10, wherein the completion condition of the instruction merge program is: a timer expires, wherein the timer begins when the instruction merge procedure begins.
14. The memory controller of claim 8, wherein in each of the plurality of iterations, the number of the plurality of instructions transferred to the continuity check pool is less than a maximum number of instructions of the continuity check pool minus the number of the plurality of instructions stored in the continuity check pool.
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| CN107783916A (en) * | 2016-08-26 | 2018-03-09 | 大心电子股份有限公司 | Data transmission method, storage control and inventory management circuit |
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