CN109324753B

CN109324753B - Virtual LUN management

Info

Publication number: CN109324753B
Application number: CN201710641209.XA
Authority: CN
Inventors: 李德领; 袁戎; 徐凯; 王祎磊
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2017-07-31
Filing date: 2017-07-31
Publication date: 2023-10-31
Anticipated expiration: 2037-07-31
Also published as: CN109324753A

Abstract

Virtual LUN management methods and apparatus are provided. A method of accessing an NVM chip of a solid-state storage device is disclosed comprising: acquiring a message for accessing the NVM chip; acquiring a physical LUN to be accessed by the message according to the virtual LUN number and/or the virtual block number in the message; sending out a valid chip enable signal to a CE port associated with the physical LUN; and issuing a command to the physical LUN to access the NVM chip.

Description

Virtual LUN management

Technical Field

The present application relates to storage technology, and more particularly to providing storage space and/or flash channel management using virtual LUNs in solid state storage devices.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capability for the host. The host and storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the storage device 102 via, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The Memory device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and firmware memory 110, and also for storage management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, either in software, hardware, firmware, or a combination thereof. The control component 104 may be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit ), or a combination thereof. The control component 104 can also include a processor or controller. The control component 104 loads firmware from the firmware memory 110 at runtime. The firmware memory 110 may be a NOR flash memory, a ROM, an EEPROM, or may be part of the N VM chip 105.

The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the N VM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.

The memory Target (Target) is one or more Logic units (Logic units) of a shared Chip Enable (CE) signal within the NAND flash package. Each logical unit has a logical unit number (LUN, logic Unit Number). One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other. In "Open NAND Flash Interface Specification (review 3.0)" available from http:// www.micron.com/-/media/Documents/Products/Other% 20Documents/ONFI3—0gold.ashx, the meaning of target, logical unit, LUN, plane is provided as part of the prior art.

Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block (also called a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes.

In chinese patent application publication No. CN1414468A, a scheme is provided for processing C PU (Central Processing Unit ) instructions by executing a micro instruction sequence. When the CPU is to process the specific instruction, the conversion logic circuit converts the specific instruction into a micro instruction sequence corresponding to the specific instruction, and the function of the specific instruction is realized by executing the micro instruction sequence. The micro instruction sequence or a template of the micro instruction sequence is stored in a ROM (Read Only Memory). In the process of converting a specific instruction into a micro instruction sequence, the micro instruction sequence template can be filled so as to correspond to the specific instruction.

Micro-instruction execution methods and apparatus for flash memory interface controllers are provided in chinese patent applications CN201610009789.6 and CN201510253428.1, chinese patent application CN 201610861793.5 provides a micro-instruction sequence scheduling method and apparatus, chinese patent application CN 201611213754.0 provides an IO command processing method and solid state storage device, chinese patent application CN 201611213755.5 provides a high capacity NVM interface controller, and the entire contents thereof are incorporated herein. The flash interface controller is typically coupled to multiple NVM chips, which include multiple LUNs (Logic units) or dies that can respond to and access NVM commands in parallel. Also, since there may be multiple NVM commands to be processed on each LUN or die, the NVM controller needs to schedule the processing of multiple NVM commands to maintain multiple in-process or pending NVM commands, or to maintain execution of multiple micro instruction sequences for generating and processing NVM commands.

In a high-capacity solid state disk, the controller needs to be connected with more NVM chips. Multiple dies or targets may be included within a single NVM chip. Since each die or target on an NVM chip has a Chip Enable (CE) pin and a separate CE signal is applied to each die or target as it is operated to distinguish from the operation of other NVM chips/dies/targets in a solid state disk. However, many CE signals require a large amount of IO pin resources to be consumed by the controller.

Fig. 2 is a schematic diagram of a memory system with chip enable signal expansion of chinese patent CN 201632269U. The memory system shown in FIG. 2 includes a memory controller 210 (also referred to as a solid state disk controller) and flash channels 1 (230) through m (233), each of which includes one or more flash chips (not shown). In the storage system of fig. 2, a CE extender 220 is also included. The CE extender 220 is connected to the memory controller 210. The connection of the CE extender 220 with the memory controller 210 transfers data between the CE extender 220 and the memory controller 210. In the embodiment of fig. 2, flash channels 230 and 233 share data signal lines and control signal lines other than chip enable.

CE extender 220 is connected to a plurality of flash chips or Chip Enable (CE) ports of flash die on flash channel 1 (230) to flash channel m (233) through a plurality of Chip Enable (CE) signal lines, which are indicated in fig. 2 by "flash channel 1-CE1", "flash channel 1-CEn", "flash channel m-CE1", and "flash channel m-CEn".

In the embodiment of fig. 2, there are m flash channels in the memory system, each having 1 flash chip thereon, each flash chip including n dies and n Chip Enable (CE) ports corresponding to the n dies, so that n×m CE signal lines are required in total. These n×m CE signal ports are each connected to the CE extender 220, and communication between the CE extender 220 and the memory controller 210 is performed through fewer signal lines (e.g., CE data signal lines and CE control signal lines in fig. 2). For example, the memory controller 210 indicates to the CE extender 220 that the first die of the first flash chip on the flash channel 233 is to be enabled, then the CE extender 220 generates a valid enable signal on the corresponding "flash channel m-CE1" chip enable signal line, and does not generate valid enable signals on the other chip enable signal lines.

It will still be appreciated that multiple CE expanders may be provided for enabling the memory controller to access more flash memory chips. And the technology provided by chinese patent CN201632269U can be applied to access other NVM chips.

Disclosure of Invention

The object of the present application includes providing a virtual LUN in a solid state storage device to mask the complexity caused by the diversity of channels, NVM chips, and providing a unified virtual LUN interface for the control components of the solid state storage device. Thus, in the solid-state storage device, the asymmetry of the channels (the capacity provided by the channels is different) and/or the asymmetry of the NVM chips (the NVM chips have different configurations and/or capacities) can be effectively managed, so that the development of the solid-state storage device, particularly the development process of the storage device with changed capacity, can be simplified.

An IO command processing method and an NVM interface controller are provided for supporting applications to CE expanders and expansion mechanisms to access more NVM chips.

According to a first aspect of the present application, there is provided a method of accessing an N VM chip of a solid state storage device according to the first aspect of the present application, comprising: acquiring a message for accessing the NVM chip; acquiring a physical LUN to be accessed by the message according to the virtual LUN number and/or the virtual block number in the message; sending out a valid chip enable signal to a CE port associated with the physical LUN; and issuing a command to the physical LUN to access the NVM chip.

According to a method of accessing an NVM chip of a solid-state storage device according to a first aspect of the present application, there is provided a method of accessing an NVM chip of a solid-state storage device according to the first aspect of the present application, wherein a first virtual LUN is mapped to two or more physical LUNs, the number of virtual blocks of the first virtual LUN being 2 times the number of physical blocks of the physical LUN; and obtaining the two or more physical LUNs according to the virtual LUN number through a LUN mapping table, and selecting the physical LUNs to be accessed by the message from the two or more physical LUNs according to the virtual block number and the modulo of the number of the physical blocks of the physical LUNs.

According to a method for accessing an NVM chip of a solid-state storage device according to a first aspect of the present application, there is provided a method for accessing an NVM chip of a solid-state storage device according to a third aspect of the present application, wherein a first virtual LUN and a second virtual LUN are mapped to a first physical LUN, the number of physical blocks of the first physical LUN being 2 times the number of virtual blocks of the virtual LUN; and obtaining the physical L UN to be accessed by the message according to the virtual LUN number through the LUN mapping table, and obtaining the physical block number of the physical LUN to be accessed by the message according to the virtual block number and the virtual LUN number.

According to a method of accessing an NVM chip of a solid-state storage device according to the first aspect of the present application, there is provided a method of accessing an NVM chip of a solid-state storage device according to the first aspect of the present application, wherein a first virtual LUN is mapped to two or more physical LUNs, the number of virtual blocks of the first virtual LUN being the sum of the number of physical blocks of the two or more physical LUNs; and obtaining the two or more physical LUNs according to the virtual LUN number through a LUN mapping table, and selecting the physical LUNs to be accessed by the message from the two or more physical LUNs according to the virtual block number as an index.

According to a method for accessing an NVM chip of a solid-state storage device according to a first aspect of the present application, there is provided a method for accessing an NVM chip of a solid-state storage device according to a fifth aspect of the present application, wherein an extended LUN including a physical LUN to be accessed by the message is obtained according to a virtual LUN number and a virtual block number in the message; selecting a processing unit according to the extended LUN; and the processing unit identifies the physical LUN to be accessed by the message from the extended LUNs according to the virtual LUN number.

According to one of the first to fifth methods of accessing an NVM chip of a solid-state storage device of the first aspect of the present application, there is provided a method of accessing an NVM chip of a solid-state storage device according to the sixth aspect of the present application, further comprising: selecting a processing unit according to the physical LUN; the processing unit sends out a valid chip enable signal to a CE port associated with the physical LUN; and issuing a command to the physical LUN to access the NVM chip.

According to a first method of accessing an NVM chip of a solid-state storage device according to the first aspect of the present application, there is provided a method of accessing an NVM chip of a solid-state storage device according to the seventh aspect of the present application, wherein the solid-state storage device comprises a first channel coupling the first NVM chip with a second NVM chip; the first NVM chip has a first number of physical LUNs and the second NVM chip has a second number of physical LUNs, the first number being different from the second number.

According to a seventh method of accessing an NVM chip of the solid-state storage device of the first aspect of the present application, there is provided a method of accessing an NVM chip of the solid-state storage device according to the eighth aspect of the present application, wherein the solid-state storage device further comprises a second channel, the second channel coupling a third NVM chip with a fourth NVM chip; the fourth NVM chip has a first number of physical LUNs and the third NVM chip has a second number of physical LUNs.

According to a ninth aspect of the present application, there is provided a method of accessing an NVM chip of a solid-state storage device, wherein the second NVM chip and the fourth NVM chip are arranged in spatially adjacent locations of the solid-state storage device.

According to one of the methods of accessing the NVM chip of the solid-state storage device according to the first aspect of the present application, there is provided the method of accessing the NVM chip of the solid-state storage device according to the tenth aspect of the present application, wherein if the message indicates a reset operation, acquiring all physical LUNs corresponding to the virtual LUN numbers of the message, and sending valid chip enable signals to CE ports providing all the physical LUNs; and issuing a reset command to all of these physical LUNs; and confirming that the reset command is complete on all physical LUNs.

According to one of the first to tenth methods of accessing an NVM chip of a solid-state storage device of the first aspect of the present application, there is provided a method of accessing an NVM chip of a solid-state storage device according to the eleventh aspect of the present application, wherein if the message indicates a programming operation, a programming command is issued to a physical LUN to which the message is to be accessed; and acquiring the execution state of the programming command until the programming command execution is completed.

According to a second aspect of the present application there is provided a solid state storage device according to the second aspect of the present application comprising a control means for accessing a plurality of NVM chips, the NVM chips comprising one or more physical LUNs, and a plurality of NVM chips, characterized in that the control means performs one of the methods of accessing an NVM chip of a solid state storage device according to the first aspect of the present application.

According to a third aspect of the present application, there is provided a control Unit of the first solid-state storage device according to the third aspect of the present application, including a LUN (Logic Unit) mapper and a media interface controller coupled to the LUN mapper; the LUN mapper comprises a lookup table circuit, wherein a virtual LUN number and/or a virtual block number are used as indexes to acquire a first LUN number from the lookup table circuit and serve as output of the LUN mapper; the media interface controller is coupled to the plurality of NVM chips through the first channel and the second channel; the media interface controller selects one of the channels according to the output of the LUN mapper, and generates a valid enable (CE) signal on the selected channel to activate the physical LUN corresponding to the first LUN number.

The control component of the first solid state storage device according to the third aspect of the present application provides the control component of the second solid state storage device according to the third aspect of the present application, wherein the LUN mapper maps the first virtual LUN to two or more physical LUNs.

The control component of the first solid state storage device according to the third aspect of the present application provides the control component of the third solid state storage device according to the third aspect of the present application, wherein the LUN mapper maps a plurality of virtual LUNs to a single physical LUN.

The control component of the first solid state storage device according to the third aspect of the present application provides the control component of the fourth solid state storage device according to the third aspect of the present application, wherein the LUN mapper maps a plurality of virtual LUNs to two or more physical LUNs.

According to a control component of the first solid state storage device of the third aspect of the present application, there is provided a control component of the fifth solid state storage device of the third aspect of the present application, the LUN mapper mapping the first virtual LUN to two or more physical LUNs; and the LUN mapper selecting one of the two or more physical LUNs to obtain the first LUN number according to a modulo of a virtual block number relative to a block number of the physical LUNs.

According to one of the control units of the first to fifth solid-state storage devices of the third aspect of the present application, there is provided the control unit of the sixth solid-state storage device of the third aspect of the present application, wherein the LUN mapper maps each of the consecutive virtual LUN numbers to a physical LU N of the physically separated plurality of NVM chips with the consecutive virtual LUN numbers as an index.

According to one of the control components of the first through sixth solid state storage devices of the third aspect of the present application, there is provided the control component of the seventh solid state storage device of the third aspect of the present application, wherein the media interface controller is further coupled to a CE extender, the CE extender being coupled to enable (CE) signal ports of the plurality of NVM chips through a plurality of enable (CE) signal lines.

According to a control unit of a seventh solid-state storage device according to a third aspect of the present application, there is provided the control unit of an eighth solid-state storage device according to the third aspect of the present application, wherein the media interface controller selects one of the channels according to an output of the LUN mapper, and generates a valid enable (CE) signal on the selected channel by setting a CE extender to activate a physical LUN corresponding to the first LUN number.

According to a control part of an eighth solid-state storage device of the third aspect of the present application, there is provided the control part of the ninth solid-state storage device of the third aspect of the present application, wherein the media interface controller acquires a physical LUN corresponding to a first LUN number according to the first LUN number and a virtual LUN number of the output of the LUN mapper.

According to one of the control components of the first to ninth solid state storage devices of the third aspect of the present application, there is provided the control component of the tenth solid state storage device of the third aspect of the present application, wherein the first channel is coupled to a first number of NVM chips and the second channel is coupled to a second number of NVM chips, wherein the first number is different from the second number.

According to one of the control means of the first to tenth solid state storage device of the third aspect of the present application, there is provided the control means of the eleventh solid state storage device according to the third aspect of the present application, wherein the plurality of NVM chips have different numbers of dies.

According to one of the control means of the first to eleventh solid-state storage device of the third aspect of the present application, there is provided the control means of the twelfth solid-state storage device of the third aspect of the present application, wherein the index of the LUN mapper further comprises a virtual channel number.

According to a control unit of a first solid state storage device of a third aspect of the present application, there is provided a control unit of a thirteenth solid state storage device of the third aspect of the present application, wherein the first channel couples a first NVM chip with a second NVM chip; the first NVM chip has a first number of physical LUNs and the second NVM chip has a second number of physical LUNs, the first number being different from the second number.

A control unit of a thirteenth solid state storage device according to the third aspect of the application provides the control unit of the fourteenth solid state storage device according to the third aspect of the application, wherein the solid state storage device further comprises a second channel coupling the third NVM chip with the fourth NVM chip; the fourth NVM chip has a first number of physical LUNs and the third NVM chip has a second number of physical LUNs.

According to a thirteenth or fourteenth solid state storage device of the third aspect of the present application, there is provided a control unit of the fifteenth solid state storage device of the third aspect of the present application, wherein the first NVM chip and the second NVM chip of the first channel coupling share a data signal line, and a plurality of enable (C E) signal ports of each of the first NVM chip and the second NVM chip are coupled to the media interface controller independently of each other.

According to a fourth aspect of the present application there is provided a first solid state storage device according to the fourth aspect of the present application comprising one of the control components according to the third aspect of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 illustrates a block diagram of a prior art memory device;

FIG. 2 is a schematic diagram of a prior art memory system with chip enable signal expansion;

FIG. 3A is a block diagram of a solid state storage device according to a first embodiment of the present application;

FIG. 3B illustrates a virtual LUN mapping table according to a first embodiment of the application;

FIG. 3C is a block diagram of a solid state storage device according to a second embodiment of the present application;

FIG. 3D illustrates a virtual LUN mapping table according to a second embodiment of the application;

FIG. 3E is a block diagram of a solid state storage device according to a third embodiment of the present application;

FIG. 3F illustrates a virtual LUN mapping table according to a third embodiment of the application;

FIG. 3G is a block diagram of a solid state storage device according to a fourth embodiment of the present application;

FIG. 3H illustrates a virtual LUN mapping table according to a fourth embodiment of the application;

FIG. 3I is a block diagram of a solid state storage device according to a fifth embodiment of the present application;

FIG. 3J illustrates a virtual LUN mapping table according to fifth embodiment of the application;

FIG. 3K is a block diagram of a solid state storage device according to a sixth embodiment of the present application;

FIG. 3L illustrates a virtual LUN mapping table according to a sixth embodiment of the application;

FIG. 4A is a block diagram of a solid state storage device according to a seventh embodiment of the application;

FIG. 4B illustrates a virtual LUN mapping table according to embodiment seven of the application;

FIG. 4C is a block diagram of a solid state storage device according to an eighth embodiment of the application;

FIG. 4D illustrates a virtual LUN mapping table according to embodiment eight of the application;

FIG. 4E is a block diagram of a solid state storage device according to embodiment nine of the present application;

FIG. 4F illustrates a virtual LUN mapping table according to embodiment nine of the application;

FIG. 5 is a schematic illustration of a solid state storage device according to an embodiment of the application;

FIG. 6 is a block diagram of a media interface controller of a control unit according to an embodiment of the present application;

FIG. 7 is a block diagram of a media interface controller of a control unit according to yet another embodiment of the present application;

FIG. 8 is a schematic diagram of an extended LUN according to an embodiment of the application;

FIG. 9A is a block diagram of a solid state storage device according to an embodiment ten of the present application;

FIG. 9B illustrates a virtual LUN mapping table according to embodiment ten of the application;

FIG. 9C illustrates yet another virtual LUN mapping table according to embodiment ten of the application;

FIG. 10 is a schematic diagram of a solid state storage device according to an embodiment of the application;

FIG. 11 is a process flow diagram of a message for accessing an NVM chip according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a solid state storage device according to another embodiment of the application; and

FIG. 13 illustrates a virtual LUN mapping table according to another embodiment of the application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Fig. 3A is a block diagram of a solid state storage device according to a first embodiment of the present application. The solid state storage device includes a control component and an NVM chip (NVM 0) coupled to the control component. The NVM chip (NVM 0) includes 4 dies (D IE), each die including 2 logical units (LUN 0 and LUN 1, respectively). The control component provides 4C E signals, each coupled to one of the dies of the NVM chip (NVM 0). The control component sends a command to the die via the active CE signal and selects the LUN in the die via the address in the command.

In accordance with an embodiment of the present application, the various LUNs coupled to the control element are organized as virtual LUNs. For ease of distinction, a LUN will hereinafter also be referred to as a physical LUN to distinguish it from a virtual LUN. The control part accesses each physical LUN through the virtual LUN, and when the virtual LUN is used, the factors of the position, the discontinuous number and the asymmetry of the physical LUN do not need to be concerned, so that the complexity of accessing the physical LUN is reduced. Optionally, the control component accesses the NVM chip according to the virtual LUN, and finds the physical L UN to be accessed by the virtual LUN number through a table look-up or mapping circuit.

FIG. 3B illustrates a virtual LUN mapping table according to one embodiment of the application. The virtual LUNs have consecutive numbers, in FIG. 3B, the virtual LUNs are numbered 0-7. The mapping table of FIG. 3B maps each value of the virtual LUN number to one of the physical LUNs, e.g., virtual LUN 0 maps to physical LUN 0 specified by signal CE 0, and virtual LUN 7 maps to physical LUN 1 specified by signal CE 3. In a first embodiment, the virtual LUNs have unique and consecutive numbers, and each LUN of each NVM chip of the solid-state storage device is assigned a unique virtual LUN number, and the control component accesses the NVM chip through the virtual LUN number without concern for the specific geometry (die count, LUN count, etc.) and/or location (e.g., flash channel in which the NVM chip resides, etc.).

Fig. 3C is a block diagram of a solid state storage device according to a second embodiment of the application. The control component is coupled to the NVM chip (NVM 0) and the NVM chip (NVM 1). The NVM chip includes 4 DIEs (DIE), each DIE including 2 logical units (LUN 0 and LUN 1, respectively). The control unit provides 4 CE signals, each coupled to one of the dies of the NVM chip.

FIG. 3D illustrates a virtual LUN mapping table according to a second embodiment of the application. The virtual LUNs have consecutive numbers. In the second embodiment, two physical LUNs are mapped to one virtual LUN, so that the capacity of the virtual LUN experienced by the control unit is 2 times the capacity of the physical LUN. In the virtual LUN mapping table of FIG. 3D, virtual LUN0 is mapped to physical LUN0 and physical LUN 1 indicated by signal CE 0. To distinguish the physical LUNs accessed, blocks numbered 0-M (also referred to as virtual blocks) on virtual LUN0 are mapped to physical LUN0, while blocks numbered (M+1) -N on virtual LUN0 (also referred to as virtual blocks) are mapped to physical LUN 1. So that the control component sees a virtual LUN0 with a greater number of blocks than either physical LUN0 or physical LUN 1, upon accessing virtual LUN0, it is further determined which physical LUN (and the blocks on that physical LUN) to access based on the virtual blocks accessed.

In the example of fig. 3D, two physical LUNs are mapped to one virtual LUN, and the physical LUNs mapped to the same virtual L UN are from the same die (indicated by the same CE signal). It will be appreciated that this is not required. Optionally, the two physical LUNs mapped to the same virtual LUN are from different dies or different NVM chips. Still alternatively, a virtual LUN is constructed from three or more physical LUNs.

In embodiment two, the control component experiences 8 virtual LUNs, while in embodiment one, the control component also experiences 8 virtual LUNs. Thus, the control unit designed for embodiment one can be applied to embodiment two without modifying or only modifying the number of blocks per virtual LUN, thereby quickly implementing a storage device with greater capacity. Moreover, the number of virtual LUNs is smaller than the number of physical LUNs, fewer data bits can be used in the control component to describe the LUNs to be accessed, and the occupation of storage space is reduced.

Fig. 3E is a block diagram of a solid state storage device according to a third embodiment of the present application. The control component is coupled to the NVM chip (NVM 0), the NVM chip (NVM 1) and the NVM chip (NVM 2). The NVM chip (NVM 0) includes 4 DIEs (DIE), each of the NVM chip (NVM 1) and the NVM chip (NVM 2) includes 2 DIEs (DIE), each DIE including 2 logical units (LUN 0 and LUN 1, respectively). The control component provides a CE signal to each die, one of the dies coupled to the respective NVM chip. The memory device of embodiment three uses NVM chips of different geometric features. And the complexity brought by the N VM chips with different geometric features of the virtual LUN mapping table screen of FIG. 3F.

FIG. 3F illustrates a virtual LUN mapping table according to a third embodiment of the application. In embodiment three, two physical LUNs are mapped to one virtual LUN, so that the capacity of the virtual LUN experienced by the control component is 2 times the physical LUN capacity. In the virtual LUN mapping table of FIG. 3F, virtual LUN 1 is mapped to physical LUN 0 and physical LUN 1 indicated by signal CE 1. To distinguish the physical LUNs accessed, blocks numbered 0-M (also referred to as virtual blocks) on virtual LUN 1 are mapped to physical LUN 0, while blocks numbered (M+1) -N (also referred to as virtual blocks) on virtual LUN 1 are mapped to physical LUN 1. So that the control component sees a virtual LUN 1 with more blocks than either physical LUN 0 or physical LUN 1. Upon accessing virtual LUN 1, it is further determined which physical LUN (and the block on that physical LUN) to access based on the accessed virtual block. Optionally, the two physical LUNs mapped to the same virtual LUN are from different dies or different NVM chips.

In the third embodiment, the control unit experiences 8 virtual LUNs (the same as in the first embodiment or the second embodiment), so that the control unit designed for the first embodiment or the second embodiment can be applied to the third embodiment without modifying or only modifying the number of blocks of each virtual LUN, thereby quickly realizing a storage device with a larger capacity. In embodiment 3, the die count is different for each NVM chip so that more capacity solid state storage devices can be combined.

Fig. 3G is a block diagram of a solid state storage device according to a fourth embodiment of the present application. The control component is coupled to the NVM chip (NVM 0), the NVM chip (NVM 1) and the NVM chip (NVM 2). The NVM chip (NVM 0) includes 4 DIEs (DIE), each DIE including 2 LUNs (LUN 0 and LUN 1, respectively). The N VM chip (NVM 1) and the NVM chip (NVM 2) each include 2 DIEs (DIEs), each of which includes 1 logical unit (denoted LUN 0). The control component provides a CE signal to each die, one of the dies coupled to the respective NVM chip. The memory device of the fourth embodiment uses NVM chips of different geometric features. The number of blocks included in the LUNs of the NVM chips (NVM 1 and NVM 2) is 2 times the number of blocks included in the LUNs of the NVM chip (NVM 0). And the complexity of the NVM chips with different geometric features is masked by the virtual LUN mapping table of fig. 3H.

FIG. 3H illustrates a virtual LUN mapping table according to a fourth embodiment of the application. In the virtual LUN mapping table of FIG. 3H, virtual LUN 0 is mapped to physical LUN 0 and physical LUN 1 indicated by signal CE 0. To distinguish the physical LUNs accessed, blocks numbered 0-M (also referred to as virtual blocks) on virtual LUN 0 are mapped to physical LUN 0, while blocks numbered (M+1) -N on virtual LUN 0 (also referred to as virtual blocks) are mapped to physical LUN 1. And mapping the virtual LUN 4 only to the physical LUN 0 indicated by the signal CE 4.

In the fourth embodiment, the control unit still experiences 8 virtual LUNs, so that the control unit designed for the first embodiment, the second embodiment, or the third embodiment can be applied to the fourth embodiment without modifying or only modifying the number of blocks of each virtual LUN, thereby rapidly implementing a storage device with a larger capacity. In embodiment 4, the number of dies of each NVM chip is different and the number of LUNs of each die is different, so that more capacity solid state storage devices can be combined.

Fig. 3I is a block diagram of a solid state storage device according to a fifth embodiment of the present application. The control component is coupled to the NVM chip (NVM 0), the NVM chip (NVM 1) and the NVM chip (NVM 2). The NVM chip (NVM 0) includes 4 DIEs (DIE), each DIE including 2 LUNs (LUN 0 and LUN 1, respectively). The NVM chip (NVM 1) and NVM chip (NVM 2) each include 2 DIEs (DIE), each DIE including 1 logical unit (denoted as LUN 0). The control component provides CE signals to each die, one of the dies being coupled to a respective NV M chip. NVM chips of different geometric features are used in the memory device of embodiment five. The number of blocks included in the LUNs of the N VM chips (NVM 1 and NVM 2) is the same as the number of blocks included in the LUNs of the NVM chip (NVM 0). And the complexity of the NVM chips with different geometric features is masked by the virtual LUN mapping table of fig. 3J.

FIG. 3J illustrates a virtual LUN mapping table according to fifth embodiment of the application. In the virtual LUN mapping table of FIG. 3J, virtual LUN 0 is mapped to physical LUN 0 and physical LUN 1 indicated by signal CE 0. To distinguish the physical LUNs accessed, blocks numbered 0-M (also referred to as virtual blocks) on virtual LUN 0 are mapped to physical L UN 0, while blocks numbered (M+1) -N (also referred to as virtual blocks) on virtual LUN 0 are mapped to physical LUN 1. Virtual LUN 4 is mapped to physical LUN 0 indicated by signal CE 4 and physical LUN 0 indicated by signal CE 6. Virtual LUN 5 is mapped to physical LUN 0 indicated by signal CE 5 and physical LUN 0 indicated by signal CE 7.

Fig. 3K is a block diagram of a solid-state storage device according to a sixth embodiment of the present application. The control component is coupled to the NVM chip (NVM 0). The NVM chip (NVM 0) includes 4 DIEs (DIE), each DIE including 2 LUNs (LUN 0 and LUN 1, respectively). The control component provides CE signals to each die, one of the dies coupled to a respective N VM chip. In the storage device of embodiment six, two virtual LUNs are mapped to one physical LUN. In some storage devices, the number of physical LUNs is small, subject to space or cost constraints, and a sufficient number of LUNs is required when RAID techniques are used to provide efficient data protection for storage space utilization. RAID techniques can be used for small capacity solid state storage devices by mapping a single physical L UN to one or more virtual LUNs and building RAID data protection units over a sufficient number of virtual LUNs. Alternatively, three or more virtual LUNs are mapped to one physical LUN.

FIG. 3L illustrates a virtual LUN mapping table according to a sixth embodiment of the application. In the virtual LUN mapping table of FIG. 3L, both virtual LUN 0 and virtual LUN 1 are mapped to physical LUN 0 indicated by signal CE 0. To distinguish, virtual LUN 0 is mapped to physical blocks 0-M of physical LUN 0, while virtual LUN 1 is mapped to physical blocks B- (B+M) of physical LUN 0. Where B and M are positive integers, M represents the number of virtual blocks contained in a virtual LUN, and B indicates the base address of a physical block provided on a physical LUN for a virtual LUN. For example, b=m+1, indicating an arrangement of physical blocks adjacent to each other on the physical LUN allocated for two virtual LUNs.

Fig. 4A is a block diagram of a solid state storage device according to a seventh embodiment of the application. The control unit is coupled to the NVM chip through two channels (CH 0 and CH 1, respectively). Channel CH 0 is coupled to NVM chip (NVM 0) and NVM chip (NVM 1). Channel CH 1 is coupled to NVM chip (NVM 2) and NVM chip (NVM 3). The NVM chip (NVM 0) and NVM chip (NVM 3) include 4 DIEs (DIE), each DIE including 2 LUNs (LUN 0 and LUN 1, respectively). The NVM chip (NVM 1) and the NVM chip (N VM 2) each include 2 DIEs (DIE), each DIE including 1 logical unit (denoted as LUN 0). The control component provides a CE signal to each die, one of the dies coupled to the respective NVM chip. The memory device of embodiment seven uses NVM chips of different geometric features. The number of blocks included in L UN of the NVM chips (NVM 1 and NVM 2) is the same as the number of blocks included in LUNs of the NVM chips (NVM 0 and NVM 3). And the complexity of the NVM chips with different geometric features is masked by the virtual LUN mapping table of fig. 4B.

FIG. 4B illustrates a virtual LUN mapping table according to embodiment seven of the application. In the virtual LUN mapping table of FIG. 4B, virtual LUN 0 is mapped to physical LUN 0 and physical LU N1 on channel CH 0 indicated by signal CE 0. To distinguish the physical LUNs accessed, blocks numbered 0-M (also referred to as virtual blocks) on virtual LUN 0 are mapped to physical LUN 0, while blocks numbered (M+1) -N on virtual LUN 0 (also referred to as virtual blocks) are mapped to physical LUN 1. Virtual LUN 4 is mapped to physical LUN 0 indicated by signal CE 4 and physical LUN 0 indicated by signal CE 5 on channel CH 0. Virtual LUN 5 is mapped to physical LUN 0 indicated by signal C E0 and physical LUN 0 indicated by signal CE 1 on channel CH 1. To distinguish the physical LUNs accessed, the blocks numbered 0-M on virtual LUN 4 (also referred to as virtual blocks) are mapped to physical LUN 0 indicated by CE signal 4, while the blocks numbered (m+1) -N on virtual LUN 4 (also referred to as virtual blocks) are mapped to physical LUN 1 indicated by signal CE 5. Virtual LUN 6 is mapped to physical LUN 0 and physical LUN 1 on channel CH 1 indicated by signal CE 2.

In embodiment seven, the control component accesses 5 virtual LUNs on each channel without concern for complexity not imposed by the geometry of the two NVM chips on the channel.

Fig. 4C is a block diagram of a solid state storage device according to embodiment eight of the application. The control unit is coupled to the NVM chip through three channels (CH 0, CH 1 and CH 2, respectively). Channel CH 0 is coupled to the NVM chip (NV M0). Channel CH 1 is coupled to an NVM chip (NVM 1). Channel CH 2 is coupled to NVM chips (NV M2 and NVM 3). The NVM chips (NVM 0, NVM 1, NVM 2, and NVM 3) each include 4 DIEs (DIE), each DIE including 1 LUN (denoted as LUN 0). The control component provides C E signals to each die, each coupled to one of the dies of the respective NVM chip. The memory device of embodiment eight uses NVM chips of the same geometry. While the NVM chips accommodated by the various channels may be different. The complexity of masking NVM chips of different geometric features by the virtual LUN mapping table of fig. 4D.

FIG. 4D illustrates a virtual LUN mapping table according to embodiment eight of the application. In the virtual LUN mapping table of FIG. 4D, a one-to-one correspondence is established between each physical LUN and the virtual LUN. Thus, the control component accesses each physical LUN through the virtual LUN without concern for unbalanced configuration of channels (each channel having a different number of NVM chips and physical LUNs). Providing different capacities of solid state storage devices is facilitated by providing different numbers of NVM chips on the channels.

Fig. 4E is a block diagram of a solid state storage device according to embodiment nine of the present application. The control unit is coupled to the NVM chip through three channels (CH 0, CH 1 and CH2, respectively). Channel CH 0 is coupled to the NVM chip (NV M0). Channel CH 1 is coupled to an NVM chip (NVM 1). Channel CH2 is coupled to NVM chips (NV M2 and NVM 3). The NVM chips (NVM 0, NVM 1, NVM 2, and NVM 3) each include 4 DIEs (DIE), each DIE including 1 LUN (denoted as LUN 0). The control component provides C E signals to each die, each coupled to one of the dies of the respective NVM chip. The memory device of embodiment nine uses NVM chips of the same geometry. While the NVM chips accommodated by the various channels may be different. The complexity of masking NVM chips of different geometric features by the virtual LUN mapping table of fig. 4E.

Fig. 4F illustrates a virtual LUN mapping table according to embodiment nine of the present application. In the virtual LUN mapping table of FIG. 4F, a one-to-one correspondence is established between each physical LUN and the virtual LUN. A virtual channel is also provided in embodiment nine, so that the control unit experiences the virtual channel instead of the physical channel. In the virtual LUN mapping table of FIG. 4E, all physical LUNs of physical channel CH 0 are mapped to virtual channel 0, all physical LUNs of physical channel CH 1 are mapped to virtual channel 1, 4 physical LUNs of physical channel CH2 are mapped to virtual channel 2, while the other 2 physical LUNs of physical channel CH2 are mapped to virtual channel 0 (virtual LUN 12 and virtual LUN 13 in FIG. 4F), and the other 2 physical LUNs of physical channel CH2 are mapped to virtual channel 1 (virtual LUN 14 and virtual L UN 15 in FIG. 4F). The control unit thus experiences a virtual channel CH 0 with 6 virtual LUNs, a virtual channel CH 1 with 6 virtual L UN, and a virtual channel CH2 with 4 virtual LUNs.

Thus, the control component accesses the individual physical LUNs through the virtual LUNs (and optionally also virtual channels) without concern for unbalanced configuration of channels (each channel having a different number of NVM chips and physical LUNs). Providing different capacities of solid state storage devices is facilitated by providing different numbers of NVM chips on the channels.

Alternatively, according to a ninth embodiment of the present application, the virtual channel and the virtual LU N are presented to the control unit or upper layer system. The control component or upper layer system is provided with a "standard" solid state storage device configuration, e.g., 16 virtual channels, each comprising 16 virtual LUNs, by virtual channels and virtual LUNs. Or, according to the requirements of the performance, service scene and the like of the solid-state storage device, the number of virtual channels and virtual LUNs is selected without being limited by the physical channels of the control component and the NVM chip. For example, to provide a RAID configuration of "31+1", 32 or an integer multiple of 32 virtual LUNs are required. Alternatively, the number of virtual LUNs that require each virtual channel is substantially the same. Still alternatively, on each virtual channel, a specified number of virtual LUNs are provided for use as additional storage space, etc. The "standard" solid state storage device is mapped to the physical LUN of the physical channel and/or NVM chip of the solid state storage device through the virtual LUN mapping table, thereby enabling the upper layer system to experience a standardized solid state storage device.

FIG. 5 is a schematic of a solid state storage device according to an embodiment of the application. The solid state storage device includes a control component coupled to the NVM chip through a channel. In FIG. 5, channels CH 0 and CH 1 are shown, channel C H0 being coupled to NVM chips (NVM 0 and NVM 1), channel CH 1 being coupled to NVM chips (NVM 2 and NVM 3). The NVM chips (NVM 0 and NVM 3) each include 4 DIEs (DIE), each DIE including 2 LUNs (LUN 0 and LUN 1, respectively). The NVM chips (NVM 1 and NVM 2) each include 2 DIEs (DIE), each DIE including 1 LUN (denoted as LUN 0). The control component provides a CE signal to each die, one of the dies coupled to the respective NVM chip. Alternatively, the control component can couple the NVM chip through other numbers of channels.

In the embodiment illustrated in FIG. 5, the control component accesses the physical LUNs of the NVM chip by describing the virtual LUNs and/or designating virtual block numbers in the virtual LUNs. The control component includes a LUN mapper for mapping virtual LUN numbers and/or virtual block numbers to physical LUNs. Further optionally, the LUN mapper also outputs a virtual channel number according to the virtual LUN number and/or the virtual block number, so that the control component knows which virtual channel the accessed virtual LUN belongs to.

In one example, the virtual LUNs are in one-to-one correspondence with physical LUNs, and the LUN mapper maps the virtual LUN numbers to specified physical LUNs of the die of the specified channel, specified enable signal (CE). Optionally, the LUN mapper outputs a channel number, an enable signal number and a physical LUN number, and the control unit selects and accesses a physical LUN corresponding to the virtual LUN number according to the channel, the enable signal number and the physical LUN number output by the LUN mapper. For example, the CPU of the control unit accesses the LUN mapper by executing an instruction, supplies a virtual LUN number and/or a virtual block number to the LUN mapper, and receives a channel number, an enable signal number, and a number of a physical LUN from the LUN mapper. Alternatively, the control component sends a message to the media interface controller to access the NVM chip, the message indicating the virtual LUN number and/or virtual block number. The LUN mapper outputs a channel number, an enabling signal number and a physical LUN number according to the virtual LUN number and/or the virtual block number, and modifies a message for accessing the NVM chip. The message sender thus accesses the media interface controller using the virtual LUN number, and the media interface controller accesses the physical LUN using the physical LUN number.

Still alternatively, the LUN mapper instructs the designated channel to generate a designated enable signal (CE) according to the virtual LUN number, and generates a designated physical LUN number in a command to access the NVM chip, thereby directly accessing the corresponding physical LUN.

In yet another example, a virtual LUN is mapped to multiple physical LUNs. The LUN mapper is provided with a virtual L UN number and a virtual block number. The LUN mapper obtains a plurality of corresponding physical LUNs according to the virtual LUN number, and selects the corresponding physical LUNs from the plurality of physical LUNs according to the virtual block number.

In yet another example, multiple virtual LUNs are mapped to one physical LUN. The LUN mapper is provided with a virtual LUN number and a virtual block number. The LUN mapper obtains the corresponding physical LUN according to the virtual LUN number, and the base address (see also fig. 3J, base address B) of the physical block allocated to the virtual LUN on the physical LUN, and updates the virtual block number to the physical block number on the virtual LUN.

As yet another example, the LUN mapper obtains a corresponding physical channel number, physical LUN number, and physical block number based on the virtual channel number, virtual LUN number, and virtual block number as a selection.

For example, the LUN mapper includes a lookup table circuit indexed by a virtual LUN number, with corresponding channel numbers, enable signal numbers, and physical LUN numbers being values corresponding to the same index. The virtual LUN number is provided to the lookup table circuit, which outputs the corresponding channel number, the enable signal number and the number of the physical LUN, or generates the corresponding strobe signal to select the designated channel, the enable signal and the number of the physical LUN. The lookup table is configurable, and the control component stores the mapping of virtual LUNs to physical LUNs (e.g., fig. 3B, 3D, 3F, 3H, 3J, 4B, 4D, and 4F) in the lookup table according to the manner in which the NVM chip is coupled to the control component.

As yet another example, the mapping relationship of the virtual LUN and the physical LUN is known, for example, the virtual LU N0 is mapped to the physical LUN 0 of the enable signal CE0 of the channel CH 0 (the virtual LUN is mapped to each physical LUN in the channel, enable signal, physical LUN numbering order in sequence in the numbering order); or map every two physical LUNs in the order described above to the same virtual LUN. The LUN mapper is implemented to map each virtual LUN in numbered order to one or more physical LUNs that are ordered on a physical location. Further, the LUN mapper is configured with the number of physical blocks provided by each physical LUN.

Still alternatively, the mapping of the virtual LUNs to the physical LUNs may be updated. In the use process of the solid-state storage device, the mapping relation between the virtual LUN and the physical LUN is changed by modifying the LUN mapping table. For example, in response to a physical LUN corruption, the corrupted physical LUN is replaced with a spare physical LUN, and the LUN device table is updated, mapping the virtual LUN to the spare physical LUN. As yet another example, the LUN mapping table is updated in response to a user instruction (e.g., formatting). Further, depending on the configuration or performance requirements indicated by the user, the number of virtual LUs N required is selected and the required mapping table is generated (e.g., the LUN mapping table of FIG. 3B corresponds to greater parallelism, while the mapping table of FIG. 3L corresponds to a greater number of virtual LUNs).

Fig. 6 is a block diagram of a media interface controller of a control unit according to an embodiment of the present application. The media interface controller in fig. 6 includes a message queue 610 and an NVM command processing unit 620. In the embodiment of fig. 6, message queue 610 is used to receive messages from a control unit (see also control unit of fig. 1 or 5) to access the NVM chip. The messages from the control unit may include messages indicating read, write, delete NVM chips, messages indicating read NVM chip status, read or set NVM chip Feature (Feature), and may also include user-defined messages. NVM command processing unit 620 retrieves the message from message queue 610 and sends NVM interface commands conforming to the NVM chip interface standard to the N VM chip or receives data or status from the N VM according to the NVM chip interface standard according to the indication of the message. NVM command processing unit 620 is coupled to multiple NVM chips. In the embodiment of FIG. 6, NVM command processing unit 620 is coupled to 4 NVM chips through 2 channels, each NVM chip including 2 LUNs. The NVM chips (NVM 0 and NVM 1) on channel CH 1 provide LUN0 and LUN1, respectively, and the NVM chips (NVM 2 and NVM 3) on channel CH 2 provide their LUN0 and LUN1, respectively. It will be appreciated that the NVM interface controller can couple more channels and access more NVM chips and more LUNs.

The NVM command processing unit includes a LUN mapper for mapping the virtual LUN indicated in the message accessing the NVM chip to a specified physical LUN of the specified channel. For example, in the embodiment of FIG. 6, the virtual LUN number space is 0-7, which the LUN mapper maps to physical LUN 1 of the NVM chip (NVM 3) of channel CH 2 for the virtual LUN 7 indicated in the message.

FIG. 7 is a block diagram of a media interface controller of a control unit according to yet another embodiment of the present application. The media interface controller in fig. 7 includes a message queue 710 and an NVM command processing unit 720.NVM processing unit 720 includes multiple processing units that access the NVM chip by executing sequences of micro instructions. Wherein the sequence of micro instructions to be executed is referred to as a thread. Also shown in FIG. 7 are a plurality of schedulable threads of execution in the media interface controller. When a thread is scheduled to execute, NVM command processing unit 720 accesses multiple NVM chips by setting up a CE extender.

The micro instruction sequence has its own execution state when executing each time, and multiple threads can be created based on the same micro instruction sequence. The execution state is also stored for each thread at NVM command processing unit 720. By way of example, threads are created or used based on the physical LUNs to be accessed. Such as physical LUN 0 using thread 1 to access NVM chip (NVM 0) and/or physical LUN 1 using thread 2 to access NVM chip (NVM 0). As yet another example, one thread is responsible for accessing multiple physical LUNs, e.g., in fig. 7, thread 1 is responsible for accessing physical LUNs of NVM chips (NVM 0, NVM 1, NVM 2, and NVM 3) coupled to the CE extender.

In the embodiment of fig. 7, the media interface controller is coupled to CE ports of the plurality of NVM chips through a CE extender and, by executing a microinstruction, sets the CE extender to generate a chip enable signal or a chip disable signal to any one of the plurality of NVM chips (or one of the targets thereof) that share a signal line with other ports of the same type (e.g., DQ, DQS, ALE, CLE, etc.). For example, by executing a set_ce micro instruction, the CE extender is informed of the NVM chip to be accessed. For example, to access physical LUN 1 of an NVM chip (NVM 1), thread 1 executes a set_CE micro-instruction, causing the CE extender to send a valid chip enable signal to the CE port of the NVM1 chip, and to generate invalid chip signals to the CE ports of NVM 0, NVM2, and NVM3, thereby validating the command issued by thread 1 to access the NVM chip to the NVM1 chip. In this way, a thread can access multiple NVM chips, multiple LUNs, or multiple targets.

The NVM command processing unit includes a LUN mapper for mapping the virtual LUN indicated in the message accessing the NVM chip to a specified physical LUN of the specified channel. For example, in the embodiment of FIG. 7, the virtual LUN number space is 0-7, which the LUN mapper maps to physical LUN 1 of the NV M chip (NVM 3) that is responsible for by thread 1 for the virtual LUN 7 indicated in the message.

As another example, an NVM interface controller is coupled to multiple NVM chips through multiple CE expanders, each CE expander being configured to send a chip enable signal or a chip disable signal to a designated NVM chip (or LUN or target) by executing a micro instruction.

FIG. 8 is a schematic diagram of an extended LUN according to an embodiment of the application. By way of example, the control component is coupled to 2 NVM chips (NVM 0 and NVM 1) through a CE extender, each NVM chip including two LUNs (physical LUN 0 and physical LUN 1), so that 4 physical LUNs are accessible through the CE extender. Referring to FIG. 8, each physical LUN includes 1024 physical blocks for storing data, and an extended LUN is provided to represent 4 physical LUNs accessible through the CE extender, such that the extended LUN includes 4096 physical blocks provided by the 4 physical LUNs. In an embodiment according to the application, the extended LUN is accessed in a space with a block address range of 0-4095, while the physical LUN (e.g., physical LUN 1 of NVM chip NVM 1) providing the block is obtained from the block address (e.g., 4000) of the extended L UN and the CE extender is instructed to send an enable signal to the CE port of the NVM chip (NVM 1) and a disable signal to the other CE ports.

By providing an extended LUN, each of a plurality of processing units (e.g., threads) of a media interface controller (see FIG. 6 or FIG. 7) is responsible for accessing one extended LUN. And a LUN mapper (e.g., the LUN mappers of fig. 5-7) uses the extended LUN as a physical LUN with increased capacity and provides mapping from the virtual LUN to the extended LUN. While the media interface controller handles the conversion (e.g., by threads) from an extended LUN to a physical LUN, it is convenient to have control elements adapted to manage a smaller number of physical LUNs be applied to manage a larger number of physical LUNs.

Fig. 9A is a block diagram of a solid state storage device according to embodiment ten of the present application. The control unit is coupled to the NVM chip through two channels (CH 0 and CH 1, respectively). Channel CH 0 is coupled to an NVM chip (NVM 0). Channel CH 1 is coupled to an NVM chip (NVM 1). The NVM chips (NVM 0 and NVM 1) each include 4 DIEs (DIE), each DIE including 2 LUNs (LUN 0 and LUN 1, respectively). The control component provides CE signals to each die through the CE extender. CE expander 0 of channel CH 0 is coupled to NVM chip (N VM 0), and CE expander 1 of channel CH 1 is coupled to NVM chip (NVM 1).

FIG. 9B illustrates a virtual LUN mapping table according to embodiment ten of the application. In the virtual LUN mapping table of FIG. 9B, the virtual LUN is mapped to an extended LUN. The virtual LUN number is mapped to an extended LUN number by a LUN mapper (see also FIG. 9A). The extended LUN number has a direct correspondence with the processing unit (or channel) of the media interface controller, for example, in fig. 9A, the processing unit managing channel CH 0 processes the message accessing extended LUN 0 and extended LUN 1, and the processing unit managing channel CH 1 processes the message accessing extended LUN 2 and extended LUN 3. The L UN mapper does not provide information of the physical LUN, but maintains the mapping relationship of the extended LUN and the physical LUN by the processing unit. The processing unit also determines a corresponding physical LUN according to the block number of the extended LUN. Thus, the control unit of the solid-state storage device manages the NVM chip according to the virtual LUN, and the media interface controller aggregates a plurality of physical LU ns by expanding the LUN to promote the number of operable physical LUNs.

FIG. 9C illustrates yet another virtual LUN mapping table according to embodiment ten of the application. In the virtual LUN mapping table of FIG. 9C, the virtual LUNs are mapped directly to physical LUNs without maintaining an extended LUN. The virtual LUN number is mapped by the LUN mapper (see also fig. 9A) to an enable signal (CE) sequence number and a physical LUN number. The processing unit (or channel) of the media interface controller is determined by an enable signal (C E), and the CE extender is operated by the processing unit to generate an enable (CE) signal specifying the sequence number and access the NVM chip according to the physical LUN number.

FIG. 10 is a schematic diagram of a solid state storage device according to an embodiment of the application. According to the embodiment of FIG. 10, the NVM command processing unit 1020 of the media interface controller receives a message to access the NVM chip through the message queue, the message indicating the virtual LUN number and the virtual block number to be accessed. For example, the command accesses virtual block 2047 of virtual LUN 3. The LUN mapper maps the virtual LUN number and the virtual block number of the specified field in the message to an extended LUN number and a block number (2047) in the extended L UN (referred to as an extended block number), for example, extended LUN3 (virtual LUN and extended L UN are mapped one-to-one). The processing unit (thread) (e.g., thread 3) responsible for processing the message is identified by the extended LUN number. Thread 3 processes the message, identifies the memory space that should be accessed by physical block 1023 of physical LUN3-2 in FIG. 10 to provide the message based on the extended LUN number and the block number (2047) in the extended LUN, and provides a valid chip enable signal to the NVM chip or target providing physical LUN3-2 by setting the CE extender, and issues an NVM interface command to physical L UN 3-2.

In the embodiment of FIG. 10, by organizing multiple physical LUNs into extended LUNs, the NVM interface controller can access more physical LUNs without increasing the number of threads (each thread managing access to one extended LUN), thereby implementing a larger capacity solid state storage device. Thus, access to more NVM chips is obtained without changing the upper layer system or with little modification.

FIG. 11 is a process flow diagram of a message for accessing an NVM chip according to an embodiment of the present application. In the embodiment of FIG. 11, the media interface controller obtains a message to access the NVM chip (1110), indicating the message type, virtual LUN number to access, and virtual block number. Message types include program, erase, read, reset, etc.

In one example, the type of message indication is a reset, and the virtual LUN number to be accessed (e.g., virtual LUN 3) is also indicated in the message. At step 1120, the type of message is determined, and the message type is identified as reset. In response to receiving the reset message, all physical LUNs corresponding to the virtual LUN numbers are obtained by the LUN mapper, and the processing units (threads) responsible for managing the physical LUNs and the enabling signal (C E) ports corresponding to the physical LUNs are selected (1134).

Next, and by setting up the CE extender, an enable signal is issued to the CE pins of the NVM chips or targets providing all of these physical LUNs, and a reset command is issued to all of these physical LUNs (1136). And processing the reset command on the physical LUNs and acknowledging completion of the reset command execution (1138).

Optionally, a reset command is issued to one of the physical LUNs at a time, and the issuing of a reset command to each physical LU N is repeated (1138), and an enable signal is sent on the corresponding CE pin providing the physical LUNs by the set CE extender. And processing a reset command on each physical LUN until all physical LUNs corresponding to the virtual LUNs are reset.

In yet another example, the type of message indication is a program command, and the virtual L UN number (e.g., virtual LUN 3) and virtual block number to be accessed are also indicated in the message. Next, the type of message is identified (1120), and the message type is determined to be a programming message. In response to receiving the programming message, a corresponding physical LUN is obtained by the LUN mapper according to the virtual LUN number, and a processing unit (thread) responsible for managing the physical LUN is selected (1142), and an enable signal (CE) port corresponding to the physical LUN is selected (1144). Next, an enable signal is sent to the CE pins of the NVM chip or die that provided the physical LUN by setting the CE extender and a program command is issued to the physical LUN (1146). And acquiring and checking the execution state of the programming command until the programming command execution is completed (1148).

FIG. 12 is a schematic diagram of a solid state storage device according to another embodiment of the application. According to the embodiment of fig. 12, the NVM command processing unit of the media interface controller receives a message to access the NVM chip via the message queue, the message indicating the virtual LUN number and virtual block number to be accessed. For example, the command accesses virtual block 2047 of virtual LUN 3. The LUN mapper maps the virtual LUN number and virtual block number of the specified field in the message to an extended LUN number and a block number in the extended L UN (referred to as an extended block number).

FIG. 13 is a LUN mapping table according to the embodiment of FIG. 12. An extended LUN is made up of all physical LUNs managed (by the CE extender) by each thread. Referring to FIG. 12, the extended LUN0 is composed of four physical LUNs (physical LUNs 0-0, physical LUNs 0-1, physical LUNs 0-2, and physical LUNs 0-3) coupled to the CE extender 0, each physical LUN providing 1024 blocks. Thus, the block 2047 of virtual LUN3 may be provided by the 2 nd physical LUN (denoted as logical LUN 3-1) that constitutes the virtual LUN 3. The processing units (threads) of the media interface controller are in one-to-one correspondence with the extended LUNs. The virtual LUN is made up of partial physical blocks of each of the plurality of extended LUNs. With continued reference to FIG. 12, virtual LUN0 includes physical LUNs (denoted as physical LUN 0-0, physical LUN 1-0, physical LUN 2-0, and physical LUN 3-0, respectively) coupled to the extension LUNs (denoted as extension LUN0, extension LUN1, extension LUN2, and extension LUN3, respectively) of the 4 CE expanders, while virtual LUN3 includes physical LUNs (denoted as physical LUN0-3, physical LUN 1-3, physical LUN 2-3, and physical LUN 3-3, respectively) coupled to the extension LUNs (denoted as extension LUN0, extension LUN1, extension LUN2, and extension LUN3, respectively) of the 4 CE expanders.

In the LUN mapping table of fig. 13, the extended LUN is specified by the virtual LUN number together with the virtual block number. For example, virtual blocks 0-1023 of virtual LUN 0 are mapped to extended LUN 0, while virtual blocks 1024-2047 of virtual LUN 0 are mapped to extended LUN 1. In the LUN mapping table of FIG. 13, the virtual LUNs and the extended LUNs are many-to-many mapping schemes. Virtual LUN 0 is mapped to extended LUN 0 to extended LUN 3, and extended LUN 0 provides physical blocks for both virtual LUN 0 to virtual LUN 3. The physical L UN is commonly specified by the virtual LUN number and the extended LUN number. The LUN mapping table in FIG. 13 also records the mapping relationship between the combination of the virtual LUN and the extended LUN and the physical LUN.

Referring back to fig. 12, the LUN mapper generates an extended LUN number (according to the LUN mapping table of fig. 13) from the combination of the virtual LUN number and the virtual block number in the message, and the NVM command processing unit selects one of the threads according to the extended LUN number and processes the message by the selected thread. The LUN mapper also generates a physical LUN number (according to the LUN mapping table of FIG. 13) from the combination of the virtual LUN number and the extended LUN number, and provides the physical LUN number to the selected thread. Optionally, the LUN mapper also generates a physical block number in the physical LUN; or the thread obtains the physical block number according to the virtual block number.

By way of example, in response to a received message to access an NVM chip, the virtual block address 2047 of the virtual L UN 3 to be accessed is indicated in the message, the LUN mapper (see fig. 12) determines that storage space is to be provided by the extended LUN 1 based on the virtual LUN 3 and the virtual block address 2047, and processes the message by thread 1 (see fig. 12) responsible for managing the extended LUN 1. The LUN mapper also obtains the storage space provided by physical LUNs 1-3 from virtual LUN 3 and extended LUN 1, and adds an indication of the physical LUNs to the message and provides it to the selected thread 1. Thread 1 provides a valid CE enable signal to the NVM chip or target providing the physical LUN by setting the CE extender according to the accessed physical LUN 1-3 and issues an NVM interface command to the corresponding physical LUN.

As yet another example, the media interface controller maps virtual LUNs (and blocks) to extended LUNs (and physical LUNs) in different ways such that accesses to consecutive blocks of virtual LUNs are mapped to different virtual LUNs, further enhancing parallelism of command processing.

As yet another example, the media interface controller maps commands to access consecutive blocks within a virtual LUN to different extended LUNs, or maps commands to access blocks of the same address of multiple virtual LUNs to different extended LUNs.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A method of accessing an NVM chip of a solid-state storage device, comprising:

acquiring a message for accessing the NVM chip;

according to the virtual LUN number and/or the virtual block number in the message, searching a virtual LUN mapping table or a lookup table circuit by taking the virtual LUN number and/or the virtual block number as an index, and acquiring a physical LUN to be accessed by the message;

sending out a valid chip enable signal to a CE port associated with the physical LUN; and

issuing a command to access an NVM chip to the physical LUN;

wherein the virtual LUN is organized by each physical LUN coupled to the control component, the virtual LUN is mapped to the physical LUNs of channels and/or NVM chips in the solid-state storage device indicated by the enabling signals through the virtual LUN mapping table, and each channel has different numbers of NVM chips and physical LUNs;

Wherein, the die number of each NVM chip is different, and the physical LUN number of each die is different;

wherein, the mapping relation between the virtual LUN and the physical LUN is realized by at least one of the following modes:

the first virtual LUN is mapped to two or more physical LUNs, the number of virtual blocks of the first virtual LUN being 2 times the number of physical blocks of the physical LUN; obtaining the two or more physical LUNs according to the virtual LUN numbers through a LUN mapping table, and selecting the physical LUNs to be accessed by the message from the two or more physical LUNs according to the virtual block numbers and the modulo of the number of the physical blocks of the physical LUNs;

or the first virtual LUN and the second virtual LUN are mapped to a first physical LUN, and the number of physical blocks of the first physical LUN is 2 times that of the virtual blocks of the virtual LUN; obtaining the physical LUN to be accessed by the message according to the virtual LUN number through the LUN mapping table, and obtaining the physical block number of the physical LUN to be accessed by the message according to the virtual block number and the virtual LUN number;

alternatively, the first virtual LUN is mapped to two or more physical LUNs, the number of virtual blocks of the first virtual LUN being the sum of the number of physical blocks of the two or more physical LUNs; and

the two or more physical LUNs are obtained according to the virtual LUN number through a LUN mapping table, and the physical LUNs to be accessed by the message are selected from the two or more physical LUNs according to the virtual block number as an index.

2. The method of claim 1, wherein

Obtaining an extended LUN comprising a physical LUN to be accessed by the message according to the virtual LUN number and the virtual block number in the message;

selecting a processing unit according to the extended LUN;

and the processing unit identifies the physical LUN to be accessed by the message from the extended LUNs according to the virtual LUN number.

3. The method of claim 1, further comprising:

selecting a processing unit according to the physical LUN;

the processing unit sends out a valid chip enable signal to a CE port associated with the physical LUN; and

and sending a command for accessing the NVM chip to the physical LUN.

4. The method of claim 1, wherein

The solid state storage device includes a first channel coupling a first NVM chip and a second NVM chip; the first NVM chip has a first number of physical LUNs and the second NVM chip has a second number of physical LUNs, the first number being different from the second number.

5. The method of claim 4, wherein

The solid state storage device further includes a second channel coupling the third NVM chip and the fourth NVM chip; the fourth NVM chip has a first number of physical LUNs and the third NVM chip has a second number of physical LUNs.

6. The method of claim 5, wherein

The second NVM chip and the fourth NVM chip are disposed in spatially adjacent locations of the solid-state storage device.

7. The method of any of claims 1-6, wherein if the message indicates a reset operation, obtaining all physical LUNs corresponding to virtual LUN numbers of the message, and sending valid chip enable signals to CE ports providing all the physical LUNs; and issuing a reset command to all of these physical LUNs; and

the confirm reset command is performed on all physical LUNs.

8. The method of any of claims 1-6, wherein if the message indicates a programming operation, issuing a programming command to a physical LUN to which the message is to access; and

and acquiring the execution state of the programming command until the programming command is executed.

9. A solid state storage device comprising a control unit and a plurality of NVM chips, the control unit for accessing the plurality of NVM chips, the NVM chips comprising one or more physical LUNs, characterized in that the control unit performs the method according to claims 1-8 to access the NVM chips.