CN109324753A - Virtual LUN management - Google Patents
Virtual LUN management Download PDFInfo
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- CN109324753A CN109324753A CN201710641209.XA CN201710641209A CN109324753A CN 109324753 A CN109324753 A CN 109324753A CN 201710641209 A CN201710641209 A CN 201710641209A CN 109324753 A CN109324753 A CN 109324753A
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- 239000007787 solid Substances 0.000 claims abstract description 113
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000013507 mapping Methods 0.000 claims description 126
- 238000012545 processing Methods 0.000 claims description 34
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- 238000007726 management method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 36
- 230000008569 process Effects 0.000 description 7
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- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
Provide virtual LUN management method and device.The method of the NVM chip of disclosed access solid storage device, comprising: obtain the message of access NVM chip；The message physics LUN to be accessed is obtained according to virtual No. LUN in the message and/or with virtual block number；Effective chip enable signal is issued to the associated port CE the physics LUN；And the order of access NVM chip is issued to the physics LUN.
Description
Technical field
This application involves memory technologies, more particularly in solid storage device using virtual LUN provide memory space and/
Or flash memory channel management.
Background technique
Referring to Fig. 1, the block diagram of storage equipment is illustrated.Storage equipment 102 is coupled with host, deposits for providing for host
Energy storage power.Host with storage equipment 102 between can be coupled in several ways, coupled modes include but is not limited to for example, by
The connections master such as SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, Ethernet, optical-fibre channel, cordless communication network
Machine and storage equipment 102.Host can be the information processing equipment that can be communicated through the above way with storage equipment, example
Such as, personal computer, tablet computer, server, portable computer, the network switch, router, cellular phone, a number
Word assistant etc..Storing equipment 102 includes interface 103, control unit 104, one or more NVM (nonvolatile storage, Non-
Volatile Memory) chip 105 and optionally firmware memory 110.Interface 103 can adapt to for example, by SATA,
The modes such as IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel and host exchanging data.Control unit 104 is for controlling
Data transmission between interface 103, NVM chip 105 and firmware memory 110, with being also used to storage management, host logic
Location is to flash memory physical address map, erasure balance, bad block management etc..A variety of sides of software, hardware, firmware or combinations thereof can be passed through
Formula realizes control unit 104.Control unit 104 can be FPGA, and (Field-programmable gate array, scene can
Program gate array), ASIC (Application Specific Integrated Circuit, application specific integrated circuit) or
The form of person's a combination thereof.Control unit 104 also may include processor or controller.Control unit 104 is at runtime from solid
110 loading firmware of part memory.Firmware memory 110 can be NOR flash memory, ROM, EEPROM, be also possible to N VM chip 105
Part.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), is dodged
It deposits interface controller and is coupled to NVM chip 105, and to N VM chip 105 in a manner of the interface protocol to follow NVM chip 105
Order is issued, to operate NVM chip 105, and receives the command execution results exported from NVM chip 105.Known NVM chip
Interface protocol includes " Toggle ", " ONFI " etc..
Memory target (Target) is that the shared chip in nand flash memory encapsulation enables (CE, Chip Enable) signal
One or more logic units (Logic Unit).Each logic unit has logical unit number (LUN, Logic Unit
Number).It may include one or more tube cores (Die) in nand flash memory encapsulation.Typically, logic unit corresponds to single pipe
Core.Logic unit may include multiple planes (Plane).Multiple planes in logic unit can be with parallel access, and nand flash memory
Multiple logic units in chip can execute order and report state independently of one another.Can be from http: //
Www.micron.com/~/media/Documents/Products/Other%20Documents/ONFI3_0Go
In " the Open NAND Flash Interface Specification (Revision 3.0) " that ld.ashx is obtained, provide
About target (target), logic unit, LUN, plane (Plane) meaning, be the prior art a part.
Data are usually stored and read on storage medium by page.And data are erased in blocks.Block (also referred to as physical block) packet
Containing multiple pages.Block includes multiple pages.Page (referred to as Physical Page) on storage medium has fixed size, such as 17664 bytes.
Physical Page also can have other sizes.
In the Chinese patent application of Publication No. CN1414468A, provides by executing microinstruction sequence and handle C
The scheme of PU (Central Processing Unit, central processing unit) instruction.When CPU will handle specific instruction, conversion
Specific instruction is converted into corresponding microinstruction sequence by logic circuit, realizes specific instruction by executing microinstruction sequence
Function.The template of microinstruction sequence or microinstruction sequence is stored in ROM (Read Only Memory, read-only memory)
In.During specific instruction is converted into microinstruction sequence, microinstruction sequence template can be filled, be allowed to and specific finger
It enables corresponding.
It provides in Chinese patent application CN201610009789.6 and CN201510253428.1 for flash interface
The microcommand of controller executes method and apparatus, and Chinese patent application CN 201610861793.5 provides microinstruction sequence
Dispatching method and device, Chinese patent application CN 201611213754.0 provide I/O command processing method and set with solid-state storage
Standby, Chinese patent application CN 201611213755.5 provides large capacity NVM interface controller, its full text is incorporated herein.It dodges
It deposits interface controller and is usually coupled to multiple NVM chips, NVM chip includes multiple LUN (Logic UNit, logic unit) or pipe
Core, multiple LUN and tube core can respond and access parallel NVM command.It is again multiple wait locate due to that can have on each LUN or tube core
The NVM command of reason, therefore NVM controller needs the treatment process to multiple NVM commands to be scheduled, to safeguard multiple handling
In or NVM command to be processed, or maintenance multistage be used for generate and handle NVM command microinstruction sequence execution.
In large capacity solid state hard disk, controller needs to connect more NVM chips.And it can also in single NVM chip
It include multiple tube cores or target.Due on NVM chip each tube core or target there is chip to enable (Chi p
Enable, CE) pin, and when operating each tube core or target, to apply individual CE signal to it, with same solid state hard disk
In the operations of other NVM chip/die/targets mutually distinguish.However numerous CE signals needs to consume a large amount of of controller
I/O pin resource.
The schematic diagram for the storage system with the extension of chip enable signal that Fig. 2 is Chinese patent CN201632269U.Fig. 2
The storage system shown includes that flash memory is arrived in Memory Controller 210 (also referred to as solid-state hard disk controller) and flash memory channel 1 (230)
Channel m (233) includes one or more pieces flash chip (not shown) on each flash memory channel.In the storage system of Fig. 2, also
Including CE expander 220.CE expander 220 is connected to Memory Controller 210.CE expander 220 and Memory Controller 210
Connection, transmit data between CE expander 220 and Memory Controller 210.In the embodiment of fig. 2, flash memory channel 230
With 233 shared data signal wires and the control signal wire in addition to chip is enabled.
CE expander 220 enables (CE) signal wire by a plurality of chip, arrives flash memory channel m with flash memory channel 1 (230)
(233) multiple flash chips on or the chip of flash memory die enable the port (CE) and are connected, these chips enable (C E) signal
Line uses " flash memory channel 1-CE1 ", " flash memory channel 1-CEn ", " flash memory channel m-CE1 " and " flash memory channel m-CEn " in Fig. 2
It points out.
In the embodiment of fig. 2, there is m flash memory channel in storage system, there is 1 flash chip on each flash memory channel,
Each flash chip includes that n tube core and n chip corresponding with the n tube core enable the port (CE), thus need in total
Use n*m CE signal wire.These n*m CE signal port is all connected to CE expander 220, and CE expander 220 with
It is communicated by less signal wire (for example, the CE data signal line and CE in Fig. 2 control between Memory Controller 210
Signal wire).For example, Memory Controller 210 indicates to enable first flash memory on flash memory channel 233 to CE expander 220
The first tube core of chip, then CE expander 220 generates effective on corresponding " flash memory channel m-CE1 " chip enable signal line
Enable signal, and effective enable signal is not generated on other chip enable signal lines.
Still it should be understood that can provide multiple CE expanders, for making Memory Controller be able to access that more sudden strains of a muscle
Deposit chip.And the technology that Chinese patent CN201632269U is provided can be applied to access other NVM chips.
Summary of the invention
The purpose of the application includes the diversity for providing virtual LUN in solid storage device to shield channel, NVM chip
Caused complexity provides unified virtual LUN interface for the control unit of solid storage device.To in solid storage device
In, the asymmetry (capacity that multiple channels respectively provide is different) of effective management passage and/or the asymmetry of NVM chip
(multiple NVM chips respectively have different configuration and/or capacity) simplifies the exploitation of solid storage device, and especially simplified pair
Change the development process of the storage equipment of capacity.
I/O command processing method and NVM interface controller are provided, CE expander and extension mechanism are answered for supporting
With to access more NVM chips.
According to a first aspect of the present application, it provides according to the first of the application first aspect the access solid storage device
The method of N VM chip, comprising: obtain the message of access NVM chip；According to virtual No. LUN in the message and/or with void
Quasi- block number obtains the message physics LUN to be accessed；Make to effective chip is issued with the associated port CE the physics LUN
It can signal；And the order of access NVM chip is issued to the physics LUN.
According to the method for the NVM chip of the first of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the second access solid storage device of first aspect, wherein the first virtual LUN is mapped to two
Or more physics LUN, the virtual number of blocks of the first virtual LUN be 2 times of the physics number of blocks of the physics LUN；And pass through
LUN mapping table obtains described two or more physics LUN, and the object according to virtual block number and physics LUN according to virtual No. LUN
Manage the mould of number of blocks, the physics LUN for selecting the message to be accessed from described two or more physics LUN.
According to the method for the NVM chip of the first of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the third access solid storage device of first aspect, wherein the first virtual LUN and second is virtual
LUN is mapped to the first physics LUN, and the physics number of blocks of the first physics LUN is 2 times of the virtual number of blocks of the virtual LUN；
And the message physics L UN to be accessed is obtained according to virtual No. LUN by LUN mapping table, and according to virtual block number with
Virtual No. LUN physical block number for obtaining the message physics LUN to be accessed.
According to the method for the NVM chip of the first of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the 4th access solid storage device of first aspect, wherein the first virtual LUN is mapped to two
Or more physics LUN, the virtual number of blocks of the first virtual LUN be the sum of the physics number of blocks of described two or more physics LUN；
And described two or more physics LUN are obtained according to virtual No. LUN by LUN mapping table, and according to virtual block number conduct
Index, the physics LUN for selecting the message to be accessed from described two or more physics LUN.
According to the method for the NVM chip of the first of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the 5th access solid storage device of first aspect, wherein according to the virtual LUN in the message
Number with virtual block number obtain include the message physics LUN to be accessed extension LUN；It is handled according to the extension LUN selection
Unit；The processing unit identifies the message physics LUN to be accessed from the extension LUN according to described virtual No. LUN.
According to one of the method for the NVM chip of the first to the 5th of the application first aspect the access solid storage device, mention
The method for having supplied the NVM chip according to the 6th of the application first aspect the access solid storage device, further includes: according to the object
It manages LUN and selects processing unit；The processing unit issues the enabled letter of effective chip to the associated port CE the physics LUN
Number；And the order of access NVM chip is issued to the physics LUN.
According to the method for the NVM chip of the first of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the 7th access solid storage device of first aspect, wherein the solid storage device includes the
One channel, the first passage couple the first NVM chip and the 2nd NVM chip；The first NVM chip has the first quantity
Physics LUN, the 2nd NVM chip have the physics LUN of the second quantity, and first quantity is different from the second quantity.
According to the method for the NVM chip of the 7th of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the 8th access solid storage device of first aspect, wherein the solid storage device further includes
Second channel, the second channel couple the 3rd NVM chip and the 4th NVM chip；The 4th NVM chip has the first quantity
Physics LUN, the 3rd NVM chip have the second quantity physics LUN.
According to the method for the NVM chip of the 8th of the application first aspect the access solid storage device, provide according to this
The method for applying for the NVM chip of the 9th access solid storage device of first aspect, wherein the second NVM chip and described the
Four NVM chips are disposed in the spatially adjacent position of the solid storage device.
According to one of the method for the NVM chip of the first to the 9th of the application first aspect the access solid storage device, mention
The method for having supplied the NVM chip according to the tenth of the application first aspect the access solid storage device, wherein if the message refers to
It gives instructions in reply bit manipulation, obtains all physics LUN corresponding to virtual No. LUN of the message, and to providing all these physics LUN
The port CE issue effective chip enable signal；And reset command is issued to all these physics LUN；And confirmation is multiple
Order of the bit is performed both by completion on all physics LUN.
According to one of the method for the NVM chip of the first to the tenth of the application first aspect the access solid storage device, mention
The method for having supplied the NVM chip according to the 11st of the application first aspect the access solid storage device, wherein if the message
Indicate programming operation, the physics LUN to be accessed to the message issues program command；And obtain the execution of the program command
State, until the program command executes completion.
According to the application second aspect, the solid storage device according to the application second aspect, including control unit are provided
Part and multiple NVM chips, for control unit for accessing multiple NVM chips, NVM chip includes one or more physics LUN, special
Sign is, the control unit execute the NVM chip of the access solid storage device according to the application first aspect method it
One.
According to the application third aspect, the control unit of the first solid storage device according to the application third aspect is provided
Part, including LUN (Logic Unit, logic unit) mapper and the Media Interface Connector controller for being coupled to LUN mapping device；LUN reflects
Emitter includes lut circuits, and with virtual No. LUN and/or virtual block number is that index obtains the one No. LUN from lut circuits,
Output as LUN mapping device；Media Interface Connector controller is coupled to multiple NVM chips by first passage and second channel；It is situated between
Matter interface controller generates effective enabled on the selected channel according to one of the output selector channel of LUN mapping device
(CE) signal, to activate the one No. LUN corresponding physics LUN.
According to the control unit of the first solid storage device of the application third aspect, provide according to the application third party
The control unit of second solid storage device in face, wherein the LUN mapping device by the first virtual LUN mapping to two or more
Physics LUN.
According to the control unit of the first solid storage device of the application third aspect, provide according to the application third party
The control unit of the third solid storage device in face, wherein the LUN mapping device is by multiple virtual LUN mappings to single physics
LUN。
According to the control unit of the first solid storage device of the application third aspect, provide according to the application third party
The control unit of 4th solid storage device in face, wherein the LUN mapping device by multiple virtual LUN mappings to two or more
Physics LUN.
According to the control unit of the first solid storage device of the application third aspect, provide according to the application third party
The control unit of 5th solid storage device in face, the LUN mapping device is by the first virtual LUN mapping to two or more physics
LUN；And the mould of block number of the LUN mapping device according to virtual block number relative to physics LUN, select described two or more objects
One of LUN is managed to obtain described one No. LUN.
According to one of the control unit of the first to the 5th solid storage device of the application third aspect, provide according to this
Apply for the control unit of the 6th solid storage device of the third aspect, wherein LUN mapping device is using continuous virtual No. LUN as rope
Draw, will be continuous each of No. LUN virtual, it is mapped to the physics LU N of physically separated multiple NVM chips.
According to one of the control unit of the first to the 6th solid storage device of the application third aspect, provide according to this
Apply for the control unit of the 7th solid storage device of the third aspect, wherein the Media Interface Connector controller is additionally coupled to CE extension
Device, CE expander are coupled to enabled (CE) signal port of multiple NVM chips by multiple enabled (CE) signal wires.
According to the control unit of the 7th solid storage device of the application third aspect, provide according to the application third party
The control unit of 8th solid storage device in face, wherein the Media Interface Connector controller is selected according to the output of LUN mapping device
One of channel generates effectively enabled (CE) signal by setting CE expander on the selected channel, to activate described the
One No. LUN corresponding physics LUN.
According to the control unit of the 8th solid storage device of the application third aspect, provide according to the application third party
The control unit of 9th solid storage device in face, wherein the Media Interface Connector controller is according to the of the output of LUN mapping device
One No. LUN obtain the one No. LUN corresponding physics LUN with virtual No. LUN.
According to one of the control unit of the first to the 9th solid storage device of the application third aspect, provide according to this
Apply for the control unit of the tenth solid storage device of the third aspect, wherein first passage couples the NVM chip of the first quantity, the
Two channels couple the NVM chip of the second quantity, wherein the first quantity is different from the second quantity.
According to one of the control unit of the first to the tenth solid storage device of the application third aspect, provide according to this
Apply for the control unit of the 11st solid storage device of the third aspect, wherein the multiple NVM chip has different number
Tube core.
According to one of the control unit of the first to the 11st solid storage device of the application third aspect, basis is provided
The control unit of 12nd solid storage device of the application third aspect, wherein the index of the LUN mapping device further includes void
Quasi- channel number.
According to the control unit of the first solid storage device of the application third aspect, provide according to the application third party
The control unit of 13rd solid storage device in face, wherein the first passage couples the first NVM chip and the 2nd NVM core
Piece；The first NVM chip has the physics LUN of the first quantity, and the 2nd NVM chip has the physics LUN of the second quantity,
First quantity is different from the second quantity.
According to the control unit of the 13rd solid storage device of the application third aspect, provide according to the application third
The control unit of 14th solid storage device of aspect, wherein the solid storage device further includes second channel, described
Two channels couple the 3rd NVM chip and the 4th NVM chip；The 4th NVM chip has the physics LUN of the first quantity, described
3rd NVM chip has the physics LUN of the second quantity.
According to the control unit of the 13rd or 14 solid storage devices of the application third aspect, provide according to this Shen
Please the third aspect the 15th solid storage device control unit, wherein first passage coupling the first NVM chip and second
NVM chip shared data signal wire and respective multiple enabled (C E) signal ports of the first NVM chip and the 2nd NVM chip
It is coupled to the Media Interface Connector controller independently of one another.
According to the four of the application aspects, the first solid storage device according to the application fourth aspect is provided, including
According to one of the control unit of the application third aspect.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, will be described below to embodiment
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some of the application
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 illustrates the block diagram of the storage equipment of the prior art；
Fig. 2 is the schematic diagram of the storage system in the prior art with the extension of chip enable signal；
Fig. 3 A is the block diagram according to the solid storage device of the embodiment of the present application one；
Fig. 3 B illustrates the virtual LUN mapping table according to the embodiment of the present application one；
Fig. 3 C is the block diagram according to the solid storage device of the embodiment of the present application two；
Fig. 3 D illustrates the virtual LUN mapping table according to the embodiment of the present application two；
Fig. 3 E is the block diagram according to the solid storage device of the embodiment of the present application three；
Fig. 3 F illustrates the virtual LUN mapping table according to the embodiment of the present application three；
Fig. 3 G is the block diagram according to the solid storage device of the embodiment of the present application four；
Fig. 3 H show is according to the virtual LUN mapping table of the embodiment of the present application four；
Fig. 3 I is the block diagram according to the solid storage device of the embodiment of the present application five；
Fig. 3 J illustrates the virtual LUN mapping table according to the embodiment of the present application five；
Fig. 3 K is the block diagram according to the solid storage device of the embodiment of the present application six；
Fig. 3 L illustrates the virtual LUN mapping table according to the embodiment of the present application six；
Fig. 4 A is the block diagram according to the solid storage device of the embodiment of the present application seven；
Fig. 4 B illustrates the virtual LUN mapping table according to the embodiment of the present application seven；
Fig. 4 C is the block diagram according to the solid storage device of the embodiment of the present application eight；
Fig. 4 D illustrates the virtual LUN mapping table according to the embodiment of the present application eight；
Fig. 4 E is the block diagram according to the solid storage device of the embodiment of the present application nine；
Fig. 4 F illustrates the virtual LUN mapping table according to the embodiment of the present application nine；
Fig. 5 is the signal according to the solid storage device of the embodiment of the present application；
Fig. 6 is the block diagram according to the Media Interface Connector controller of the control unit of the embodiment of the present application；
Fig. 7 is the block diagram according to the Media Interface Connector controller of the control unit of the another embodiment of the application；
Fig. 8 is the schematic diagram according to the extension LUN of the embodiment of the present application；
Fig. 9 A is the block diagram according to the solid storage device of the embodiment of the present application ten；
Fig. 9 B illustrates the virtual LUN mapping table according to the embodiment of the present application ten；
Fig. 9 C illustrates the another virtual LUN mapping table according to the embodiment of the present application ten；
Figure 10 is the schematic diagram according to the solid storage device of the embodiment of the present application；
Figure 11 is the process flow diagram according to the message of the access NVM chip of the embodiment of the present application；
Figure 12 is the schematic diagram according to the solid storage device of another embodiment of the application；And
Figure 13 illustrates the virtual LUN mapping table according to another embodiment of the application.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on this Shen
Please in embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall in the protection scope of this application.
Fig. 3 A is the block diagram according to the solid storage device of the embodiment of the present application one.Solid storage device includes control unit
With the NVM chip (NVM 0) for being coupled to control unit.NVM chip (NVM 0) includes 4 tube cores (D IE), and each tube core includes
2 logic units (being denoted as LUN 0 and LUN 1 respectively).Control unit provides 4 C E signals, is respectively coupled to NVM chip
One of the tube core of (NVM 0).Control unit is sent to tube core by effective CE signal and is ordered, and passes through the address choosing in order
Select the LUN in tube core.
According to an embodiment of the present application, each LUN tissue that will be coupled into control unit is virtual LUN.For the ease of
It distinguishes, LUN hereinafter will be also referred to as physics LUN, and be distinguished with same virtual LUN.Control unit is each by virtual LUN access
A physics LUN, when using virtual LUN, position, discontinuous number, the factor of asymmetry without care physics LUN, from
And reduce the complexity of access physics LUN.Optionally, control unit accesses NVM chip according to virtual LUN, by tabling look-up or reflecting
Transmit-receive radio road finds the physics L UN to be accessed by virtual LUN number.
Fig. 3 B illustrates the virtual LUN mapping table according to the embodiment of the present application one.Virtual LUN has continuous number, figure
In 3B, virtual LUN number is 0-7.Each value that the mapping table of Fig. 3 B numbers virtual LUN is mapped as one of physics LUN, example
Such as, virtual LUN 0 is mapped to the physics LUN 0 as specified by signal CE 0, and virtual LUN 7 is mapped to by 3 meaning of signal CE
Fixed physics LUN 1.In embodiment one, virtual LUN has unique and continuous number, each NVM core of solid storage device
Each LUN of piece is assigned unique virtual LUN number, and control unit passes through virtual LUN number access NVM chip, and need not
The particular geometric feature (number of die, LUN quantity etc.) for being concerned about NVM chip and/or position are (for example, the flash memory channel at place
Deng).
Fig. 3 C is the block diagram according to the solid storage device of the embodiment of the present application two.Control unit is coupled to NVM chip
(NVM 0) and NVM chip (NVM 1).NVM chip includes 4 tube cores (DIE), and each tube core includes 2 logic units (difference
It is denoted as LUN 0 and LUN 1).Control unit provides 4 CE signals, is respectively coupled to one of the tube core of NVM chip.
Fig. 3 D illustrates the virtual LUN mapping table according to the embodiment of the present application two.Virtual LUN has continuous number.It is real
It applies in example two, by two physics LUN mappings to a virtual LUN, so that the capacity for the virtual LUN that control unit is experienced is
2 times of physics LUN capacity.In the virtual LUN mapping table of Fig. 3 D, virtual LUN 0 is mapped to the object as indicated by signal CE 0
Manage LUN 0 and physics LUN 1.In order to distinguish accessed physics LUN, by numbered on virtual LUN 0 for 0-M block (also referred to as
Virtual block) it is mapped to physics LUN 0, and the block (also referred to as virtual block) for numbering as (M+1)-N on virtual LUN0 is mapped to object
Manage LUN 1.To which the virtual LUN 0 that control unit is seen has the block more more than physics LUN 0 or physics LUN 1,
When accessing virtual LUN 0, which physics LUN is accessed (and on physics LUN according further to the virtual block determination accessed
Block).
In the example of Fig. 3 D, by two physics LUN mappings to a virtual LUN, and it is mapped to same virtual L UN's
Physics LUN comes from identical tube core (as indicated by identical CE signal).It is appreciated that it's not necessary.Optionally, it maps
To same virtual LUN two physics LUN from different tube cores or different NVM chips.Still optionally, by three or more
More physics LUN constitute a virtual LUN.
In embodiment two, control unit experiences 8 virtual LUN, and in embodiment one, control unit equally experiences 8
A virtual LUN.To for embodiment one design control unit can not modify or only modify each virtual LUN number of blocks and
Applied to embodiment two, to fast implement the storage equipment with larger capacity.Also, the quantity of virtual LUN is less than physics
The quantity of LUN can be used less data bit in control unit to describe the LUN to be accessed, reduce to memory space
It occupies.
Fig. 3 E is the block diagram according to the solid storage device of the embodiment of the present application three.Control unit is coupled to NVM chip
(NVM 0), NVM chip (NVM 1) and NVM chip (NVM 2).NVM chip (NVM 0) includes 4 tube cores (DIE), NVM core
Piece (NVM 1) and NVM chip (NVM 2) respectively include 2 tube cores (DIE), and each tube core includes that 2 logic units (are remembered respectively
For LUN 0 and LUN 1).Control unit provides CE signal to each tube core, is respectively coupled to one of the tube core of each NVM chip.
The NVM chip of different geometrical characteristics has been used in the storage equipment of embodiment three.And pass through the virtual LUN mapping table screen of Fig. 3 F
The N VM chip bring complexity of different geometrical characteristics.
Fig. 3 F illustrates the virtual LUN mapping table according to the embodiment of the present application three.In embodiment three, by two physics LUN
It is mapped to a virtual LUN, so that the capacity for the virtual LUN that control unit is experienced is 2 times of physics LUN capacity.Fig. 3 F
Virtual LUN mapping table in, virtual LUN 1 is mapped to the physics LUN 0 as indicated by signal CE 1 and physics LUN 1.For
Accessed physics LUN is distinguished, by numbering on virtual LUN 1 is mapped to physics LUN for the block (also referred to as virtual block) of 0-M
0, and physics LUN 1 is mapped to by numbering on virtual LUN 1 for the block (also referred to as virtual block) of (M+1)-N.To control unit
The virtual LUN 1 seen has the block more more than physics LUN 0 or physics LUN 1.When accessing virtual LUN 1, into one
Step will access which physics LUN (and block on physics LUN) according to the virtual block determination accessed.Optionally, it is mapped to
Two physics LUN of same virtual LUN are from different tube cores or different NVM chips.
In embodiment three, control unit experiences 8 virtual LUN (identical with embodiment one or embodiment two), to be
The control unit that embodiment one or embodiment two design can not modify or only modify the number of blocks of each virtual LUN and be applied to
Embodiment three, to fast implement the storage equipment with larger capacity.In embodiment 3, the number of die of each NVM chip is not
Together, so as to being combined into the solid storage devices of more kinds of capacity.
Fig. 3 G is the block diagram according to the solid storage device of the embodiment of the present application four.Control unit is coupled to NVM chip
(NVM 0), NVM chip (NVM 1) and NVM chip (NVM 2).NVM chip (NVM0) includes 4 tube cores (DIE), Mei Geguan
Core includes 2 LUN (being denoted as LUN 0 and LUN 1 respectively).N VM chip (NVM 1) and NVM chip (NVM 2) respectively include 2
Tube core (DIE), each tube core include 1 logic unit (being denoted as LUN 0).Control unit provides CE signal to each tube core, point
It is not coupled to one of the tube core of each NVM chip.The NVM core of different geometrical characteristics has been used in the storage equipment of example IV
Piece.Also, block number included by the LUN of NVM chip (NVM 1 and NVM 2) is the block that the LUN of NVM chip (NVM0) is included
Several 2 times.And the NVM chip bring complexity of different geometrical characteristics is shielded by the virtual LUN mapping table of Fig. 3 H.
Fig. 3 H show is according to the virtual LUN mapping table of the embodiment of the present application four.It, will in the virtual LUN mapping table of Fig. 3 H
Virtual LUN 0 is mapped to the physics LUN 0 as indicated by signal CE 0 and physics LUN 1.In order to distinguish accessed physics
LUN is mapped to physics LUN 0 for numbering on virtual LUN 0 for the block (also referred to as virtual block) of 0-M, and will compile on virtual LUN 0
Number physics LUN 1 is mapped to for the block (also referred to as virtual block) of (M+1)-N.And virtual LUN 4 is only mapped by signal CE
Physics LUN 0 indicated by 4.
In example IV, control unit still experiences 8 virtual LUN, to for embodiment one, embodiment two or implement
The control unit that example 3 designs can not modify or only modify the number of blocks of each virtual LUN and be applied to example IV, thus fastly
Speed realizes the storage equipment with larger capacity.In embodiment 4, the number of die of each NVM chip is different, the LUN number of each tube core
Amount is different, so as to be combined into the solid storage device of more kinds of capacity.
Fig. 3 I is the block diagram according to the solid storage device of the embodiment of the present application five.Control unit is coupled to NVM chip
(NVM 0), NVM chip (NVM 1) and NVM chip (NVM 2).NVM chip (NVM 0) includes 4 tube cores (DIE), each
Tube core includes 2 LUN (being denoted as LUN 0 and LUN 1 respectively).NVM chip (NVM 1) and NVM chip (NVM 2) respectively include 2
A tube core (DIE), each tube core include 1 logic unit (being denoted as LUN 0).Control unit provides CE signal to each tube core,
It is respectively coupled to one of the tube core of each NV M chip.The NVM of different geometrical characteristics has been used in the storage equipment of embodiment five
Chip.Also, block number included by the LUN of N VM chip (NVM 1 and NVM 2) is included with the LUN of NVM chip (NVM0)
Block number is identical.And the NVM chip bring complexity of different geometrical characteristics is shielded by the virtual LUN mapping table of Fig. 3 J.
Fig. 3 J illustrates the virtual LUN mapping table according to the embodiment of the present application five.It, will in the virtual LUN mapping table of Fig. 3 J
Virtual LUN 0 is mapped to the physics LUN 0 as indicated by signal CE 0 and physics LUN 1.In order to distinguish accessed physics
LUN is mapped to physics L UN 0 for numbering on virtual LUN 0 for the block (also referred to as virtual block) of 0-M, and will be on virtual LUN 0
The block (also referred to as virtual block) that number is (M+1)-N is mapped to physics LUN 1.Virtual LUN 4 is mapped to by 4 institute of signal CE
The physics LUN 0 and the physics LUN 0 as indicated by signal CE 6 of instruction.Virtual LUN 5 is mapped to by 5 institute of signal CE
The physics LUN 0 and the physics LUN 0 as indicated by signal CE 7 of instruction.
Fig. 3 K is the block diagram according to the solid storage device of the embodiment of the present application six.Control unit is coupled to NVM chip
(NVM 0).NVM chip (NVM 0) includes 4 tube cores (DIE), and each tube core includes that 2 LUN (are denoted as LUN 0 and LUN respectively
1).Control unit provides CE signal to each tube core, is respectively coupled to one of the tube core of each N VM chip.Embodiment six is deposited
It stores up in equipment, two virtual LUN are mapped to a physics LUN.In some storage equipment, by space or the limit of cost
System, the negligible amounts of physics LUN, and be to be needed when the effective data protection of storage space utilization being provided and using RAID technique
Want enough LUN quantity.By the way that single one physical L UN is mapped as one or more virtual LUN, and sufficient amount of virtual
RAID data protection location is constructed on LUN, and RAID technique can be used for the solid storage device of low capacity.Optionally, by three
A or more virtual LUN mapping is to a physics LUN.
Fig. 3 L illustrates the virtual LUN mapping table according to the embodiment of the present application six.It, will in the virtual LUN mapping table of Fig. 3 L
Virtual LUN 0 and virtual LUN 1 both maps to the physics LUN 0 as indicated by signal CE 0.In order to distinguish, by virtual LUN 0
It is mapped to the physical block 0-M of physics LUN 0, and virtual LUN 1 is mapped to the physical block B- (B+M) of physics LU N 0.Wherein,
B and M is positive integer, and M represents the virtual number of blocks that virtual LUN is included, and it is to have one on physics LUN that B, which is indicated,
The base address for the physical block that virtual LUN is provided.For example, B=M+1, indicates on physics LUN as the physics of two virtual LUN distribution
The adjacent arrangement of block.
Fig. 4 A is the block diagram according to the solid storage device of the embodiment of the present application seven.Control unit (is divided by two channels
It is not denoted as CH 0 and CH 1) it is coupled to NVM chip.Channel C H 0 is coupled to NVM chip (NVM 0) and NVM chip (NVM 1).
Channel C H 1 is coupled to NVM chip (NVM 2) and NVM chip (NVM3).NVM chip (NVM 0) and NVM chip (NVM 3) are wrapped
4 tube cores (DIE) are included, each tube core includes 2 LUN (being denoted as LUN 0 and LUN 1 respectively).NVM chip (NVM 1) and NVM core
Piece (N VM 2) respectively includes 2 tube cores (DIE), and each tube core includes 1 logic unit (being denoted as LUN 0).Control unit to
Each tube core provides CE signal, is respectively coupled to one of the tube core of each NVM chip.It is used in the storage equipment of embodiment seven
The NVM chip of different geometrical characteristics.Also, block number included by the L UN of NVM chip (NVM 1 and NVM 2) is the same as NVM chip
(NVM 0 is identical as the block number that the LUN of NVM 3) is included.And different geometrical characteristics are shielded by the virtual LUN mapping table of Fig. 4 B
NVM chip bring complexity.
Fig. 4 B illustrates the virtual LUN mapping table according to the embodiment of the present application seven.It, will in the virtual LUN mapping table of Fig. 4 B
Virtual LUN 0 is mapped to the physics LUN 0 as indicated by signal CE 0 and physics LU N 1 on channel C H 0.In order to distinguish
The physics LUN of access is mapped to physics LUN 0 for numbering on virtual LUN 0 for the block (also referred to as virtual block) of 0-M, and will be empty
The block (also referred to as virtual block) that number is (M+1)-N on quasi- LUN 0 is mapped to physics LUN 1.Virtual LUN 4 is mapped to channel
The physics LUN 0 as indicated by signal CE 4 on the CH 0 and physics LUN 0 as indicated by signal CE 5.By virtual LUN
5 are mapped to the physics LUN 0 as indicated by signal C E 0 on the channel C H 1 and physics LUN as indicated by signal CE 1
0.In order to distinguish accessed physics LUN, it is mapped to being numbered on virtual LUN 4 for the block (also referred to as virtual block) of 0-M by CE
Physics LUN 0 indicated by signal 4, and by the block (also referred to as virtual block) for numbering as (M+1)-N on virtual LUN 4 be mapped to by
Physics LUN 1 indicated by signal CE 5.The physics as indicated by signal CE 2 virtual LUN 6 being mapped on channel C H 1
LUN 0 and physics LUN 1.
In embodiment seven, control unit accesses 5 virtual LUN on each channel, and without two be concerned about on channel
The not brought complexity of the geometrical characteristic of NVM chip.
Fig. 4 C is the block diagram according to the solid storage device of the embodiment of the present application eight.Control unit (is divided by three channels
It is not denoted as CH 0, CH 1 and CH 2) it is coupled to NVM chip.Channel C H 0 is coupled to NVM chip (NV M 0).Channel C H 1 is even
Close NVM chip (NVM 1).Channel C H 2 is coupled to NVM chip (NV M 2 and NVM 3).NVM chip (NVM 0, NVM 1,
NVM 2 and NVM 3) it respectively include 4 tube cores (DIE), each tube core includes 1 LUN (being denoted as LUN 0).Control unit to
Each tube core provides C E signal, is respectively coupled to one of the tube core of each NVM chip.It is used in the storage equipment of embodiment eight
The NVM chips of identical geometrical features.And the NVM chip that each channel is accommodated can be different.It is reflected by the virtual LUN of Fig. 4 D
Firing table shields the NVM chip bring complexity of different geometrical characteristics.
Fig. 4 D illustrates the virtual LUN mapping table according to the embodiment of the present application eight.It, will in the virtual LUN mapping table of Fig. 4 D
Each physics LUN is corresponded with foundation between virtual LUN.To, control unit accesses each physics LUN by virtual LUN,
And it need not be concerned about the unbalanced configuration (NVM chip and physics LUN that each channel has different number) in channel.By in channel
The NVM chip of upper setting different number, so that the solid storage device for providing different capabilities is more convenient.
Fig. 4 E is the block diagram according to the solid storage device of the embodiment of the present application nine.Control unit (is divided by three channels
It is not denoted as CH 0, CH 1 and CH 2) it is coupled to NVM chip.Channel C H 0 is coupled to NVM chip (NV M 0).Channel C H 1 is even
Close NVM chip (NVM 1).Channel C H 2 is coupled to NVM chip (NV M 2 and NVM 3).NVM chip (NVM 0, NVM 1,
NVM 2 and NVM 3) it respectively include 4 tube cores (DIE), each tube core includes 1 LUN (being denoted as LUN 0).Control unit to
Each tube core provides C E signal, is respectively coupled to one of the tube core of each NVM chip.It is used in the storage equipment of embodiment nine
The NVM chips of identical geometrical features.And the NVM chip that each channel is accommodated can be different.It is reflected by the virtual LUN of Fig. 4 E
Firing table shields the NVM chip bring complexity of different geometrical characteristics.
Fig. 4 F illustrates the virtual LUN mapping table according to the embodiment of the present application nine.It, will in the virtual LUN mapping table of Fig. 4 F
Each physics LUN is corresponded with foundation between virtual LUN.Virtual channel is also provided in embodiment nine, experiences control unit
Virtual channel rather than physical channel.In the virtual LUN mapping table of Fig. 4 E, all physics LUN of physical channel CH 0 are reflected
It is mapped to virtual channel 0, all physics LUN of physical channel CH 1 are mapped into virtual channel 1, and 4 of physical channel CH 2
Physics LUN is mapped into virtual channel 2, and by another 2 physics LUN mappings of physical channel CH2 to (Fig. 4 F of virtual channel 0
In, virtual LUN 12 and virtual LUN 13), by 2 physics LUN mappings again of physical channel CH 2 to (Fig. 4 F of virtual channel 1
In, virtual LUN 14 and virtual L UN 15).To which control unit experiences the virtual channel CH 0 with 6 virtual LUN, have
There are the virtual channel CH 1 of 6 virtual L UN, and the virtual channel CH 2 with 4 virtual LUN.
To which control unit accesses each physics LUN by virtual LUN (optionally, further including virtual channel), and need not
It is concerned about the unbalanced configuration (NVM chip and physics LUN that each channel has different number) in channel.By being arranged on a passage
The NVM chip of different number, so that the solid storage device for providing different capabilities is more convenient.
Optionally, according to the embodiment of the present application nine, virtual channel and virtual LU N are shown to control unit or upper-level system.
The configuration of " standard " solid storage device, such as 16 are provided to control unit or upper-level system by virtual channel and virtual LUN
Virtual channel, each virtual channel include 16 virtual LUN.Alternatively, according to need such as the performance of solid storage device, business scenarios
It asks, the quantity of selection virtual channel and virtual LUN, and the limitation of the physical channel of uncontrolled component and NVM chip.For example,
To provide the RAID configuration of " 31+1 ", the virtual LUN of integral multiple of 32 or 32 are needed.Alternatively, needing each virtual channel
Virtual LUN quantity is substantially the same.Still optionally, in each virtual channel, the virtual LUN for providing specified quantity is used as volume
Outer memory space etc..By " standard " solid storage device, the reality of solid storage device is mapped to by virtual LUN mapping table
The physics LUN of channel and/or NVM chip, so that upper-level system be made to experience standardized solid storage device.
Fig. 5 is the signal according to the solid storage device of the embodiment of the present application.Solid storage device includes control unit, control
Component processed is coupled to NVM chip by channel.In Fig. 5, channel C H 0 and channel C H 1 are illustrated, channel C H 0 is coupled to NVM
Chip (NVM 0 and NVM 1), channel C H 1 is coupled to NVM chip (NVM 2 and NVM3).NVM chip (NVM 0 and NVM 3)
It respectively include 4 tube cores (DIE), each tube core includes 2 LUN (being denoted as LUN 0 and LUN 1 respectively).NVM chip (NVM 1 with
And NVM 2) it respectively include 2 tube cores (DIE), each tube core includes 1 LUN (being denoted as LUN 0).Control unit is to each tube core
CE signal is provided, one of the tube core of each NVM chip is respectively coupled to.Optionally, control unit can pass through the logical of other quantity
Road couples NVM chip.
In the embodiment that Fig. 5 is shown, control unit is by describing virtual LUN and/or specifying the virtual block number in virtual LUN
Access the physics LUN of NVM chip.Control unit includes LUN mapping device, for by virtual No. LUN and/or virtual block number is mapped to
Physics LUN.Still optionally further, LUN mapping device also according to virtual No. LUN and/or virtual block number and export virtual channel number, make
It obtains control unit and knows which virtual channel the virtual LUN accessed belongs to.
In one example, virtual LUN and physics LUN is to correspond, and LUN mapping device is mapped to finger for virtual No. LUN
Routing, specified enable signal (CE) tube core specified physics LUN.Optionally, LUN mapping device output channel numbers, is enabled
The number of signal number and physics LUN, channel, enable signal number and the physics LUN that control unit is exported according to LUN mapping device
Number choose and access the corresponding physics LUN with virtual No. LUN.For example, the CPU of control unit is by executing instruction access
LUN mapping device provides virtual No. LUN and/or virtual block number to LUN mapping device, and numbers, makes from LUN mapping device receiving channel
The number of energy signal number and physics LUN.Alternatively, control unit issues the message of access NVM chip to Media Interface Connector controller,
Virtual No. LUN and/or virtual block number are indicated in message.LUN mapping device is according to virtual No. LUN and/or virtual block number output is logical
The number of road number, enable signal number and physics LUN, and modify the message of access NVM chip.To which message sender uses
Virtual No. LUN access Media Interface Connector controller, and Media Interface Connector controller uses No. LUN access physics LUN of physics.
Still optionally, LUN mapping device indicates that specified channel generates specified enable signal (CE) according to virtual No. LUN,
And specified physics LUN number is generated in the order of access NVM chip, to directly access corresponding physics LUN.
In another example, virtual LUN is mapped to multiple physics LUN.To LUN mapping device provide virtual L UN with
And virtual block number.LUN mapping device obtains corresponding multiple physics LUN according to virtual No. LUN, and according to virtual block number, from multiple
Corresponding physics LUN is selected in physics LUN.
In still another example, multiple virtual LUN are mapped to a physics LUN.It is provided to LUN mapping device virtual
No. LUN and virtual block number.LUN mapping device obtains corresponding physics LUN according to virtual No. LUN, and distributes on physics LUN
To the base address (referring also to Fig. 3 J, base address B) of the physical block of the virtual LUN, and virtual block number is updated on the virtual LUN
Physical block number.
As further example, LUN mapping device according to virtual channel number, it is virtual No. LUN with virtual block number alternatively, obtain
To corresponding physical channel number, physics LUN and physical block number.
As an example, LUN mapping device includes lut circuits, and lut circuits are index with virtual No. LUN, with corresponding
Channel number, enable signal number and the number of physics LUN are corresponding value with index.Virtual LUN is provided to lut circuits
Number, lut circuits export the number of corresponding channel number, enable signal number and physics LUN, or generate corresponding choosing
Messenger is to select the number in specified channel, enable signal and physics LUN.Look-up table is configurable, control unit root
Be coupled to the mode of control unit according to NVM chip, by the mapping relations of virtual LUN and physics LUN (for example, Fig. 3 B, 3D, 3F,
3H, 3J, 4B, 4D and 4F) storage is in a lookup table.
As another example, the mapping relations of virtual LUN and physics LUN are known, for example, virtual LU N 0 is reflected
Virtual LUN (is sequentially mapped in numerical order by channel, enables by the physics LUN 0 for being mapped to the enable signal CE0 of channel C H 0
Each physics LUN of signal, physics LUN number order)；Or by by the every two physics LUN mapping of said sequence to same
A virtual LUN.LUN mapping device be embodied as one that each virtual LUN is mapped to physically sequence in numerical order or
Multiple physics LUN.Further, physics number of blocks provided by each physics LUN is configured for LUN mapping device.
Still optionally, the mapping relations of virtual LUN and physics LUN can be updated.In solid storage device use process
In, by modifying LUN mapping table, and change the mapping relations of virtual LUN Yu physics LUN.For example, damaged in response to physics LUN,
The physics LUN damaged with spare physical LUN replacement, and LUN equipment list is updated, by virtual LUN mapping to spare physical LUN.Make
LUN mapping table is updated in response to user instruction (for example, formatting) for another example.Further, it is indicated according to user
Configuration or performance requirement, virtual LU number N required for selecting, and mapping table required for generating is (for example, the LUN of Fig. 3 B
The corresponding bigger concurrency of mapping table, and the mapping table of Fig. 3 L corresponds to more quantity of virtual LUN).
Fig. 6 is the block diagram according to the Media Interface Connector controller of the control unit of the embodiment of the present application.Media Interface Connector in Fig. 6
Controller includes message queue 610 and NVM command processing unit 620.In the embodiment of Fig. 6, message queue 610 comes for receiving
From the message of the access NVM chip of control unit (referring also to the control unit of Fig. 1 or Fig. 5).Message from control unit can
It is read including instruction, write-in, the message for deleting NVM chip, can also include that NVM chip status, reading or setting are read in instruction
The message of NVM chip features (Feature), and also may include user self-defined message.NVM command processing unit 620 from
Message queue 610 obtains message, and is connect according to the instruction of message to the NVM that the transmission of N VM chip meets NVM chip interface standard
Mouth order receives data or state from N VM according to NVM chip interface standard.NVM command processing unit 620 is coupled to multiple
NVM chip.In the embodiment in fig 6, NVM command processing unit 620 is coupled to 4 NVM chips, each NVM by 2 channels
Chip includes 2 LUN.LUN 0 and LUN1 is respectively provided in the NVM chip (NVM 0 and NVM 1) of channel C H 1, in channel C H
2 NVM chip (NVM 2 and NVM 3) respectively provides its LUN0 and LUN1.It should be understood that NVM interface controller can couple more
More channels, and access more NVM chips and more LUN.
NVM command processing unit includes LUN mapping device, for reflecting the virtual LUN indicated in the message for accessing NVM chip
It is mapped to the specified physics LUN of dedicated tunnel.For example, the numbering space of virtual LUN is 0-7, for message in the embodiment of Fig. 6
The virtual LUN 7 of middle instruction, LUN mapping device map that the physics LUN 1 of the NVM chip (NVM 3) of channel C H 2.
Fig. 7 is the block diagram according to the Media Interface Connector controller of the control unit of the another embodiment of the application.Medium in Fig. 7
Interface controller includes message queue 710 and NVM command processing unit 720.NVM processing unit 720 includes multiple processing units,
Multiple processing units access NVM chip by executing microinstruction sequence.Wherein, the microinstruction sequence being performed is referred to as line
Journey.Multiple execution threads that are scheduled in Media Interface Connector controller are also shown in Fig. 7.In the scheduled execution of thread, NVM
Command process unit 720 is by setting CE expander, to access multiple NVM chips.
Microinstruction sequence possesses the execution state of oneself in each execute, and can be created based on same microinstruction sequence multiple
Thread.Execution state also is stored for per thread in NVM command processing unit 720.As an example, based on the physics to be accessed
LUN is to create or using thread.Such as the physics LUN 0 of NVM chip (NVM 0) is accessed using thread 1, and/or use line
Journey 2 accesses the physics LUN 1 of NVM chip (NVM 0).As another example, a thread is responsible for multiple physics LUN's
Access, for example, thread 1 is responsible for NVM chip (NVM 0, NVM 1, NVM 2 and the NVM for being coupled to CE expander in Fig. 7
3) access of physics LUN.
In the example of figure 7, Media Interface Connector controller is coupled to the port CE of multiple NVM chips by CE expander,
And by execute microcommand, come be arranged CE expander into multiple NVM chips any one (or in which target
One of (Target)) generate chip enable signal or chip disabling signal, other similar port (examples of these multiple NVM chips
Such as, DQ, DQS, ALE, CLE etc.) share signal wire.For example, to be visited by executing Set_CE microcommand to CE expander informing
Ask NVM chip.For example, for the physics LUN 1 of access NVM chip (NVM 1), thread 1 executes Set_CE microcommand, so that CE expands
It opens up device and sends effective chip enable signal to the port CE of 1 chip of NVM, and produced to the port CE of NVM 0, NVM2 and NVM3
Raw invalid chip signal, so that the order for the access NVM chip for issuing thread 1 comes into force to NVM1 chip.By this method, line
Journey can access multiple NVM chips, multiple LUN or multiple targets.
NVM command processing unit includes LUN mapping device, for reflecting the virtual LUN indicated in the message for accessing NVM chip
It is mapped to the specified physics LUN of dedicated tunnel.For example, the numbering space of virtual LUN is 0-7, for message in the embodiment of Fig. 7
The virtual LUN 7 of middle instruction, LUN mapping device map that the physics LUN 1 for the NV M chip (NVM 3) being responsible for by thread 1.
As another example, NVM interface controller is coupled to multiple NVM chips by multiple CE expanders, by holding
Row microcommand, come be arranged each CE expander to specified NVM chip (alternatively, LUN or target) transmission chip enable signal or
Chip disables signal.
Fig. 8 is the schematic diagram according to the extension LUN of the embodiment of the present application.As an example, control unit passes through CE expander
It is coupled to 2 NVM chips (NVM 0 and NVM 1), each NVM chip includes two LUN (physics LUN 0 and physics LUN 1),
To may have access to 4 physics LUN by CE expander.Referring to Fig. 8, each physics LUN include 1024 for storing data
Physical block provides extension LUN to represent the 4 physics LUN that can be accessed by CE expander, so that extending LUN includes by 4 objects
Manage 4096 physical blocks that LUN is provided.According to an embodiment of the present application, visited in the space that block address range is 0-4095
Ask extension LUN, and the block address (for example, 4000) according to extension L UN obtains the physics LUN for providing the block (for example, NVM chip
The physics LUN 1 of NVM 1), and indicate CE expander to the port CE of NVM chip (NVM 1) send enable signal, and to other
The port CE sends disabling signal.
LUN, multiple processing units (for example, thread) of Media Interface Connector controller (referring to Fig. 6 or Fig. 7) are extended by providing
Each of be responsible for access one extension LUN.And LUN mapping device (such as LUN mapping device of Fig. 5 to Fig. 7) is used as LUN is extended
The physics LUN that capacity becomes larger, and the mapping from virtual LUN to extension LUN is provided.And Media Interface Connector controller is (for example, pass through line
Journey) processing is from the conversion of LUN to physics LUN is extended, to easily make the control unit for being suitable for managing lesser amt physics LUN
Part is applied to manage large number of physics LUN.
Fig. 9 A is the block diagram according to the solid storage device of the embodiment of the present application ten.Control unit (is divided by two channels
It is not denoted as CH 0 and CH 1) it is coupled to NVM chip.Channel C H 0 is coupled to NVM chip (NVM 0).Channel C H 1 is coupled to NVM
Chip (NVM 1).NVM chip (NVM 0 and NVM 1) respectively includes 4 tube cores (DIE), and each tube core includes 2 LUN (difference
It is denoted as LUN 0 and LUN 1).Control unit provides CE signal to each tube core by CE expander.The CE expander of channel C H 0
0 is coupled to NVM chip (N VM 0), and the CE expander 1 of channel C H 1 is coupled to NVM chip (NVM 1).
Fig. 9 B illustrates the virtual LUN mapping table according to the embodiment of the present application ten.It, will in the virtual LUN mapping table of Fig. 9 B
Virtual LUN mapping is to extending LUN.Extension LUN is mapped as by virtual No. LUN by LUN mapping device (referring also to Fig. 9 A).Extension
No. LUN processing unit (or channel) with Media Interface Connector controller has in direct corresponding relationship, such as Fig. 9 A, management passage
The processing unit of CH 0, processing access extension LUN 0 and the message for extending LUN 1, and the processing unit of management passage CH 1, place
Reason access extension LUN 2 and the message for extending LUN 3.L UN mapper does not provide the information of physics LUN, but by processing unit
The mapping relations of maintenance extension LUN and physics LUN.Block number of the processing unit also according to extension LUN determines corresponding physics LUN.
To the control unit of solid storage device, NVM chip is managed by virtual LUN, Media Interface Connector controller passes through extension LUN polymerization
Multiple physics LU N, to promote operable physics LUN quantity.
Fig. 9 C illustrates the another virtual LUN mapping table according to the embodiment of the present application ten.The virtual LUN mapping table of Fig. 9 C
In, virtual LUN is mapped directly into physics LUN, and need not maintenance extension LUN.It will be virtual by LUN mapping device (referring also to Fig. 9 A)
No. LUN is mapped as enable signal (CE) serial number and physics LUN.The place of Media Interface Connector controller is determined by enable signal (C E)
It manages in unit (or channel), and generates enabled (CE) signal of appointed sequence number by processing unit operation CE expander, and according to physics
No. LUN access NVM chip.
Figure 10 is the schematic diagram according to the solid storage device of the embodiment of the present application.According to the embodiment of Figure 10, medium is connect
The NVM command processing unit 1020 of mouth controller receives the message of access NVM chip by message queue, indicates and wants in message
Virtual No. LUN and virtual block number of access.For example, the virtual block 2047 of the virtual LUN 3 of command access.LUN mapping device is by message
Virtual No. LUN of middle specific field and virtual block number are mapped as the block number (2047) in extension LUN and extension L UN (referred to as
Extend block number), as an example, extension LUN 3 (virtual LUN is to map one by one with extension L UN).It is negative according to No. LUN identification of extension
Duty handles the processing unit (thread) (for example, thread 3) of the message.Thread 3 handles message, according to extension LUN and extension LUN
In block number (2047) identification should to provide the storage that be accessed of the message by the physical block 1023 of the physics LUN 3-2 in Figure 10 empty
Between, and effective chip enable signal is provided to the NVM chip or target that provide physics LUN3-2 by setting CE expander,
And NVM interface order is issued to physics L UN 3-2.
In the embodiment in figure 10, by being extension LUN by multiple physics LUN tissue, so that being not required to increase Thread Count
In the case where amount (access that per thread management extends LUN to one), NVM interface controller can access more physics LUN,
To realize the solid storage device of larger capacity.To obtain in the case where not changing upper-level system or change very little
To the access ability of more NVM chips.
Figure 11 is the process flow diagram according to the message of the access NVM chip of the embodiment of the present application.In the embodiment of Figure 11,
Media Interface Connector controller obtains the message (1110) of access NVM chip, indicate type of message in message, to be accessed it is virtual
No. LUN and virtual block number.Type of message includes programming, erasing, reading, reset etc..
In one example, the type of message instruction is to reset, and further indicates the virtual No. LUN (example to be accessed in message
Such as virtual LUN 3).In step 1120, the type of message is judged, identify type of message to reset.It is resetted in response to receiving
Message obtains corresponding all physics LUN according to virtual No. LUN by LUN mapping device, and selects to be responsible for managing these physics
The processing unit (thread) of LUN and the port (1134) the corresponding enable signal of these physics LUN (C E).
Next, and being drawn by setting CE expander to the CE of the NVM chip or target that provide all these physics LUN
Human hair combing waste goes out enable signal, and issues reset command (1136) to all these physics LUN.And on these physics LUN
Reset command is managed, and confirms that reset command executes completion (1138).
Optionally, a sending reset command into these physics LUN every time, and repeat to send out to each physics LU N
Reset command (1138) out, and sent and enabled on the corresponding CE pin that these physics LUN is provided by setting CE expander
Signal.And reset command is handled on each physics LUN, until having resetted the corresponding all physics LUN of virtual LUN.
In another example, the type of message instruction is program command, further indicates the virtual L to be accessed in message
No. UN (such as virtual LUN 3) and virtual block number.Next, the type (1120) of identification message, and judge type of message
To program message.In response to receiving programming message, by LUN mapping device, corresponding physics LUN is obtained according to virtual No. LUN,
And select the processing unit (thread) (1142) and the corresponding enable signal of physics LUN (CE) of being responsible for management physics LUN
Port (1144).Next, being sent by setting CE expander to the CE pin of the NVM chip or tube core that provide physics LUN
Enable signal, and program command (1146) are issued to physics LUN.And obtain and check the execution state of program command,
Until program command executes completion (1148).
Figure 12 is the schematic diagram according to the solid storage device of another embodiment of the application.According to the embodiment of Figure 12, it is situated between
The NVM command processing unit of matter interface controller receives the message of access NVM chip by message queue, indicates and wants in message
Virtual No. LUN and virtual block number of access.For example, the virtual block 2047 of the virtual LUN 3 of command access.LUN mapping device is by message
Virtual No. LUN of middle specific field and virtual block number are mapped as block number (the referred to as extension blocks in extension LUN and extension L UN
Number).
Figure 13 is the LUN mapping table according to the embodiment of the application Figure 12.Extension LUN is to be managed (to lead to by per thread
Cross CE expander) all physics LUN constituted.Referring to Figure 12, LUN 0 is extended by being coupled to four physics of CE expander 0
LUN (physics LUN 0-0, physics LUN 0-1, physics LUN 0-2 and physics LUN0-3) is constituted, and each physics LUN provides 1024
A block.To which the block 2047 of virtual LUN3 can be mentioned by the 2nd physics LUN (being denoted as logic LUN 3-1) for forming virtual LU N3
For.The processing unit (thread) of Media Interface Connector controller is corresponded with extension LUN.Virtual LUN is by each of multiple extension LUN
Part physical block formed.With continued reference to Figure 12, virtual LUN 0 includes the extension LUN for being respectively coupled to 4 CE expanders
(be denoted as respectively extension LUN0, extension LUN1, extension LUN2 and extend LUN3) physics LUN (be denoted as physics LUN 0-0 respectively,
Physics LUN 1-0, physics LUN 2-0 and physics LUN 3-0), and virtual LUN 3 includes being respectively coupled to 4 CE expanders
Extension LUN (be denoted as respectively extension LUN0, extension LUN1, extension LUN2 and extend LUN3) physics LUN (be denoted as physics respectively
LUN 0-3, physics LUN 1-3, physics LUN 2-3 and physics LUN 3-3).
In the LUN mapping table of Figure 13, extension LUN is specified jointly with virtual block number by virtual No. LUN.For example, virtual LUN 0
0-1023 virtual block, be mapped to extension LUN 0, and the 1024-2047 virtual block of virtual LUN 0, be mapped to expansion
Open up LUN 1.In the LUN mapping table of Figure 13, virtual LUN and extension LUN be multi-to-multi mapping mode.Virtual LUN 0 is mapped
To extension LUN 0 to extension LUN 3, and extends LUN 0 and all provide physical block to virtual LUN 3 for virtual LUN 0.By virtual
No. LUN is specified physics L UN with extension LUN jointly.In the LUN mapping table of Figure 13, also has recorded virtual LUN and extend LUN's
The mapping relations of combination and physics LUN.
Referring back to Figure 12, LUN mapping device is extended according to the combination producing of virtual No. LUN in message and virtual block number
No. LUN (according to the LUN mapping table of Figure 13), NVM command processing unit is according to extension one of No. LUN selection thread, and by being chosen
The thread selected handles the message.LUN mapping device is also according to virtual No. LUN and combination producing physics LUN of No. LUN of extension
(according to the LUN mapping table of Figure 13), and the thread selected is supplied to by physics LUN.Optionally, LUN mapping device also generates
Physical block number in physics LUN；Or physical block number is obtained according to virtual block number by thread.
As an example, in response to the message of the access NVM chip received, the virtual L UN 3 to be accessed is indicated in message
Virtual block address 2047, LUN mapping device (referring to Figure 12) determines according to virtual LUN 3 and virtual block address 2047 by extending
LUN 1 provides memory space, and the thread 1 (referring to Figure 12) by being responsible for administration extensions LUN 1 handles the message.LUN mapping device
It obtains providing memory space by physics LUN 1-3 also according to virtual LUN 3 and extension LUN 1, and the instruction of physics LUN will be added
It is added in message, and is supplied to selected thread 1.Thread 1 is extended according to the physics LUN 1-3 accessed by setting CE
Device to provide effective CE enable signal to the NVM chip or target for providing physics LUN, and issues NVM to corresponding physics LUN
Interface command.
As still another example, virtual LUN (and block) is mapped to by Media Interface Connector controller in different ways
It extends LUN (and physics LUN), so that the access of the continuous blocks to virtual LUN, is mapped to different virtual LUN, thus into
The concurrency of one step promotion command process.
As still another example, Media Interface Connector controller arrives the command mapping of the continuous blocks accessed in virtual LUN
Difference extension LUN, or will access multiple virtual LUN the block with identical address command mapping to different extension LUN.
The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any
Those familiar with the art within the technical scope of the present application, can easily think of the change or the replacement, and should all contain
Lid is within the scope of protection of this application.Therefore, the protection scope of the application should be subject to the protection scope in claims.
Claims (10)
1. a kind of method for the NVM chip for accessing solid storage device, comprising:
Obtain the message of access NVM chip；
The message physics LUN to be accessed is obtained according to virtual No. LUN in the message and/or with virtual block number；
Effective chip enable signal is issued to the associated port CE the physics LUN；And
The order of access NVM chip is issued to the physics LUN.
2. according to the method described in claim 1, wherein
First virtual LUN is mapped to two or more physics LUN, and the virtual number of blocks of the first virtual LUN is the physics LUN
2 times of physics number of blocks；And
Described two or more physics LUN are obtained according to virtual No. LUN by LUN mapping table, and according to virtual block number and object
Manage the mould of the physics number of blocks of LUN, the physics LUN for selecting the message to be accessed from described two or more physics LUN.
3. according to the method described in claim 1, wherein
First virtual LUN and the second virtual LUN is mapped to the first physics LUN, and the physics number of blocks of the first physics LUN is described
2 times of the virtual number of blocks of virtual LUN；And
Obtain the message physics LUN to be accessed according to virtual No. LUN by LUN mapping table, and according to virtual block number with
Virtual No. LUN physical block number for obtaining the message physics LUN to be accessed.
4. according to the method described in claim 1, wherein
First virtual LUN is mapped to two or more physics LUN, the virtual number of blocks of the first virtual LUN be it is described two or
The sum of the physics number of blocks of more physics LUN；And
Described two or more physics LUN are obtained according to virtual No. LUN by LUN mapping table, and according to virtual block number conduct
Index, the physics LUN for selecting the message to be accessed from described two or more physics LUN.
5. according to the method described in claim 1, wherein
The extension including the message physics LUN to be accessed is obtained with virtual block number according to virtual No. LUN in the message
LUN；
Processing unit is selected according to the extension LUN；
The processing unit identifies the message physics LUN to be accessed from the extension LUN according to described virtual No. LUN.
6. according to the method described in claim 1, wherein
The solid storage device includes first passage, and the first passage couples the first NVM chip and the 2nd NVM chip；Institute
The physics LUN that the first NVM chip has the first quantity is stated, the 2nd NVM chip has the physics LUN of the second quantity, described
First quantity is different from the second quantity.
7. according to the method described in claim 6, wherein
The solid storage device further includes second channel, and the second channel couples the 3rd NVM chip and the 4th NVM chip；
The 4th NVM chip has the physics LUN of the first quantity, and the 3rd NVM chip has the physics LUN of the second quantity.
8. according to the method described in claim 7, wherein
The 2nd NVM chip and the 4th NVM chip are disposed in the spatially adjacent position of the solid storage device
It sets.
9. the method according to claim 1, wherein if the message indication reset operates, obtain the message
Virtual No. LUN corresponding to all physics LUN, and issue effective core to the port CE for providing all these physics LUN
Piece enable signal；And reset command is issued to all these physics LUN；And
Confirmation reset command is performed both by completion on all physics LUN.
10. a kind of solid storage device, including control unit and multiple NVM chips, control unit is for accessing multiple NVM cores
Piece, NVM chip include one or more physics LUN, which is characterized in that the control unit executes -9 institute according to claim 1
Method to access the NVM chip.
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