CN108153582A - I/O command processing method and Media Interface Connector controller - Google Patents
I/O command processing method and Media Interface Connector controller Download PDFInfo
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- CN108153582A CN108153582A CN201611106674.5A CN201611106674A CN108153582A CN 108153582 A CN108153582 A CN 108153582A CN 201611106674 A CN201611106674 A CN 201611106674A CN 108153582 A CN108153582 A CN 108153582A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4831—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/48—Indexing scheme relating to G06F9/48
- G06F2209/484—Precedence
Abstract
This application provides I/O command processing method, Media Interface Connector controllers.Disclosed method includes：If there is the first order of the first kind for accessing the first logic unit in low priority command queue, take out and handle the first order；During the first order of processing, if there is the second order of the Second Type for accessing the first logic unit in high priority command queue, suspend the processing to the first order, take out and handle the second order；It is completed in response to the second command process, restores the processing to the first order.The Media Interface Connector controller is coupled to one or more NVM chips, and each NVM chips include one or more logic units, are additionally coupled to high priority command queue and low priority command queue, for performing the I/O command processing method.The application is applied to the read operation of solid storage device.
Description
Technical field
This application involves the I/O command processing in technical field of memory more particularly to Media Interface Connector controller.
Background technology
NVM (nonvolatile storage, Non-Volatile Memory) is used to implement store function, has non-volatile spy
Point.Fig. 1 is the block diagram of solid storage device, and solid storage device 102 is coupled with host, for providing storage energy for host
Power.Host can be coupled in several ways between solid storage device 102, coupled modes include but not limited to for example, by
SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI (Small
Computer System Interface, small computer system interface), (Serial Attached SCSI, serially connect SAS
Meet SCSI), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial
Bus, universal serial bus), PCIE (Peripheral Component Interconnect Express, PCIe, it is outer at a high speed
Enclose component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical-fibre channel, cordless communication network etc. even
Connect host and solid storage device 102.Host can be the information processing that can be communicated through the above way with storage device
Equipment, for example, personal computer, tablet computer, server, portable computer, the network switch, router, cellular phone,
Personal digital assistant etc..Storage device 102 include interface 103, control unit 104, one or more NVM chips 105 and
DRAM (Dynamic Random Access Memory, dynamic RAM) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic
Random Access Memory, magnetoresistive memory), RRAM (Resistive RandomAccess Memory, resistance-change memory
Device) etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 passes for data of the control between interface 103, NVM chips 105 and firmware memory 110
It is defeated, it is additionally operable to storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..Control unit
104 can be realized by the various ways of software, hardware, firmware or combination, for example, control unit 104 can be FPGA
(Field-programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form；Control unit 104 can also include place
Device or controller are managed, software is performed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders；Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110；
DRAM can store the data of the I/O command of FTL tables and/or caching.
Memory target (Target) is that the shared chip in the encapsulation of flash memory particle 105 enables (CE, Chip Enable) letter
Number one or more logic units (Logic Unit), each logic unit have logical unit number (LUN, Logic Unit
Number).It may include one or more tube cores (Die) in nand flash memory encapsulation.Typically, logic unit corresponds to single pipe
Core.Logic unit may include multiple planes (Plane).Multiple planes in logic unit can be with parallel access, and nand flash memory
Multiple logic units in chip can perform order and report state independently of one another.
http:What //www.onfi.org/~/media/ONFI/specs/ONFI_3_2%20Gold.pdf was obtained
In " Open NAND Flash Interface Specification (Revision 3.2) ", provide about target
(target), logic unit, LUN, plane (Plane) meaning and also provide operation NVM chips order.
On storage medium usually data are stored and read by page.And data are erased in blocks.Block includes multiple pages.Storage
Page (being known as Physical Page) on medium has fixed size, such as 17664 bytes.Physical Page can also have other rulers
It is very little.It can include multiple data frames (data frame) in Physical Page, data frame has the size specified, such as 4096 or 4416
Byte.
In solid storage device, using FTL (Flash Translation Layer, flash translation layer (FTL)) come safeguard from
Logical address is to the map information of physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits
Store up the memory space of equipment.Physical address is the address for accessing the physical memory cell of solid storage device.In existing skill
Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate
Address is further mapped as physical address.
Wherein, the table structure for storing the map information from logical address to physical address is referred to as FTL tables.FTL tables are
Important metadata in solid storage device.The data item of usual FTL tables is had recorded in solid storage device using data page as list
The address mapping relation of position.
FTL tables include multiple FTL table clauses (or list item).In one example, one is had recorded in each FTL table clauses
The correspondence of a logical page address and a Physical Page.In another example, had recorded in each FTL table clauses continuous
The correspondence of multiple logical page addresses and continuous multiple Physical Page.In another example, recorded in each FTL table clauses
The correspondence of logical block address and physical block address.In still another embodiment, logical block address is recorded in FTL tables
With the mapping relations and/or logical page address of physical block address and the mapping relations of physical page address.
In read command of the processing from host, solid storage device utilizes the logical address that is carried in read command from FTL
Corresponding physical address is obtained in table, and read request is sent out to NVM chips according to physical address, and receive NVM chips in response to
The data of read request output.When handling the write order from host, solid storage device is write order allocated physical address,
In FTL tables record write order logical address with distribution physical address correspondence, and according to distribution physical address to
NVM chips send out write request.
Solid storage device includes multiple NVM chips.Each NVM chips include one or more tube cores (DIE) or patrol
Collect unit (LUN, Logic UNit).Read-write operation can be responded between tube core or logic unit parallel.In same tube core or patrol
Multiple reading and writing or the erasing operation sequence collected on unit perform.
Fig. 2 shows the schematic diagrames of bulk.Bulk includes each physical block from multiple logic units.Preferably,
Each logic unit provides a physical block for bulk.As an example, bulk is constructed on every 16 logic units (LUN).Often
A bulk includes 16 physical blocks, each from 16 logic units (LUN).In the example in figure 2, bulk 0 includes coming
From each physical block 0 of 16 logic units (LUN), and bulk 1 includes the physical block 1 from each logic unit (LUN).
Bulk can also be constructed there are many other modes.
As a kind of optional mode, page band, each interior same physical address of logic unit (LUN) are constructed in bulk
Physical Page constitute " page band ".In Fig. 2, Physical Page 0-0, Physical Page 0-1...... and Physical Page 0-x constitute a page band
0, wherein Physical Page 0-0, Physical Page 0-1...... Physical Page 0-14 are for storing user data, and Physical Page 0-15 is used to deposit
Store up the verification data being calculated according to all customer data in band.Similarly, in Fig. 2, Physical Page 2-0, Physical Page 2-
1...... page band 2 is constituted with Physical Page 2-x.Optionally, page band can be located at for storing the Physical Page of verification data
In any position.
One or more of bulk physical block may be bad block.Data should not be written to bad block.It thus can in page band
The amount of user data of receiving, the bad number of blocks dependent on the bulk where page band.Physical Page includes one or more data sheets
Member.The valid data element number of page band, the quantity of the data cell by user data can be accommodated in finger page band.As act
The Physical Page provided in page band by bad block is removed and removed the Physical Page for storing verification data, remaining object by example
The data cell quantity of page is managed, is the valid data element number of page band.
For data are written to page band, the control unit (104) (referring to Fig. 1) of solid storage device provides verification data meter
Calculate unit.For calculating verification data using xor operation, for including the page band of N+1 Physical Page, to N number of Physical Page
User data calculate exclusive or (for example, (P0-1) XOR (P0-1) XOR (P0-2) XOR...XOR (P0-15)), and by calculate tie
Fruit is written as a page Physical Page (such as P0-X) for band storage verification data.Optionally, it is provided in control unit (104) multiple
Verification data computing unit (for example, M), data are written to M page band simultaneously.
Invention content
In the prior art, read-write operation can be responded between tube core or logic unit parallel, in a storage unit (logic
Unit or tube core etc.), read command, program command and erasing order must be performed serially, although the processing of the read command of flash memory
Delay will be significantly less than the processing delay of program command, but read command such as may need at the programming of same memory cell to be visited
Order or erasing order could be handled after completing.This can cause the processing of read command to postpone to be ordered by program command/erasing
The influence of order causes read command processing delay to rise appreciably.This can also significantly affect service quality.
Although priority processing read command helps to reduce the processing delay of read command relative to program command.However it programs
Order is also required to be deposited to reduce the occupancy of the resource of the verification data to being used to calculate page band and increase solid-state by priority processing
Store up the handling capacity (oncurrent processing ability) of equipment.Resource for calculating the calculating of the verification data of page band includes testing data calculating
Unit and/or XOR cachings.When XOR is buffered in page band write-in data, verification data is calculated.For the page item of N+1 structures
Band after N number of page of data are obtained, can just calculate verification data.Thus start to page band the 1st page data of write-in, school
It is i.e. occupied to test Data Computation Unit, after N page datas are written to page band, verification data computing unit can just calculate
For the N+1 pages of verification data of page band.Thus the quantity of verification data computing unit is limited in solid storage device
The quantity of the program command of concurrent processing.Further, the increase of the delay of program command so that complete the place of page band write-in
Reason delay increases, and further increases the occupancy to verification data computing unit, reduces the concurrent processing energy to program command
Power.
The purpose of the application includes providing I/O command processing method, NVM interface controller, for reducing the processing of I/O command
Delay reduces to the occupancy of processor resource, and improves the oncurrent processing ability of solid storage device.
The first aspect of the present invention provides a kind of I/O command processing method, wherein from high priority command queue or low preferential
Pending I/O command is obtained in grade command queue and relative to the priority processing high priority order of low priority command queue
I/O command in queue, the I/O command processing method include：
If there is the first order of the first kind for accessing the first logic unit in low priority command queue, take out and locate
The first order of reason；
During the first order of processing, if there is access the first logic unit second in high priority command queue
Second order of type suspends the processing to the first order, takes out and handle the second order；
It is completed in response to the second command process, restores the processing to the first order.
The second aspect of the present invention provides a kind of I/O command processing method, wherein from high priority command queue or low preferential
Pending I/O command is obtained in grade command queue and relative to the priority processing high priority order of low priority command queue
I/O command in queue, the I/O command processing method include：
If there is the first order and the Gao You for the first kind for accessing the first logic unit in low priority command queue
There is the second order of the Second Type for accessing the first logic unit in Xian Ji command queues, take out and handle the first order, it will
The first corresponding data of order are sent to the processing of the first logic unit and pause to the first order, take out and handle second
Order；
It is completed in response to the second command process, restores the processing to the first order.
According to the first aspect of the invention or second aspect, provide according to a first aspect of the present invention or second aspect
The order of one I/O command processing method, the wherein first kind first is program command, and the second order of Second Type is read command.
According to the first aspect of the invention, the second I/O command processing method according to the first aspect of the invention is provided,
It further includes：During the first order of processing, accessed except the first logic unit if existing in high priority command queue
During the order of other logic units, the processing to the first order is not suspended, processing accesses the order of other logic units.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
Third I/O command processing method, further includes：I/O command is put into high priority command queue or low preferential according to I/O command type
Grade command queue.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
4th I/O command processing method, wherein read command is put into high priority command queue, by program command, erasing order or should not
The read command that processing postpones is asked to be put into low priority command queue.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
5th I/O command processing method is being handled when having in read command pending in high-priority queue, the first logic unit
Program command or during erasing order, if read command accesses the first logic unit, suspend the program command handled or wiping
Read command is taken out except order and from high priority command queue and is handled；And completed in response to being handled in read command, it is extensive
The multiple processing to program command or erasing order.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
6th I/O command processing method if pending read command in high priority command queue, has in low priority command queue
Program command in low priority command queue or erasing order are taken out and located by pending program command or erasing order
Reason；And if read command accesses the first logic unit with program command or erasing order, suspends to program command or erasing
The processing of order is taken out read command and is handled from high priority command queue；And completed in response to the processing of read command, it is extensive
The multiple processing to program command or erasing order.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
N+P Physical Page in 7th I/O command processing method, wherein N+P logic unit forms page band, and N pages is stored in page band
User data and the P pages of verification data being calculated by the N pages of user data, N, P are the positive integer more than or equal to 1.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
8th I/O command processing method, buffer memory are used for the verification data of first page band, and the I/O command processing method further includes：
In response to being taken out from low priority command queue and handling program command, the corresponding data of program command are stored together
Data carry out exclusive or, exclusive or result store in the buffer.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
9th I/O command processing method, if storing the exclusive or result of N pages of user data in first page band in caching；By the school of caching
Test data write-in first page band；And discharge the caching.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
Tenth I/O command processing method, further includes：The verification data of caching is stored to DRAM；And discharge the caching.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
11st I/O command processing method, further includes：In response to continuing to write to data to first page band, caching is redistributed, and
Verification data associated with first page band is transferred in caching from DRAM, the corresponding user data of program command is same
Data in caching carry out exclusive or, and will be in the storage to the caching of exclusive or result；And program command is sent to logic unit.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
12nd I/O command processing method, further includes：If caching in store N pages of user data in first page band exclusive or as a result,
The verification data of caching is sent to the logic unit corresponding to P Physical Page of page band；By the data in caching store to
DRAM：And discharge the caching.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
13rd I/O command processing method, if to the write-in verification data error of one of P Physical Page, it will be with first page band from DRAM
Associated verification data is stored to caching.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
14th I/O command processing method, further includes：Distribute page band；And distribution caching.
According to the first aspect of the invention or second aspect, it provides according to the first aspect of the invention or second aspect
15th I/O command processing method, in response to whole user data are written to first page band, by the check number of this page of band
According to P Physical Page of write-in page band；And release caching.
The difference that same logic unit will be accessed due to the command scheduling method of the first aspect of the present invention and second aspect
The I/O command of type has been respectively put into high priority command queue and low priority command queue, and according to the preferential of command queue
Grade and order different conditions in execution, set up corresponding command process mechanism, on the one hand when the mistake of the first order of processing
Cheng Zhong if there is the second order of the Second Type for accessing the first logic unit in high priority command queue, suspends to first
The processing of order takes out and handles the second order；If on the other hand exist in low priority command queue and access the first logic list
There is the Second Type of the first logic unit of access in first order of the first kind of member and high priority command queue
Second order, takes out and handles the first order, and the corresponding data of the first order are sent to the first logic unit and pause pair
The processing of first order, takes out and handles the second order；Read command is solved by the influence of program command/erasing order and
Caused by handle delay the problem of, but also program command obtains priority processing, so as to reduce the occupancy to resource, and increase
The handling capacity of solid storage device (oncurrent processing ability).
The third aspect of the present invention provides a kind of Media Interface Connector controller, the Media Interface Connector controller be coupled to one or
Multiple NVM chips, each NVM chips include one or more logic units；The Media Interface Connector controller is additionally coupled to Gao You
Xian Ji command queues and low priority command queue, if there is access the first logic unit first in low priority command queue
During the first order of type, the Media Interface Connector controller takes out from low priority command queue and handles the first order；When
During the first order of processing, if there is the second order for accessing the first logic unit in high priority command queue, institute
Processing of the matter interface controller pause to the first order is given an account of, takes out and handles the second order；And in response to the second order at
Reason is completed, and the Media Interface Connector controller restores the processing to the first order.
The fourth aspect of the present invention provides a kind of Media Interface Connector controller, the Media Interface Connector controller be coupled to one or
Multiple NVM chips, each NVM chips include one or more logic units；The Media Interface Connector controller is additionally coupled to Gao You
Xian Ji command queues and low priority command queue, if there is access the first logic unit first in low priority command queue
There is the second life of the Second Type for accessing the first logic unit in first order of type and high priority command queue
It enables, the Media Interface Connector controller takes out from low priority command queue and handles the first order, and the first order is corresponded to
Data be sent to the first logic unit and pause to first order processing, take out and handle the second order；And response
It is completed in the second command process, the Media Interface Connector controller restores the processing to the first order.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
I/O command in first medium interface controller, wherein high priority command queue and low priority command queue respectively has not
Same type.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
Second medium interface controller, if there are other logic units accessed except the first logic unit in high priority command queue
Order when, the Media Interface Connector controller do not suspend to first order processing, processing access other logic units order.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
Third Media Interface Connector controller, the I/O command of high priority command queue is read command；IO lives in low priority command queue
It enables as program command, erasing order or the read command that processing is not required to postpone.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
4th Media Interface Connector controller is being handled when having in read command pending in high-priority queue, the first logic unit
Program command or during erasing order, if read command accesses the first logic unit, the Media Interface Connector controller is specifically used for, temporarily
Stop the program command handled or erasing order and read command is taken out from high priority command queue and is handled；And
It is completed in response to being handled in read command, restores the processing to program command or erasing order.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
5th Media Interface Connector controller if pending read command in high priority command queue, has in low priority command queue
Pending program command or erasing order, the Media Interface Connector controller are used for, by the programming in low priority command queue
Order or erasing order are taken out and are handled；And if read command and program command or erasing order access the first logic unit,
Then processing of the pause to program command or erasing order is taken out read command and is handled from high priority command queue；And it rings
It should be completed in the processing of read command, restore the processing to program command or erasing order.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
6th Media Interface Connector controller further includes verification data calculator and at least one caching, wherein caching is for storage first
The verification data of page band；In response to being taken out from low priority command queue and handling program command, verification data calculator
The corresponding data of program command are subjected to exclusive or with stored data are cached, exclusive or result stores in the buffer.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
N+p Physical Page in 7th Media Interface Connector controller, wherein N+P logic unit forms page band, and N pages is stored in page band
User data and the P pages of verification data being calculated by the N pages of user data, N, P are the positive integer more than or equal to 1.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
8th Media Interface Connector controller, if storing the exclusive or of N pages of user data in first page band as a result, the medium connects in caching
First page band is written in the verification data of caching by mouth controller；And discharge the caching.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
9th Media Interface Connector controller, Media Interface Connector controller are additionally coupled to DRAM, and the Media Interface Connector controller is by the verification of caching
Data are stored to DRAM；And discharge the caching.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
Tenth Media Interface Connector controller, in response to continuing to write to data to first page band, the Media Interface Connector controller is redistributed
Caching, and verification data associated with first page band is transferred in caching from DRAM；The verification data calculator
The corresponding user data of program command is subjected to exclusive or, and will be in the storage to the caching of exclusive or result with the data in caching；With
And program command is sent to logic unit by the Media Interface Connector controller.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
11st Media Interface Connector controller, if storing the exclusive or of N pages of user data in first page band as a result, the medium in caching
The verification data of caching is sent to the logic unit corresponding to P Physical Page of page band by interface controller；It and will caching
In data store to DRAM；And discharge the caching.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
Tenth second medium interface controller, if to the write-in verification data error of one of P Physical Page, the Media Interface Connector controller from
Verification data associated with first page band is stored to caching in DRAM.
According to the third aspect of the invention we or fourth aspect, it provides according to the third aspect of the invention we or fourth aspect
13rd Media Interface Connector controller, in response to whole user data, the Media Interface Connector controller is written to first page band
By P Physical Page of the verification data write-in page band of this page of band；And release caching.
The fifth aspect of the present invention provides a kind of Media Interface Connector controller, and the Media Interface Connector controller, which is coupled to one, patrols
Unit is collected, the Media Interface Connector controller is additionally coupled to high priority command queue and low priority command queue, if low preferential
When there is the first order of the first kind for accessing the logic unit in grade command queue, the Media Interface Connector controller is from low
It is taken out in priority command queue and handles the first order；During the first order of processing, if high priority command queue
Middle when there is the second order for accessing the logic unit, processing of the Media Interface Connector controller pause to the first order takes
Go out and handle the second order；And completed in response to the second command process, the Media Interface Connector controller restores to order first
Processing.
The sixth aspect of the present invention provides a kind of Media Interface Connector controller, and the Media Interface Connector controller, which is coupled to one, patrols
Unit is collected, the Media Interface Connector controller is additionally coupled to high priority command queue and low priority command queue, if low preferential
Exist in grade command queue and deposited in the first order of the first kind for accessing the logic unit and high priority command queue
In the second order for accessing the Second Type of the logic unit, the Media Interface Connector controller is from low priority command queue
It takes out and handles the first order, and the corresponding data of the first order are sent to the logic unit and pause to the first life
The processing of order takes out and handles the second order；And completed in response to the second command process, the Media Interface Connector controller restores
Processing to the first order.
According to the fifth aspect of the invention or in terms of the 6th, provide according to the fifth aspect of the invention or in terms of the 6th
I/O command in first medium interface controller, wherein high priority command queue and low priority command queue respectively has not
Same type.
According to the fifth aspect of the invention or in terms of the 6th, provide according to the fifth aspect of the invention or in terms of the 6th
Second medium interface controller, the Media Interface Connector controller are additionally coupled to verification data calculator and at least one caching,
Wherein cache the verification data for storing first page band；The verification data calculator is used for, in response to from low priority
It is taken out in command queue and handles program command, the corresponding data of program command are subjected to exclusive or with stored data are cached,
Exclusive or result stores in the buffer.
According to the fifth aspect of the invention or in terms of the 6th, provide according to the fifth aspect of the invention or in terms of the 6th
Third Media Interface Connector controller, the Media Interface Connector controller are additionally coupled to DRAM, will be programmed for working as verification data calculator
Corresponding data is ordered to carry out exclusive or with stored data are cached, and by after the storage in the buffer of exclusive or result, pass through medium
The verification data of caching is stored into DRAM and discharged the caching by interface controller.
The seventh aspect of the present invention provides a kind of solid storage device, and the solid storage device includes host interface, control
Component processed, DRAM and one or more NVM chips, control unit are used between control interface, NVM chips and firmware memory
Data transmission, the control unit further includes one or more such as third aspect present invention and fourth aspects and its possible
Media Interface Connector controller described in embodiment.
The eighth aspect of the present invention provides a kind of solid storage device, and the solid storage device includes host interface, control
Component processed, DRAM and one or more NVM chips, each NVM chips include one or more logic units, and control unit is used
In data transmission of the control between interface, NVM chips and firmware memory, the control unit further includes one or more such as
Media Interface Connector controller and check number described in fifth aspect present invention and the 6th aspect and its possible embodiment
According to calculator, the verification data calculator is coupled with one or more Media Interface Connector controllers, for input data
Make exclusive or to obtain verification data.
The ninth aspect of the present invention provides a kind of computer readable storage medium including program, when described program is loaded into
Solid storage device and when being performed on the controller of solid storage device, said program code make the controller perform such as this
I/O command processing method described in invention first aspect and second aspect and its possible embodiment.
The tenth aspect of the present invention provides a kind of solid storage device, and the storage device includes one or more processors
With storage, one or more of processors are performed by the program in run memory such as first aspect present invention and second
I/O command processing method described in aspect and its possible embodiment.
The eleventh aspect of the present invention provides a kind of I/O command processing method, which includes：In response to
The verification data of page band, which calculates, to be completed, by the verification data storage in caching to external memory, generation interrupt signal R_
CPL to indicate the caching releasably distributed by the page band, and indicates the storage address of verification data；And in response to
It is completed to the write operation of page band write-in verification data, interrupt signal P_CPL is generated, to indicate in releasable external memory
Verification data.
The twelveth aspect of the present invention provides a kind of I/O command processing method, which includes：It will be to patrolling
The program command for collecting unit write-in data is sent to Media Interface Connector controller；In response to receiving interrupt signal R_CPL, generation programming
Page band is written in verification data in external memory indicated by interrupt signal R_CPL by order, and indicates to be institute
The program command of generation calculates verification data；And in response to receiving interrupt signal P_CPL, if interrupt signal P_CPL is indicated
Write operation success, abandons the verification data in external memory.
According to the twelfth aspect of the invention, the first I/O command processing side according to the twelfth aspect of the present invention is provided
Method, if interrupt signal P_CPL instruction write operation failures, generate the second program command, by the check number in external memory
According to write-in page band, and indicate to calculate verification data without the second program command to be generated.
According to the twelfth aspect of the invention, the second I/O command processing side according to the twelfth aspect of the present invention is provided
Method, if interrupt signal P_CPL instruction write operation failures, read the data being written into page band, and generate programming life
It enables the data read from page band another page band and generation program command is written by the verification in external memory
Another page of band is written in data, and indicates to calculate verification data without the program command to be generated.
According to the twelfth aspect of the invention, the third I/O command processing side according to the twelfth aspect of the present invention is provided
Method, in response to receiving interrupt signal R_CPL, the caching indicated by release interrupt signal R_CPL.
According to the twelfth aspect of the invention, the 4th I/O command processing side according to the twelfth aspect of the present invention is provided
Method in response to application to the second caching, will be sent to Media Interface Connector control to the second program command of logic unit write-in data
Device, the program command instruction calculate verification data using the second caching for the second program command.
According to the twelfth aspect of the invention, the 5th I/O command processing side according to the twelfth aspect of the present invention is provided
Method in response to receiving interrupt signal R_CPL, ignores interrupt signal R_CPL.
The thirteenth aspect of the present invention provides a kind of I/O command processing method, wherein being used for the school of page band with buffer memory
Data are tested, which includes：In response to the program command of user data is written to page band, by program command pair
The user data answered carries out exclusive or with the data in caching, and exclusive or result stores in the buffer；And program command is sent to
Corresponding logic unit.
According to the thirteenth aspect of the invention, the first I/O command processing side according to the 13rd aspect of the present invention is provided
Method calculates completion in response to all verification datas of page band, will verify data transmission to external memory, and generate interrupt signal
R_CPL, and interrupt signal R_CPL is sent to CPU.
According to the thirteenth aspect of the invention, the second I/O command processing side according to the 13rd aspect of the present invention is provided
Method further includes：In response to interrupt signal R_CPL, program command is generated, page item is written into the verification data in external memory
Band, and indicate to calculate verification data without the program command to be generated.
According to the thirteenth aspect of the invention, the third I/O command processing side according to the 13rd aspect of the present invention is provided
Method, in response to interrupt signal P_CPL, if interrupt signal P_CPL instruction write operation successes, abandon the school in external memory
Test data.
According to the thirteenth aspect of the invention, the 4th I/O command processing side according to the 13rd aspect of the present invention is provided
Method,, will if interrupt signal P_CPL instruction write operation failures, generate the second program command in response to interrupt signal P_CPL
Verification data write-in page band in external memory, and indicate to calculate check number without the second program command to be generated
According to.
According to the thirteenth aspect of the invention, the 5th I/O command processing side according to the 13rd aspect of the present invention is provided
Method, if interrupt signal P_CPL instruction write operation failures, read the data being written into page band, and generate programming life
It enables the data read from page band another page band and generation program command is written by the verification in external memory
Another page of band is written in data, and indicates to calculate verification data without the program command to be generated.
According to the thirteenth aspect of the invention, the 6th I/O command processing side according to the 13rd aspect of the present invention is provided
Method, in response to receiving interrupt signal R_CPL, it is other that the caching indicated by interrupt signal R_CPL, which can be released or distribute,
Page band generation verification data, and record the address indicated by R_CPL.
Since the I/O command processing method of the eleventh aspect of the present invention to 13 aspect offers is by responding interrupt signal
Carry out the executive process of control command, wherein, completion is calculated in response to all verification datas of page band, verification data transmission is arrived
External memory, and generate interrupt signal R_CPL；In response to receiving interrupt signal R_CPL, program command is generated by interrupt signal
Verification data write-in page band in external memory indicated by R_CPL；In response to writing to page band write-in verification data
Enter operation to complete, generate interrupt signal P_CPL, in response to receiving interrupt signal P_CPL, if interrupt signal P_CPL instructions are write
Enter to operate successfully, abandon the verification data in external memory.So that release caching that can be earlier when page band is written is simultaneously
The caching of release is distributed into other program commands, and can concurrently perform more program commands in solid storage device, into
And limited cache resources are reduced to concurrently performing the limitation of the quantity of program command, it decreases program command and waits for resource
Probability, reduce the processing delay of program command, improve the performance of solid storage device.
The fourteenth aspect of the present invention provides a kind of Media Interface Connector controller, and the Media Interface Connector controller includes high preferential
Grade command queue and low priority command queue, Media Interface Connector controller are coupled to one or more logic units, Media Interface Connector
Controller is additionally coupled to verification data calculator and caching, carries out exclusive or for user data corresponding to program command to obtain
To verification data, and will be in the storage to caching of exclusive or result；Media Interface Connector controller is additionally coupled to CPU and external memory；School
It tests data calculator and is also coupled to CPU and external memory, data are exchanged and into CPU instructions for same external memory
Break signal.
According to the fourteenth aspect of the invention, the first medium Interface Controller according to fourteenth aspect of the present invention is provided
Device, wherein the verification data in response to page band calculates completion, during Media Interface Connector controller or verification data calculator will cache
Verification data storage to external memory, interrupt signal R_CPL is generated, to indicate that releasably the page band is distributed
Caching, and indicate the storage address of verification data；And in response to being completed to the write operation of page band write-in verification data, it is situated between
Matter interface controller or verification data calculator generation interrupt signal P_CPL, to indicate the verification in releasable external memory
Data.
According to the fourteenth aspect of the invention, the second medium Interface Controller according to fourteenth aspect of the present invention is provided
Device, in response to the program command of page band write-in user data, verification data calculator is by the corresponding number of users of program command
Exclusive or is carried out according to the data in same caching, exclusive or result stores in the buffer；And Media Interface Connector controller sends out program command
Give corresponding logic unit.
According to the fourteenth aspect of the invention, it provides and is controlled according to the third Media Interface Connector of fourteenth aspect of the present invention
Device calculates completion in response to the verification data of page band, and Media Interface Connector controller or verification data calculator pass verification data
It is defeated to arrive external memory, interrupt signal R_CPL is generated, and interrupt signal R_CPL is sent to CPU.
According to the fourteenth aspect of the invention, it provides and is controlled according to the 4th Media Interface Connector of fourteenth aspect of the present invention
Device, in response to interrupt signal R_CPL, page band is written in the verification data in external memory by CPU generation program commands, and
And instruction calculates verification data without the program command to be generated.
According to the fourteenth aspect of the invention, it provides and is controlled according to the 5th Media Interface Connector of fourteenth aspect of the present invention
Device, in response to interrupt signal P_CPL, if interrupt signal P_CPL instruction write operation successes, CPU are abandoned in external memory
Verification data.
According to the fourteenth aspect of the invention, it provides and is controlled according to the 6th Media Interface Connector of fourteenth aspect of the present invention
Device, in response to interrupt signal P_CPL, if interrupt signal P_CPL instruction write operation failures, CPU generate the second program command,
Page band is written into verification data in external memory, and indicates to calculate verification without the second program command to be generated
Data.
According to the fourteenth aspect of the invention, it provides and is controlled according to the 7th Media Interface Connector of fourteenth aspect of the present invention
Device, if interrupt signal P_CPL instruction write operation failures, CPU reads the data being written into page band, and generates programming
It orders the data read from page band another page band and generation program command is written by the school in external memory
It tests data and another page of band is written, and indicate to calculate verification data without the program command to be generated.
According to the fourteenth aspect of the invention, it provides and is controlled according to the 8th Media Interface Connector of fourteenth aspect of the present invention
Device, in response to receiving interrupt signal R_CPL, it is other that the caching indicated by interrupt signal R_CPL, which can be released or distribute,
Page band generation verification data, and record the address indicated by R_CPL.
The fifteenth aspect of the present invention provides a kind of solid storage device, the solid storage device include host interface,
Control unit, external memory and one or more NVM chips, control unit is for control in interface, NVM chips and firmware
Data transmission between memory, NVM chip include one or more logic units, the control unit include one or
Multiple Media Interface Connector controllers as described in claim 15-23, one or more Media Interface Connector controllers are additionally coupled to
Verification data calculator and caching, for obtaining verification data to input data progress exclusive or.
The sixteenth aspect of the present invention provides a kind of program including instruction code, when be loaded into solid storage device and
When being performed on the controller of solid storage device, said program code makes the controller perform such as the tenth one side of the invention extremely
The method of processing I/O command described in 13 aspects and its possible embodiment.
The seventeenth aspect of the present invention provides a kind of solid storage device, and the solid storage device includes one or more
Processor is performed by the program in run memory such as the tenth one side to ten with storage, one or more of processors
The method of processing I/O command described in three aspects and its possible embodiment.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the schematic diagram of solid storage device of the prior art；
Fig. 2 is the organigram of page band；
Fig. 3 is the schematic diagram of the control unit of the solid storage device in the embodiment of the present invention one；
Fig. 4 is the schematic diagram of the Media Interface Connector controller in the embodiment of the present invention two；
Fig. 5 is the schematic diagram of the Media Interface Connector controller in the embodiment of the present invention three；
Fig. 6 is the flow chart of the I/O command processing in the embodiment of the present invention four；
Fig. 7 is the schematic diagram of the Media Interface Connector controller in the embodiment of the present invention five；And
Fig. 8 is the flow chart of the I/O command processing in the embodiment of the present invention six.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is part of the embodiment of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, the every other implementation that those of ordinary skill in the art are obtained without making creative work
Example, shall fall within the protection scope of the present invention.
Embodiment one
Fig. 3 is the block diagram of the control unit of solid storage device according to embodiments of the present invention.The control of solid storage device
Component 104 processed includes host interface 310, front end processing block 320, flash memory management module 330 and one or more media
Interface controller 340.Host interface 310 is used for host exchange command and data.Flash memory management module 330 provides logical address
To functions such as physical address map, abrasion equilibrium, garbage reclamations, and generate I/O command and be sent to Media Interface Connector controller 340.It is situated between
Matter interface controller is coupled to NVM chips 105.There are one Media Interface Connector controllers or multiple, and each interface controller is coupled to
Respective NVM chips 105.Media Interface Connector controller receive I/O command, and according to I/O command to NVM chips send out I/O command (read,
Programming, pause, reads the orders such as feature (feature) and/or setting feature at erasing).
In one example, Media Interface Connector controller provide with different priorities multiple queues (such as queue 342 with
Queue 344, wherein queue 342 is high-priority queue and queue 344 is Low Priority Queuing) receive I/O command.Flash memory pipe
The high-priority queue of interface controller is inserted in read command by reason module 330, makes Media Interface Connector controller priority processing read command.
And Media Interface Connector control is inserted into program command, erasing order and/or read command (such as read command that processing is not required to postpone)
The Low Priority Queuing of device.Order in Media Interface Connector controller meeting priority processing high-priority queue 342, and with low priority
Handle the order in queue 344.It is to be appreciated that other kinds of I/O command can also be inserted high priority by flash memory management module
Queue.
According to an embodiment of the invention, under normal circumstances, in Media Interface Connector controller priority processing high-priority queue
I/O command, and the I/O command in Low Priority Queuing is handled with low priority.
According to one embodiment of present invention, in order to reduce the processing of the I/O command of solid storage device delay, if patrolling
Collecting on unit (L1) has the program command (P1) being carrying out or erasing order (E1), and to be handled in high-priority queue
Read command (R1).It should be pointed out that logic unit (L1) identical with program command P1 access read command R1.Then medium connects
Mouthful controller sends out pause command to logic unit (L1), the processing of pause program command (P1) or erasing order (E1) and
Handle read command (R1).And after the completion of read command (R1) processing, recovery order is sent out to logic unit (L1), is restored to compiling
Journey order (P1) or the processing of erasing order (E1).
It is to be appreciated that the I/O command in high-priority queue/Low Priority Queuing is ordered with being sent to the IO of logic unit
Different forms can be had by enabling, but with identical label (R1, P1, E1 etc.) instruction in different phase, have different shape but
The identical same order of meaning.
According to still another embodiment of the invention, Media Interface Connector controller is found pending in high-priority queue
Read command (R2), and the pending program command (P2) in Low Priority Queuing.Media Interface Connector controller is not first to handle
Read command (R2), but first handle the program command (P2) in Low Priority Queuing.Programming life is being sent out to logic unit (L2)
After enabling (P2), if the logic unit (L2) that read command (R2) is identical with program command (P2) access, and then to logic unit
(L2) pause command is sent out, to suspend the processing to program command (P2).And the processing of Media Interface Connector controller is from high preferential
The read command (R2) of grade queue sends out read command (R2) to logic unit (L2), and after the completion of read command (R2) processing, to patrolling
It collects unit (L2) and sends out recovery order, to restore the processing to program command (P2).If read command (R2) and program command (P2)
Different logic units is accessed, then directly processing read command (R2), without suspending program command (P2).
According to another embodiment of the present invention, Media Interface Connector controller finds pending reading life in high-priority queue
It enables (R3), and the pending erasing order (E3) in Low Priority Queuing.Media Interface Connector controller is not that first life is read in processing
It enables (R3), but first handles the erasing order (E3) in Low Priority Queuing.Erasing order is being sent out to logic unit (L3)
(E3) after, if the logic unit (L3) that read command (R3) is identical with erasing order (E3) access, and then to logic unit
(L3) pause command is sent out, to suspend the processing to erasing order (E3).And the processing of Media Interface Connector controller is from high preferential
The read command (R3) of grade queue sends out read command (R3) to logic unit (L3), and after the completion of read command (R3) processing, to patrolling
It collects unit (L3) and sends out recovery order, to restore the processing to erasing order (E3).If read command (R3) and erasing order (E3)
Different logic units is accessed, then directly processing read command (R3), without suspending erasing order (E3).Further, if connecing
Programming (P4)/erasing (E4) order got off in Low Priority Queuing and occur accessing other logic units is (different from logic
Other logic units of unit L3), there is read command (R4) in high-priority queue, then perform programming (P4)/erasing (E4)
Order and pause programming (P4)/erasing (E4) order, next perform read command (R4) and recovering programming (P4)/erasing
(E4) processing of order.
Optionally, each logic unit has the execution state of corresponding Media Interface Connector controller or Media Interface Connector controller,
I/O command so as to handled by same Media Interface Connector controller accesses identical logic unit.In the case, medium connects
Mouth controller need not judge whether read command accesses identical logic unit with program/erase order, and perform programming/wiping
Except it is rear and from high-priority queue receive read command when, all send out pause command to logic unit, with pause to program/erase order
The processing of order.Then read command is sent out, and after the completion of read command execution, the execution of recovering programming/erasing order.
Embodiment two
Fig. 4 is the block diagram of Media Interface Connector controller 440 according to embodiments of the present invention.Media Interface Connector controller includes multiple
Queue (for example, queue 342 and queue 344).Each queue has different priority, such as queue 342 is high priority team
Row, and queue 344 is Low Priority Queuing.Media Interface Connector controller 440 includes command scheduling module 410, verification data calculates
Device 420.As an example, XOR cachings (422/424/426), verification data calculator are further included in verification data calculator 420
420 pairs of input datas cache the data in (422/424/426) with XOR and do exclusive or to obtain verification data, the school being calculated
Data are tested to be stored in XOR cachings (422/424/426).
Optionally, Media Interface Connector controller 440 is additionally coupled to DRAM (referring to Fig. 1, DRAM 110).
Command scheduling module 410 takes out order from queue 342/344, and performs order to access NVM chips.For compiling
Journey order during the corresponding data of program command are sent to NVM chips, specifies XOR cachings (for example, XOR is cached
422), to program command, corresponding data are cached with XOR cachings (for example, XOR caching 422) verification data calculator 420
Data perform xor operation, and the result of xor operation is stored in XOR cachings (for example, XOR cachings 422).
As an example, NVM chips 405/415/425 it is each on one Physical Page of distribution construct a page band (S1).
2 Physical Page in page band (S1) are for storing user data, and 1 Physical Page is used to store verification data.
Command scheduling module 410 obtains program command (P5) from command queue, and distribution XOR cachings (422) order programming
The data of (P5) is enabled to do exclusive or with XOR cachings (422), result of calculation is stored in XOR cachings (422) and by program command
(P5) NVM chips 405 are sent to.
Next, command scheduling module 410 obtains program command (P7) from command queue, distribution XOR caches (426),
The data of program command (P7) are done into exclusive or with XOR cachings (426), result of calculation is stored in XOR cachings (426) and will
Program command (P7) is sent to NVM chips 435.
Wherein, data are written to page band (S1) in program command (P5), and before page band (S1) is by complete be written, XOR
Caching (422) is occupied to be generated for the verification data of page band (S1).Similarly, program command (P7) is to page band (S2)
Data are written, XOR cachings (426) are occupied to be generated for the verification data of page band (S2).
Next, occurring read command (R5) in high-priority queue, and occurs program command in Low Priority Queuing
(P6).Although the priority of read command (R5) is higher than program command (P6), in order to reduce the holding time to XOR cachings (422),
Data are written to page band (S1) in 410 priority processing program command (P6) of command scheduling module, program command (P6).Programming is ordered
(P6) corresponding data is enabled to do exclusive or with XOR cachings (422), exclusive or result is stored in XOR cachings (422).And it will compile
Journey order (P6) is sent to NVM chips 415.
At this point, all user data of page 2 of a page band (S1) to be written due to having had received, XOR is cached in (422)
The data of storage as page band (S1) verification data and NVM chips 425 (by generating program command PX5) are written, and release
Put XOR cachings (422).
In an embodiment according to the present invention, the corresponding data of program command (P6) are done into exclusive or with XOR cachings (422),
After exclusive or result is stored in XOR cachings (422), command scheduling module 410 handles the reading from high-priority queue 342
It orders (R5).If there is the program command handled (for example, program command in the logic unit (L5) that read command (R5) is accessed
P6/P7/PX5) or erasing order, pause command is sent out to logic unit (L5), is carrying out in pause logic unit (L5)
Program command or erasing order send out read command (R5) to logic unit (L5), after the completion of read command (R5) execution, to logic
Unit (L5) sends out recovery order, to restore the program command being suspended or erasing order.
Optionally, the corresponding data of program command are done into exclusive or, exclusive or result with XOR cachings (for example, XOR cachings 422)
XOR cachings (for example, XOR caching 422) are stored in, and after program command is sent to logic unit, XOR is cached (422)
Content (for example, user data or verification data for page band (S1)) the write-in DRAM of storage is (referring to Fig. 1, DRAM
110), so as to which releasable XOR caches (422), and XOR is cached into (422) distribution to calculate another page of band (for example, page band
(S3)) verification data.And it in response to receiving the program command to page band (S1) write-in data, obtains and is deposited from DRAM
The content of the XOR cachings (422) of storage, and store to XOR and cache (for example, 422/426), and continue with and write to page band (S1)
Enter the program command of data.
Embodiment three
Fig. 5 illustrates the Media Interface Connector controller of further embodiment of this invention.In the embodiment of Fig. 5, control unit 104
(referring to Fig. 1) includes multiple Media Interface Connector controllers (540/550).Media Interface Connector controller includes multiple queues (for example, queue
542/544,552/554).Each queue has different priority, such as queue 542/552 is high-priority queue, and team
Row 544/554 are Low Priority Queuings.Media Interface Connector controller 540/550 is coupled to verification data calculator 520.As act
Example, verification data calculator 520 do input data exclusive or to obtain verification data, are also wrapped in verification data calculator 520
Include XOR cachings (522/524/526).
Optionally, Media Interface Connector controller 540/550 is additionally coupled to DRAM (referring to Fig. 1, DRAM 110).
Wherein, Media Interface Connector controller 540 is exclusively used in accessing logic unit (LUN 505), and Media Interface Connector controller 550 is special
For accessing logic unit (LUN 515).Thus, to access LUN 505, will corresponding order addition queue 542/544 and
To access LUN 515, corresponding order is added to queue 552/554.
It is to be appreciated that can store multigroup execution state in Media Interface Connector controller, every group of execution state is exclusively used in accessing
One of logic unit.It is switched over by the execution state to Media Interface Connector controller so that at each moment, Media Interface Connector control
Device processed is exclusively used in accessing (one) logic unit corresponding with current execution state.
In the 5 embodiment of figure 5, multiple Media Interface Connector controllers (540/550) share verification data calculator 520, also altogether
Enjoy DRAM.
As an example, in response to processing program command (P10), data are written to page band (S10) in program command (P10).
Media Interface Connector controller 540 distributes XOR for program command (P10) and caches (522), and the corresponding data of program command (P10) are same
XOR cachings (522) do exclusive or, and exclusive or result is stored in XOR cachings (522) and is sent to program command (P10)
LUN 505。
Next, occurs pending read command (R10) on high-priority queue 542.Due to Media Interface Connector controller 540
It is exclusively used in accessing logic unit (LUN 505), thus implys that read command (R10) all accesses logic list with program command (P10)
First (LUN 505).Media Interface Connector controller 540 finds that program command (P10) just performs on LUN 505, to reduce read command
(R10) processing delay, pause command is sent out to LUN 505, the execution of pause program command (P10), and by read command (R10)
It is sent to LUN505.And completion is performed in response to read command (R10), recovery order is sent out to LUN 505, is ordered with recovering programming
Enable the execution of (P10).
Next, occurring pending read command (R11) on high-priority queue 542, occur on Low Priority Queuing 544
Pending program command (P11).And program command (P10) executed is completed.Since Media Interface Connector controller 540 is exclusively used in
Logic unit (LUN 505) is accessed, thus implys that read command (R11) all accesses logic unit (LUN with program command (P11)
505) whether the order that, media access controller 540 is checked and accepted without examining again accesses identical logic unit.Although read command
(R11) priority is higher than program command (P11), but 540 priority processing program command (P11) of media access controller.Programming
(P11) is ordered for data to be written to page band (S11).Media Interface Connector controller 540 distributes XOR for program command (P11) and delays
(524) are deposited, the corresponding data of program command (P11) are done into exclusive or with XOR cachings (524), exclusive or result is stored in XOR cachings
(524) LUN 505 is sent in and by program command (P11).Next, media access controller 540 is sent out to LUN 505
Go out pause command, the execution of pause program command (P11), and read command (R11) is sent to LUN 505.And in response to reading
Order (R11) performs completion, recovery order is sent out to LUN 505, with the execution of recovering programming order (P11).
Next, in response to occurring pending read command (R12), Low Priority Queuing 554 on high-priority queue 552
It is upper pending program command (P12) occur, since Media Interface Connector controller 550 is exclusively used in accessing logic unit (LUN 515),
Thus imply that read command (R12) all accesses logic unit (LUN 515), media access controller 550 with program command (P12)
Whether the order checked and accepted without examining again accesses identical logic unit.Even if the priority of read command (R12) is ordered higher than programming
It enables (P12), also priority processing program command (P12) of media access controller 550.Program command (P12) is for page band
(S12) data are written.Media Interface Connector controller 550 distributes XOR for program command (P12) and caches (526), by program command
(P12) corresponding data do exclusive or with XOR cachings (526), and exclusive or result is stored in XOR cachings (526) and will programming
Order (P12) is sent to LUN 515.Next, media access controller 550 sends out pause command, pause programming to LUN 515
The execution of (P12) is ordered, and read command (R12) is sent to LUN 515.And completion is performed in response to read command (R12), to
LUN515 sends out recovery order, with the execution of recovering programming order (P12).
Next, in response to occurring pending read command (R13), Low Priority Queuing 554 on high-priority queue 552
It is upper pending program command (P13) occur, even if the priority of read command (R13) is higher than program command (P13), medium access
Also priority processing program command (P13) of controller 550.Program command (P13) for page band (S14) be written data.Medium
Interface controller 550 distributes XOR cachings for program command (P13).It, will since XOR cachings (522/524/526) are occupied
The content transmission that one of XOR cachings (for example, XOR caching 526) is stored is to DRAM.XOR cachings (526) are initialized, will be programmed
The corresponding data of order (P13) do exclusive or with XOR cachings (526), and exclusive or result is stored in XOR cachings (526) and will
Program command (P13) is sent to LUN 515.Next, media access controller 550 sends out pause command to LUN 515, pause
The execution of program command (P13), and read command (R13) is sent to LUN 515.And it is performed in response to read command (R13)
Into, to LUN 515 send out recovery order, with the execution of recovering programming order (P13).
Next, no matter Media Interface Connector controller 540/550 which receive to page band (S12) write-in data programming
Order, the storage information for page band (S12) that XOR is all cached to (526) are transmitted in DRAM, and obtain it from DRAM
The content that preceding the stored XOR for page band (S12) is cached, and store into XOR cachings (526).
Example IV
Fig. 6 illustrates the flow chart of the I/O command processing method of the embodiment of the present invention, for embodiment two and embodiment three
In Media Interface Connector controller processing queue in I/O command.
In one example, the processing of read command is postponed in order to reduce program command, Media Interface Connector controller response life
Enable queue (such as queue 342/344 of Fig. 4, the queue 542/544 of Fig. 5) pending order.If in high-priority queue
In have that read command is pending, and the program command from Low Priority Queuing is carrying out (601)；Then pause is low preferential to coming from
The processing (632) of the program command of grade queue.It, can be to being carrying out the program command to suspend processing to program command
NVM sends programming pause command.And it is obtained from high-priority queue and handles read command (633).It has been handled in read command
Cheng Hou restores the processing (634) of the program command to being suspended.It, can be to this to restore the processing to the program command being suspended
The targeted NVM of program command sends programming and restores order.
In another example, postpone and reduce program command pair to the processing of read command to reduce program command
The holding time of XOR cache resources, the queue of Media Interface Connector controller response command (such as the queue 342/344 of Fig. 4, the team of Fig. 5
Row 542/544) pending order.If there is the read command pending and in Low Priority Queuing in high-priority queue
In have the program command pending (610)；Then preferentially program command is taken out from Low Priority Queuing and handle the program command
(611).To handle program command, the data that program command will be written in the data XOR cachings of NVM are done into exclusive or, are as a result stored
NVM is sent in XOR cachings and by program command.Optionally, after program command being sent to NVM, release XOR cachings
(612).Still optionally, before release XOR cachings, in the data-moving to DRAM during can XOR be cached, so as to following
When needing the data using XOR cachings, the data can be obtained from DRAM and are moved into XOR cachings.Next, pause is to compiling
The processing (632) of journey order.And the read command (633) in processing high-priority queue.After the completion of read command processing, restore
Processing (634) to the program command being suspended.
In another example, the processing of read command is postponed in order to reduce erasing order, Media Interface Connector controller response life
Enable queue (such as queue 342/344 of Fig. 4, the queue 542/544 of Fig. 5) pending order.If in high-priority queue
In have read command pending and have the erasing order pending (620) in Low Priority Queuing；Then preferentially from low priority team
Row take out erasing order.And for example erasing order (621) is handled by sending erasing order to NVM.Next, pass through to
NVM sends erasing pause command to suspend the processing (622) to the erasing order.And the reading life in processing high-priority queue
It enables (633).After the completion of read command processing, restore the processing (634) of the erasing order to being suspended.
Embodiment five
Fig. 7 illustrates the Media Interface Connector controller of further embodiment of this invention.In the embodiment of Fig. 7, Media Interface Connector control
Device 740 includes multiple queues (for example, queue 542/544).Each queue has different priority, such as queue 542 is high
Priority query, and queue 544 is Low Priority Queuing.Media Interface Connector controller 740 is coupled to verification data calculator 720.
As an example, verification data calculator 720 does input data exclusive or to obtain verification data, in verification data calculator 720
In further include XOR caching (722/724/726).
Optionally, Media Interface Connector controller 540 is additionally coupled to DRAM (referring to Fig. 1, DRAM 110).
Wherein, Media Interface Connector controller 740 is exclusively used in accessing logic unit (LUN 505), thus to access LUN 505,
Queue 542/544 is added into corresponding order.
It is to be appreciated that may include multigroup execution state in Media Interface Connector controller, every group of execution state is exclusively used in accessing
One of logic unit.The execution state of Media Interface Connector controller is switched over so that at each moment, Media Interface Connector controller
It is exclusively used in accessing (one) logic unit corresponding with current execution state.
Media Interface Connector controller 740 shown in Fig. 7 is also coupled to CPU and DRAM by bus 730, so as in the association of CPU
It helps down and more efficiently handles I/O command.Verification data calculator 720 exchanges data and by total by bus 730 with DRAM
Line 730 to CPU indicate interrupt, interrupt include instruction for page band verification data calculate completion interruption (R_CPL) and
It is used to indicate the interruption (P_CPL) that the write operation processing to page band is completed.It can also it is to be appreciated that interrupting (P_CPL)
It is generated by Media Interface Connector controller 740.Write operation to page band, which is handled, to be completed, and refers to the user data and check number of page band
According to NVM chips 105 being written by multiple program commands, and NVM chips 105 indicate that multiple program commands are in completing.
In some cases, one or more program commands perform failure, interrupt (P CPL) by response, CPU will also know to perform mistake
The program command lost.
As an example, data are written to page band (S14), page band (S14) includes 3 Physical Page, for storing the use of page 2
User data and the verification data of page 1.Wherein warp-wise page band (S14) is written with the user data of page 1.Media Interface Connector controller
740 receive program command (P14), and program command (P14) to page band (S14) for being written the user data of page 2.In check number
It caches in (722) and is had recorded for the verification data of page band (S14) according to the XOR of calculator 720.Media Interface Connector controller 740
XOR is distributed for program command (P14) and caches (722), and the corresponding data of the program command stored in DRAM (P14) are delayed with XOR
It deposits the data that (722) are stored and does exclusive or, exclusive or result is stored in XOR cachings (722) and sends out program command (P14)
Give LUN 505.
Next, the exclusive or due to all customer data for having been completed a page band (S14) calculates, XOR cachings (722)
Middle storage is the verification data (X1) for being used for page band (S14).XOR is cached the school in (722) by verification data calculator 740
Data are tested by bus transfer to DRAM, generation interrupts (R_CPL) and is sent to CPU (for example, by bus 730).CPU is based on
It interrupts (R_CPL) and knows that the verification data for page band (S14) has calculated completion, and knows for page band (S14)
Storage location of the verification data in DRAM.Next, CPU or Media Interface Connector controller 740 can cache XOR (722)
The page band of data will be written by initializing and distributing to other.
In next any time, CPU fills program command (P15) to command queue 542/544, will be in DRAM
Verification data (X1) write-in page band (S14), and need not be counted to the instruction of Media Interface Connector controller 740 for program command (P15)
Calculate verification data.And
Next, indicate that program command (P15) performs completion in response to LUN 505, Media Interface Connector controller 740 is to CPU
It generates and interrupts (P_CPL), the implementing result of program command (P15) is indicated in interruption.If program command (P15) runs succeeded,
CPU abandons the verification data (X1) in DRAM；If program command (P15) performs failure, CPU generates another program command (P15),
The verification data (X1) in DRAM is written NVM chips again.Further, if program command (P15) performs failure, due to
Page band (S14) is not written completely, needs to read the data that page band (S14) has been written into, and another page of band is written.
With continued reference to Fig. 7, in another embodiment, in response to receiving and performing program command (P14), delay in XOR
Deposit the verification data (X1) generated in (722) for page band (S14).Media Interface Connector controller 740 passes through program command
(P16) XOR is cached data (X1) the write-in LUN505 in (722) and XOR is cached the data in (722) and pass through bus
DRAM is written.The register and DRAM of LUN 505 are written into response to verification data (X1), is generated to CPU and interrupts (R_
CPL).In response to interrupting (R_CPL), CPU knows that verification data (X1) has been sent to LUN 505, and there are schools in DRAM
Test the copy of data (X1).It initializes and distributes next, XOR can be cached (722) by CPU or Media Interface Connector controller 740
The page band of data to be written to other.And when LUN 505 indicates that program command (P16) is held to Media Interface Connector controller 740
Row is completed, and the generation of Media Interface Connector controller 740 interrupts (P_CPL) to be completed to CPU instructions to the operation of page band (S14).
In the embodiment of Fig. 7, when page band is written, XOR cachings can be discharged earlier, and the XOR of release is cached
Other program commands are distributed to, so as to can concurrently perform more program commands in solid storage device, are reduced limited
XOR cache resources decrease program command and wait for the general of XOR cache resources to concurrently performing the limitation of the quantity of program command
Rate reduces the processing delay of program command, improves the performance of solid storage device.
Embodiment six
Fig. 8 illustrates the flow chart of the I/O command processing method according to further embodiment of this invention.Media Interface Connector controller
(referring also to Fig. 7, Media Interface Connector controller 740)/verification data calculator (referring to Fig. 7, verification data calculator 720) and CPU
I/O command is sent to logic unit (referring to Fig. 7, such as LUN 505) by (referring to Fig. 7) cooperating.
CPU generations order programming for user data to be written to the program command (P17) of logic unit (LUN 505)
Enable the command queue (referring to Fig. 7, queue 545/544) (810) of write-in Media Interface Connector controller.
Next, in response to receiving program command (P17), Media Interface Connector controller will be corresponding to program command (P17)
Data are sent to logic unit (LUN 505) (801).Verification data calculator is same by the data corresponding to program command (P17)
The data that XOR cachings are cached (referring also to Fig. 7, XOR cachings (722/724/726)) do exclusive or, are as a result stored in XOR cachings
(722/724/726) in (802).It calculates and completes in response to the verification data of page band (S15), verification data calculator is by XOR
In the verification data storage to DRAM (referring to Fig. 7, referring also to Fig. 1, DRAM 110) for caching (722/724/726), generation is interrupted
R_CPL, and R_CPL will be interrupted and be sent to CPU and indicate address (803) of the verification data in DRAM to CPU.
R_CPL (820) is interrupted in response to receiving, CPU generates to cache DRAM or XOR in (722/724/726)
The program command (P18) of verification data write-in logic unit (LUN 505), and it is sent to Media Interface Connector controller (830).It is optional
Ground interrupts R_CPL (820) in response to receiving, and CPU also discharges the XOR cachings (722/724/726) interrupted indicated by R_CPL,
Or it distributes it and is used for generating verification data for other page of band.Still optionally, CPU also records the school interrupted indicated by R_CPL
Test address of the data in DRAM；Or R_CPL (820) is interrupted in response to receiving, CPU ignores interruption R_CPL.
In response to receiving program command (P18), the verification data from DRAM is sent to logic by Media Interface Connector controller
Unit (LUN 505) (804), the verification data are the verification datas for page band (S15).Further, in response to page item
The verification data of band (S15) is written into NVM, and Media Interface Connector controller or the generation of verification data calculator interrupt P_CPL, and will
P_CPL is interrupted to be sent to CPU and indicate its implementing result (805) for programming verification data to CPU.
Next, interrupting P_CPL in response to receiving, CPU confirms that verification data program command (P18) runs succeeded or fails
(840).If success, show that the data of page band (S15) are written and complete, can drop the verification data (850) in DRAM；If
Failure, CPU generate the program command (P19) for the verification data in DRAM to be written to logic unit (LUN 505) again, and
It is sent to Media Interface Connector controller.Optionally, if program command (P18) performs failure, CPU reads number from page band (S15)
According to generation is used for the program command (P20) for the data write-in page band (S16) that will be read from page band (S15) and by DRAM
In verification data write-in page band (S16).
Methods and apparatus of the present invention can with hardware, software, firmware and it is above-mentioned in arbitrary combination realize.Hardware
It can include digital circuit, analog circuit, digital signal processor (DSP), special succession circuit (ASIC) etc..Software can be with
Including computer-readable program, these computer-readable programs realize method of the present invention when being computer-executed.
The software of the present invention can also be stored in computer readable storage medium, such as hard disk, CD etc., the calculating
Machine readable storage medium storing program for executing has program stored therein, when described program is performed by an equipment so that the equipment carries out described above
Method.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in change or replacement, should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of I/O command processing method, wherein being obtained from high priority command queue or low priority command queue pending
I/O command and relative to the I/O command in priority processing high priority command queue of low priority command queue, feature
It is, including：
If there is the first order of the first kind for accessing the first logic unit in low priority command queue, take out and handle the
One order；
During the first order of processing, if there is the Second Type for accessing the first logic unit in high priority command queue
Second order, suspend to first order processing, take out and handle the second order；
It is completed in response to the second command process, restores the processing to the first order.
2. a kind of I/O command processing method, wherein being obtained from high priority command queue or low priority command queue pending
I/O command and relative to the I/O command in priority processing high priority command queue of low priority command queue, feature
It is, including：
If there is the first order and the high priority for the first kind for accessing the first logic unit in low priority command queue
There is the second order of the Second Type for accessing the first logic unit in command queue, take out and handle the first order, by first
Corresponding data is ordered to be sent to the processing of the first logic unit and pause to the first order, takes out and handles the second order；
It is completed in response to the second command process, restores the processing to the first order.
3. I/O command processing method according to claim 1 or 2, which is characterized in that wherein the first order of the first kind
It is program command, the second order of Second Type is read command.
4. I/O command processing method as claimed in claim 3, which is characterized in that if to be handled in high priority command queue
Read command, pending program command or erasing order in low priority command queue will be in low priority command queues
Program command or erasing order take out and handle；And
If read command accesses the first logic unit with program command or erasing order, suspend to program command or erasing order
Processing, take out and read command and handle from high priority command queue；And
Processing in response to read command is completed, and restores the processing to program command or erasing order.
5. a kind of Media Interface Connector controller, the Media Interface Connector controller is coupled to one or more NVM chips, each NVM cores
Piece includes one or more logic units；The Media Interface Connector controller is additionally coupled to high priority command queue and low priority
Command queue, which is characterized in that if there is the first of the first kind for accessing the first logic unit in low priority command queue
During order, the Media Interface Connector controller takes out from low priority command queue and handles the first order；When the first life of processing
During order, if there is the second order for accessing the first logic unit in high priority command queue, the Media Interface Connector
Processing of the controller pause to the first order, takes out and handles the second order；And completed in response to the second command process, it is described
Media Interface Connector controller restores the processing to the first order.
6. a kind of Media Interface Connector controller, the Media Interface Connector controller is coupled to one or more NVM chips, each NVM cores
Piece includes one or more logic units；The Media Interface Connector controller is additionally coupled to high priority command queue and low priority
Command queue, which is characterized in that if there is the first of the first kind for accessing the first logic unit in low priority command queue
There is the second order of the Second Type for accessing the first logic unit, the medium in order and high priority command queue
Interface controller takes out from low priority command queue and handles the first order, and the corresponding data of the first order are sent to
The processing of first logic unit and pause to the first order, takes out and handles the second order；And
It is completed in response to the second command process, the Media Interface Connector controller restores the processing to the first order.
7. Media Interface Connector controller as claimed in claim 6, which is characterized in that if to be handled in high priority command queue
Read command, pending program command or erasing order in low priority command queue, the Media Interface Connector controller uses
In taking out and handle the program command in low priority command queue or erasing order；And
If read command accesses the first logic unit with program command or erasing order, suspend to program command or erasing order
Processing, take out and read command and handle from high priority command queue；And
Processing in response to read command is completed, and restores the processing to program command or erasing order.
8. a kind of Media Interface Connector controller, the Media Interface Connector controller is coupled to a logic unit, the Media Interface Connector control
Device processed is additionally coupled to high priority command queue and low priority command queue, which is characterized in that if low priority command queue
It is middle to exist in the first order of the first kind for accessing the logic unit and high priority command queue in the presence of described in access
Second order of the Second Type of logic unit, the Media Interface Connector controller take out and handle from low priority command queue
First order, and the corresponding data of the first order are sent to the processing of the logic unit and pause to the first order, it takes
Go out and handle the second order；And
It is completed in response to the second command process, the Media Interface Connector controller restores the processing to the first order.
9. a kind of solid storage device, including host interface, control unit, DRAM and one or more NVM chips, control unit
Part is for the data transmission between control interface, NVM chips and firmware memory, which is characterized in that the control unit includes
One or more Media Interface Connector controllers as described in one of claim 5-8.
10. a kind of solid storage device, including one or more processors and memory, one or more of processors pass through
Program in run memory performs the I/O command processing method as described in one of claim 1-4.
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