CN108153582B

CN108153582B - IO command processing method and medium interface controller

Info

Publication number: CN108153582B
Application number: CN201611106674.5A
Authority: CN
Inventors: 王树珂; 徐凯; 孙明浩
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2016-12-05
Filing date: 2016-12-05
Publication date: 2024-01-26
Anticipated expiration: 2036-12-05
Also published as: CN108153582A

Abstract

The application provides an IO command processing method and a medium interface controller. The disclosed method comprises the following steps: if a first command of a first type accessing the first logic unit exists in the low-priority command queue, the first command is fetched and processed; if a second command of a second type accessing the first logic unit exists in the high-priority command queue in the process of processing the first command, suspending the processing of the first command, and taking out and processing the second command; in response to completion of the second command processing, processing of the first command is resumed. The media interface controller is coupled to one or more NVM chips, each NVM chip including one or more logic cells, and is further coupled to a high priority command queue and a low priority command queue for performing the IO command processing method. The method and the device are applied to the reading operation of the solid-state storage device.

Description

IO command processing method and medium interface controller

Technical Field

The present application relates to the field of storage technologies, and in particular, to IO command processing in a media interface controller.

Background

The NVM (nonvolatile Memory) is used for realizing a Memory function, and has a nonvolatile characteristic. FIG. 1 is a block diagram of a solid state storage device 102 coupled to a host for providing storage capacity for the host. The host and solid state storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communications network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.

NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive RandomAccess Memory, resistive memory), and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and firmware memory 110, and also for storage management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof; the control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands; control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110; FTL tables and/or cached data of IO commands may be stored in the DRAM.

The memory Target (Target) is one or more logical units (Logic units) of a shared Chip Enable (CE) signal within the flash granule 105 package, each logical Unit having a logical Unit number (LUN, logic Unit Number). One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other. At the position of

In "Open NAND Flash Interface Specification (envision 3.2)" obtained from http:// www.onfi.org/-/media/ONFI/specs/onfi_3_2% 20gold. Pdf, meanings about target, logical unit, LUN, plane (Plane) are provided, as well as commands to operate NVM chips are also provided.

Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes. A physical page may include a plurality of data frames (data frames) therein, the data frames having a specified size, such as 4096 or 4416 bytes.

In solid state storage devices, FTL (Flash Translation Layer ) is utilized to maintain mapping information from logical addresses to physical addresses. The logical addresses constitute the storage space of the solid state storage device as perceived by upper level software such as the operating system. The physical address is an address for accessing a physical storage unit of the solid state storage device. Address mapping can also be implemented in the prior art using an intermediate address modality. For example, logical addresses are mapped to intermediate addresses, which in turn are further mapped to physical addresses.

The table structure in which the mapping information from logical addresses to physical addresses is stored is called FTL table. FTL tables are important metadata in solid state storage devices. Typically, the data items of the FTL table record address mapping relationships in units of data pages in the solid-state storage device.

FTL tables include a plurality of FTL table entries (or entries). In one example, a logical page address to physical page correspondence is recorded in each FTL table entry. In another example, correspondence between consecutive logical page addresses and consecutive physical pages is recorded in each FTL table entry. In yet another example, a correspondence of logical block addresses to physical block addresses is recorded in each FTL table entry. In still another embodiment, the FTL table records a mapping relationship between a logical block address and a physical block address, and/or a mapping relationship between a logical page address and a physical page address.

When a read command from a host is processed, the solid-state storage device obtains a corresponding physical address from the FTL table by utilizing a logic address carried in the read command, sends a read request to the NVM chip according to the physical address, and receives data output by the NVM chip in response to the read request. When a write command from a host is processed, the solid state storage device allocates a physical address for the write command, records the correspondence between the logical address of the write command and the allocated physical address in the FTL table, and issues a write request to the NVM chip according to the allocated physical address.

A plurality of NVM chips are included in the solid-state storage device. Each NVM chip includes one or more DIEs (DIE) or Logical Units (LUNs). The die or logic units may respond to read and write operations in parallel. Multiple read, write, or erase operations are performed sequentially on the same die or logic unit.

Fig. 2 shows a schematic diagram of a large block. A chunk includes a physical block from each of a plurality of logical units. Preferably, each logical unit provides a physical block for a large block. By way of example, a large block is constructed on every 16 Logical Units (LUNs). Each chunk includes 16 physical blocks, from each of 16 Logical Units (LUNs). In the example of FIG. 2, chunk 0 includes physical chunk 0 from each of the 16 Logical Units (LUNs), while chunk 1 includes physical chunk 1 from each Logical Unit (LUNs). There are a variety of other ways to construct the chunk.

As an alternative, page stripes are constructed in large blocks, with physical pages of the same physical address in each Logical Unit (LUN) constituting a "page stripe". In fig. 2, physical pages 0-0, physical pages 0-1, and physical pages 0-x constitute a page stripe 0, wherein physical pages 0-0, physical pages 0-1, physical pages 0-14 are used to store user data, and physical pages 0-15 are used to store parity data calculated from all user data within the stripe. Similarly, in FIG. 2, physical pages 2-0, physical pages 2-1. Alternatively, the physical page used to store the parity data may be located anywhere in the page stripe.

One or more physical blocks in a large block may be bad blocks. No data should be written to the bad blocks. The amount of user data that can be accommodated in a page stripe is thus dependent on the number of bad blocks of the large block in which the page stripe is located. The physical page includes one or more data units. The number of valid data units of the page stripe refers to the number of data units in the page stripe that can accommodate user data. By way of example, the physical pages provided by the bad blocks in the page stripe are removed, and the physical pages used to store the parity data are removed, with the number of data units of the remaining physical pages being the number of valid data units of the page stripe.

To write data to a page stripe, a control component (104) of the solid state storage device (see FIG. 1) provides a verification data calculation unit. Taking the example of calculating the parity data using an exclusive or operation, for a page stripe including n+1 physical pages, an exclusive or (e.g., (P0-1) XOR (P0-2) xor..xor (P0-15)) is calculated for the user data of the N physical pages, and the calculation result is written to the physical page (e.g., P0-X) storing the parity data for the page stripe. Optionally, a plurality of check data calculation units (e.g., M) are provided in the control section (104) to write data to M page stripes simultaneously.

Disclosure of Invention

In the prior art, the read-write operation can be responded in parallel between the dies or the logic units, and in one memory unit (logic unit or die, etc.), the read command, the program command and the erase command must be executed in series, and although the processing delay of the read command of the flash memory is significantly smaller than that of the program command, the read command may need to wait for the program command or the erase command accessing the same memory unit to be completed before being processed. This causes the processing delay of the read command to be affected by the program command/erase command, resulting in a significant increase in the processing delay of the read command. This can also significantly impact quality of service.

Although prioritizing the read command relative to the program command helps to reduce processing delay of the read command. However, the programming commands also need to be processed preferentially to reduce the occupation of resources for computing the parity data for the page stripe and increase the throughput (concurrent processing capacity) of the solid state storage device. The resources used for the check data computation to compute the page stripes include a check data computation unit and/or an XOR buffer. The XOR cache computes the check data when writing data to the page stripe. For the page stripe of the n+1 structure, after obtaining the data of N pages, the check data can be calculated. Thus, the check data calculation unit is occupied at the start of writing the 1 st page data to the page stripe, and cannot calculate the check data for the n+1st page of the page stripe until the N-th page data is written to the page stripe. The number of check data calculation units thus limits the number of concurrently processed programming commands in the solid state storage device. Further, the delay of the programming command is increased, so that the processing delay for completing the writing of the page stripe is increased, the occupation of a verification data calculation unit is further increased, and the concurrent processing capacity of the programming command is reduced.

The purpose of the application comprises providing an IO command processing method and an NVM interface controller, which are used for reducing the processing delay of IO commands, reducing the occupation of processor resources and improving the concurrent processing capacity of solid-state storage equipment.

A first aspect of the present invention provides an IO command processing method in which an IO command to be processed is acquired from a high-priority command queue or a low-priority command queue, and the IO command in the high-priority command queue is processed preferentially with respect to the low-priority command queue, the IO command processing method including:

if a first command of a first type accessing the first logic unit exists in the low-priority command queue, the first command is fetched and processed;

if a second command of a second type accessing the first logic unit exists in the high-priority command queue in the process of processing the first command, suspending the processing of the first command, and taking out and processing the second command;

in response to completion of the second command processing, processing of the first command is resumed.

A second aspect of the present invention provides an IO command processing method in which an IO command to be processed is acquired from a high-priority command queue or a low-priority command queue, and the IO command in the high-priority command queue is processed preferentially with respect to the low-priority command queue, the IO command processing method including:

If a first command of a first type accessing the first logic unit exists in the low-priority command queue and a second command of a second type accessing the first logic unit exists in the high-priority command queue, the first command is fetched and processed, data corresponding to the first command is sent to the first logic unit, processing of the first command is suspended, and the second command is fetched and processed;

According to a first aspect or a second aspect of the present invention, there is provided a first IO command processing method according to the first aspect or the second aspect of the present invention, wherein the first command of the first type is a program command and the second command of the second type is a read command.

According to a first aspect of the present invention, there is provided a second IO command processing method according to the first aspect of the present invention, further comprising: when a command accessing other logic units except the first logic unit exists in the high-priority command queue in the process of processing the first command, the processing of the first command is not suspended, and the command accessing the other logic units is processed.

According to the first or second aspect of the present invention, there is provided a third IO command processing method according to the first or second aspect of the present invention, further comprising: and placing the IO command into a high-priority command queue or a low-priority command queue according to the type of the IO command.

According to a first or second aspect of the present invention there is provided a fourth IO command processing method according to the first or second aspect of the present invention wherein a read command is placed in a high priority command queue and a program command, an erase command or a read command that does not require processing delay is placed in a low priority command queue.

According to a first aspect or a second aspect of the present invention, there is provided a fifth IO command processing method according to the first aspect or the second aspect of the present invention, when a read command to be processed is in the high priority queue, and there is a program command or an erase command being processed on the first logic unit, if the read command accesses the first logic unit, suspending the program command or the erase command being processed, and taking out the read command from the high priority command queue and processing; and resuming processing of the program command or the erase command in response to the read command processing being completed.

According to a first aspect or a second aspect of the present invention, there is provided a sixth IO command processing method according to the first aspect or the second aspect of the present invention, if a read command to be processed is in a high priority command queue, a program command or an erase command to be processed is in a low priority command queue, and the program command or the erase command in the low priority command queue is fetched and processed; if the read command and the programming command or the erasing command both access the first logic unit, suspending processing of the programming command or the erasing command, and taking out the read command from the high-priority command queue and processing; and resuming processing of the program command or the erase command in response to the processing of the read command being completed.

According to a first aspect or a second aspect of the present invention, there is provided the seventh IO command processing method according to the first aspect or the second aspect of the present invention, wherein n+p physical pages within n+p logical units constitute a page stripe in which N pages of user data and P pages of check data calculated from the N pages of user data are stored, and N, P is a positive integer greater than or equal to 1.

According to a first aspect or a second aspect of the present invention, there is provided an eighth IO command processing method according to the first aspect or the second aspect of the present invention, the cache storing check data for the first page stripe, the IO command processing method further comprising: and in response to fetching and processing the programming command from the low-priority command queue, performing exclusive-or on the data corresponding to the programming command and the data stored in the cache, and storing the exclusive-or result in the cache.

According to a first aspect or a second aspect of the present invention, there is provided a ninth IO command processing method according to the first aspect or the second aspect of the present invention, if an exclusive or result of N pages of user data in the first page stripe is stored in the cache; writing the cached verification data into the first page stripe; and releasing the cache.

According to a first aspect or a second aspect of the present invention, there is provided a tenth IO command processing method according to the first aspect or the second aspect of the present invention, further comprising: storing the cached verification data to a DRAM; and releasing the cache.

According to a first aspect or a second aspect of the present invention, there is provided an eleventh IO command processing method according to the first aspect or the second aspect of the present invention, further comprising: in response to a subsequent write of data to the first page stripe, reallocating the cache, transferring check data associated with the first page stripe from the DRAM to the cache, xoring user data corresponding to the programming command with the data in the cache, and storing the xored result in the cache; and sending the programming command to the logic unit.

According to a first aspect or a second aspect of the present invention, there is provided a twelfth IO command processing method according to the first aspect or the second aspect of the present invention, further comprising: if the exclusive OR result of the N pages of user data in the first page stripe is stored in the cache, sending the cached check data to the logic units corresponding to the P physical pages of the page stripe; storing the data in the cache to the DRAM: and releasing the cache.

According to a first aspect or a second aspect of the present invention, there is provided a thirteenth IO command processing method according to the first aspect or the second aspect of the present invention, if writing check data into one of P physical pages is erroneous, storing the check data associated with the first page stripe from the DRAM into a cache.

According to a first aspect or a second aspect of the present invention, there is provided a fourteenth IO command processing method according to the first aspect or the second aspect of the present invention, further comprising: distributing page strips; a cache is allocated.

According to a first aspect or a second aspect of the present invention, there is provided a fifteenth IO command processing method according to the first aspect or the second aspect of the present invention, writing check data of a first page stripe to P physical pages of the page stripe in response to all user data having been written to the page stripe; the cache is released.

Because the command scheduling method of the first aspect and the second aspect of the present invention puts different types of IO commands accessing the same logic unit into the high priority command queue and the low priority command queue respectively, and establishes a corresponding command processing mechanism according to the priority of the command queue and different states in command execution, on the one hand, when processing a first command, if a second command of a second type accessing the first logic unit exists in the high priority command queue, processing the first command is suspended, and the second command is taken out and processed; if the low-priority command queue has a first command of a first type accessing the first logic unit and the high-priority command queue has a second command of a second type accessing the first logic unit, the first command is fetched and processed, data corresponding to the first command is sent to the first logic unit, processing of the first command is suspended, and the second command is fetched and processed; the problem of processing delay caused by the influence of the programming command/erasing command on the read command is solved, and the programming command is preferentially processed, so that the occupation of resources is reduced, and the throughput (concurrent processing capacity) of the solid-state storage device is increased.

A third aspect of the invention provides a media interface controller coupled to one or more NVM chips, each NVM chip including one or more logic cells; the medium interface controller is further coupled to a high priority command queue and a low priority command queue, and if a first command of a first type accessing the first logic unit exists in the low priority command queue, the medium interface controller fetches and processes the first command from the low priority command queue; when a second command accessing the first logic unit exists in the high-priority command queue in the process of processing the first command, the medium interface controller pauses the processing of the first command, and takes out and processes the second command; and in response to completion of the second command processing, the media interface controller resumes processing of the first command.

A fourth aspect of the invention provides a media interface controller coupled to one or more NVM chips, each NVM chip including one or more logic cells; the medium interface controller is further coupled to the high priority command queue and the low priority command queue, and if a first command of a first type accessing the first logic unit exists in the low priority command queue and a second command of a second type accessing the first logic unit exists in the high priority command queue, the medium interface controller fetches and processes the first command from the low priority command queue, sends data corresponding to the first command to the first logic unit, pauses processing of the first command, and fetches and processes the second command; and in response to completion of the second command processing, the media interface controller resumes processing of the first command.

According to a third or fourth aspect of the present invention there is provided a first media interface controller according to the third or fourth aspect of the present invention, wherein the IO commands in the high priority command queue and the low priority command queue are each of a different type.

According to a third or fourth aspect of the present invention there is provided a second media interface controller according to the third or fourth aspect of the present invention, the media interface controller processing commands accessing other logical units without suspending processing of the first command if there are commands accessing other logical units than the first logical unit in the high priority command queue.

According to a third or fourth aspect of the present invention there is provided a third media interface controller according to the third or fourth aspect of the present invention, the IO commands of the high priority command queue being read commands; the IO commands in the low priority command queue are program commands, erase commands, or read commands that do not require processing delays.

According to a third or fourth aspect of the present invention there is provided a fourth media interface controller according to the third or fourth aspect of the present invention, when a read command is pending in a high priority queue, a program command or an erase command being processed is present on a first logical unit, if the read command accesses the first logical unit, the media interface controller being operable in particular to suspend the program command or the erase command being processed, and to fetch the read command from the high priority command queue and process it; and resuming processing of the program command or the erase command in response to the read command processing being completed.

According to a third or fourth aspect of the present invention, there is provided a fifth media interface controller according to the third or fourth aspect of the present invention, if a read command to be processed is in a high priority command queue, a program command or an erase command to be processed is in a low priority command queue, the media interface controller being configured to fetch and process the program command or the erase command in the low priority command queue; if the read command and the programming command or the erasing command both access the first logic unit, suspending processing of the programming command or the erasing command, and taking out the read command from the high-priority command queue and processing; and resuming processing of the program command or the erase command in response to the processing of the read command being completed.

According to a third or fourth aspect of the present invention, there is provided a sixth media interface controller according to the third or fourth aspect of the present invention, further comprising a parity data calculator, and at least one cache, wherein the cache is for storing parity data for a first page stripe; in response to fetching and processing the programming command from the low priority command queue, the check data calculator xors data corresponding to the programming command with data stored in the cache, and the xored result is stored in the cache.

According to a third or fourth aspect of the present invention, there is provided the seventh media interface controller according to the third or fourth aspect of the present invention, wherein n+p physical pages within n+p logical units constitute a page stripe in which N pages of user data and P pages of check data calculated from the N pages of user data are stored, N, P being a positive integer greater than or equal to 1.

According to a third or fourth aspect of the present invention, there is provided an eighth media interface controller according to the third or fourth aspect of the present invention, the media interface controller writing the buffered check data into the first page stripe if the exclusive or result of the N pages of user data in the first page stripe is stored in the buffer; and releasing the cache.

According to a third or fourth aspect of the present invention there is provided a ninth media interface controller according to the third or fourth aspect of the present invention, the media interface controller further coupled to a DRAM, the media interface controller storing cached verification data to the DRAM; and releasing the cache.

According to a third or fourth aspect of the present invention there is provided a tenth media interface controller according to the third or fourth aspect of the present invention, responsive to subsequent writing of data to the first page stripe, the media interface controller reallocating the cache and transferring check data associated with the first page stripe from the DRAM into the cache; the verification data calculator performs exclusive-or on user data corresponding to the programming command and data in the cache, and stores an exclusive-or result in the cache; and the media interface controller sends the programming command to the logic unit.

According to a third aspect or a fourth aspect of the present invention, there is provided an eleventh media interface controller according to the third aspect or the fourth aspect of the present invention, if an exclusive or result of N pages of user data in the first page stripe is stored in the cache, the media interface controller sends the cached check data to a logic unit corresponding to P physical pages of the page stripe; storing the data in the cache to the DRAM; and releasing the cache.

According to a third or fourth aspect of the present invention there is provided a twelfth media interface controller according to the third or fourth aspect of the present invention, the media interface controller storing check data associated with the first page stripe from the DRAM into the cache if the write of the check data to one of the P physical pages is erroneous.

According to a third or fourth aspect of the present invention there is provided a thirteenth media interface controller according to the third or fourth aspect of the present invention, the media interface controller writing check data for a first page stripe to P physical pages of the page stripe in response to having written all user data to the page stripe; the cache is released.

A fifth aspect of the present invention provides a media interface controller, the media interface controller being coupled to a logic unit, the media interface controller further being coupled to a high priority command queue and a low priority command queue, the media interface controller retrieving and processing a first command from the low priority command queue if the first command of a first type accessing the logic unit is present in the low priority command queue; when a second command accessing the logic unit exists in the high-priority command queue in the process of processing the first command, the medium interface controller pauses the processing of the first command, and takes out and processes the second command; and in response to completion of the second command processing, the media interface controller resumes processing of the first command.

A sixth aspect of the present invention provides a media interface controller, the media interface controller being coupled to a logic unit, the media interface controller being further coupled to a high priority command queue and a low priority command queue, if there is a first command of a first type accessing the logic unit in the low priority command queue and there is a second command of a second type accessing the logic unit in the high priority command queue, the media interface controller retrieving and processing the first command from the low priority command queue and sending data corresponding to the first command to the logic unit, and suspending processing of the first command, retrieving and processing the second command; and in response to completion of the second command processing, the media interface controller resumes processing of the first command.

According to a fifth or sixth aspect of the present invention there is provided a first media interface controller according to the fifth or sixth aspect of the present invention, wherein the IO commands in the high priority command queue and the low priority command queue are each of a different type.

According to a fifth or sixth aspect of the present invention there is provided a second media interface controller according to the fifth or sixth aspect of the present invention, the media interface controller further coupled to a parity data calculator and at least one cache, wherein the cache is for storing parity data for a first page stripe; the check data calculator is used for responding to the program command which is fetched from the low-priority command queue and processed, performing exclusive-or on the data corresponding to the program command and the data stored in the cache, and storing the exclusive-or result in the cache.

According to a fifth or sixth aspect of the present invention, there is provided a third media interface controller according to the fifth or sixth aspect of the present invention, further coupled to the DRAM, for storing the buffered check data in the DRAM through the media interface controller and releasing the buffer after the check data calculator xors the data corresponding to the program command with the data stored in the buffer and stores the xored result in the buffer.

A seventh aspect of the invention provides a solid state storage device comprising a host interface, a control unit for controlling data transfer between the interface, the NVM chip and a firmware memory, a DRAM and one or more NVM chips, the control unit further comprising one or more media interface controllers as described in the third and fourth aspects of the invention, and possible implementations thereof.

An eighth aspect of the present invention provides a solid state storage device comprising a host interface, a control unit, a DRAM, and one or more NVM chips, each NVM chip comprising one or more logic units, the control unit for controlling data transfer between the interface, the NVM chips and a firmware memory, the control unit further comprising one or more media interface controllers as described in the fifth and sixth aspects of the present invention, and possible implementations thereof, and a verification data calculator coupled with one or more of the media interface controllers for xoring input data to obtain verification data.

A ninth aspect of the present invention provides a computer readable storage medium comprising a program which, when loaded into a solid state storage device and executed on a controller of the solid state storage device, causes the controller to perform the IO command processing method as described in the first and second aspects of the present invention, and possible implementations thereof.

A tenth aspect of the present invention provides a solid state storage device comprising one or more processors and a storage, the one or more processors executing the IO command processing method as described in the first and second aspects of the present invention and their possible implementations by running a program in the storage.

An eleventh aspect of the present invention provides an IO command processing method, the IO command processing method including: in response to completion of the calculation of the check data of the page stripe, storing the check data in the cache to an external memory, generating an interrupt signal R_CPL to indicate the cache allocated for the page stripe to be releasable and to indicate a storage address of the check data; and generating an interrupt signal p_cpl to indicate that the parity data in the external memory can be released in response to completion of the write operation to write the parity data to the page stripe.

A twelfth aspect of the present invention provides an IO command processing method, including: transmitting a programming command for writing data into the logic unit to the media interface controller; in response to receiving the interrupt signal r_cpl, generating a program command to write the check data in the external memory indicated by the interrupt signal r_cpl to the page stripe and indicating that the check data need not be calculated for the generated program command; and discarding the check data in the external memory if the interrupt signal p_cpl indicates that the write operation is successful in response to receiving the interrupt signal p_cpl.

According to a twelfth aspect of the present invention, there is provided the first IO command processing method according to the twelfth aspect of the present invention, generating the second programming command if the interrupt signal p_cpl indicates that the write operation fails, writing the check data in the external memory to the page stripe, and indicating that it is not necessary to calculate the check data for the generated second programming command.

According to a twelfth aspect of the present invention, there is provided the second IO command processing method according to the twelfth aspect of the present invention, reading out the data that has been written in the page stripe and generating a program command to write the data read out from the page stripe to another page stripe if the interrupt signal p_cpl indicates that the write operation fails, and generating a program command to write the check data in the external memory to the other page stripe and indicating that it is not necessary to calculate the check data for the generated program command.

According to a twelfth aspect of the present invention, there is provided the third IO command processing method according to the twelfth aspect of the present invention, in response to receiving the interrupt signal r_cpl, releasing the cache indicated by the interrupt signal r_cpl.

According to a twelfth aspect of the present invention, there is provided the fourth IO command processing method according to the twelfth aspect of the present invention, in response to an application to the second buffer, sending a second programming command to write data to the logic unit to the media interface controller, the programming command indicating that check data is calculated for the second programming command using the second buffer.

According to a twelfth aspect of the present invention, there is provided the fifth IO command processing method according to the twelfth aspect of the present invention, wherein the interrupt signal r_cpl is ignored in response to receipt of the interrupt signal r_cpl.

A thirteenth aspect of the present invention provides an IO command processing method in which check data for a page stripe is stored with a cache, the IO command processing method comprising: responding to a programming command of writing user data into the page stripe, performing exclusive OR on the user data corresponding to the programming command and the data in the cache, and storing the exclusive OR result in the cache; and transmitting the programming command to the corresponding logic unit.

According to a thirteenth aspect of the present invention, there is provided the first IO command processing method according to the thirteenth aspect of the present invention, transmitting the check data to the external memory in response to completion of all check data calculation of the page stripe, generating the interrupt signal r_cpl, and transmitting the interrupt signal r_cpl to the CPU.

According to a thirteenth aspect of the present invention, there is provided a second IO command processing method according to the thirteenth aspect of the present invention, further comprising: in response to the interrupt signal r_cpl, a program command is generated, the parity data in the external memory is written to the page stripe, and it is indicated that the parity data need not be calculated for the generated program command.

According to a thirteenth aspect of the present invention, there is provided the third IO command processing method according to the thirteenth aspect of the present invention, in response to the interrupt signal p_cpl, discarding the check data in the external memory if the interrupt signal p_cpl indicates that the write operation is successful.

According to a thirteenth aspect of the present invention, there is provided the fourth IO command processing method according to the thirteenth aspect of the present invention, generating a second program command if the interrupt signal p_cpl indicates that the write operation fails, writing check data in the external memory to the page stripe, and indicating that it is not necessary to calculate the check data for the generated second program command, in response to the interrupt signal p_cpl.

According to a thirteenth aspect of the present invention, there is provided the fifth IO command processing method according to the thirteenth aspect of the present invention, reading out data that has been written in a page stripe and generating a program command to write data read out from the page stripe to another page stripe, and generating a program command to write check data in an external memory to the other page stripe and indicating that it is not necessary to calculate check data for the generated program command, if the interrupt signal p_cpl indicates that the write operation fails.

According to a thirteenth aspect of the present invention, there is provided the sixth IO command processing method according to the thirteenth aspect of the present invention, in response to receiving the interrupt signal r_cpl, the cache indicated by the interrupt signal r_cpl may be released or allocated to generate check data for other page stripes, and the address indicated by r_cpl is recorded.

Since the IO command processing method provided in the eleventh to thirteenth aspects of the present invention controls the execution progress of the command by responding to the interrupt signal, wherein the check data is transferred to the external memory in response to completion of all check data calculation of the page stripe, and the interrupt signal r_cpl is generated; generating a programming command to write check data in the external memory indicated by the interrupt signal r_cpl into the page stripe in response to receiving the interrupt signal r_cpl; in response to completion of a write operation to write the parity data to the page stripe, an interrupt signal P_CPL is generated, and in response to receipt of the interrupt signal P_CPL, the parity data in the external memory is discarded if the interrupt signal P_CPL indicates that the write operation was successful. Therefore, when the page stripe is written, the cache can be released earlier and distributed to other programming commands, and more programming commands can be executed concurrently in the solid-state storage device, so that the limit of limited cache resources on the number of concurrent execution programming commands is reduced, the probability of waiting for the resources by the programming commands is also reduced, the processing delay of the programming commands is reduced, and the performance of the solid-state storage device is improved.

A fourteenth aspect of the present invention provides a media interface controller, the media interface controller comprising a high priority command queue and a low priority command queue, the media interface controller being coupled to one or more logic units, the media interface controller further being coupled to a check data calculator and a cache for xoring user data corresponding to a programming command to obtain check data, and storing the xored result in the cache; the media interface controller is also coupled to the CPU and the external memory; the check data calculator is also coupled to the CPU and the external memory for exchanging data with the external memory and for indicating an interrupt signal to the CPU.

According to a fourteenth aspect of the present invention, there is provided the first media interface controller according to the fourteenth aspect of the present invention, wherein in response to completion of the check data calculation for a page stripe, the media interface controller or the check data calculator stores the check data in the cache to the external memory, generates an interrupt signal r_cpl to indicate the cache allocated for the page stripe can be released, and indicates a storage address of the check data; and in response to completion of a write operation to write the parity data to the page stripe, the media interface controller or the parity data calculator generates an interrupt signal p_cpl to indicate that the parity data in the external memory can be released.

According to a fourteenth aspect of the present invention, there is provided the second media interface controller according to the fourteenth aspect of the present invention, in response to a program command to write user data to the page stripe, the check data calculator xors the user data corresponding to the program command with data in the cache, the xored result being stored in the cache; and the media interface controller sends the programming command to the corresponding logic unit.

According to a fourteenth aspect of the present invention, there is provided the third media interface controller according to the fourteenth aspect of the present invention, the media interface controller or the check data calculator transmitting the check data to the external memory in response to completion of the check data calculation of the page stripe, generating the interrupt signal r_cpl, and transmitting the interrupt signal r_cpl to the CPU.

According to a fourteenth aspect of the present invention, there is provided a fourth media interface controller according to the fourteenth aspect of the present invention, wherein in response to the interrupt signal r_cpl, the CPU generates a program command, writes check data in the external memory to the page stripe, and indicates that it is not necessary to calculate the check data for the generated program command.

According to a fourteenth aspect of the present invention, there is provided the fifth medium interface controller according to the fourteenth aspect of the present invention, wherein the CPU discards the check data in the external memory if the interrupt signal p_cpl indicates that the write operation is successful, in response to the interrupt signal p_cpl.

According to a fourteenth aspect of the present invention, there is provided the sixth media interface controller according to the fourteenth aspect of the present invention, wherein in response to the interrupt signal p_cpl, if the interrupt signal p_cpl indicates that the write operation fails, the CPU generates a second program command, writes the check data in the external memory to the page stripe, and indicates that it is not necessary to calculate the check data for the generated second program command.

According to a fourteenth aspect of the present invention, there is provided the seventh media interface controller according to the fourteenth aspect of the present invention, wherein if the interrupt signal p_cpl indicates that the write operation fails, the CPU reads out the data that has been written in the page stripe and generates a program command to write the data read out from the page stripe to another page stripe, and generates a program command to write the check data in the external memory to the other page stripe and indicates that it is not necessary to calculate the check data for the generated program command.

According to a fourteenth aspect of the present invention, there is provided an eighth media interface controller according to the fourteenth aspect of the present invention, in response to receiving the interrupt signal r_cpl, the cache indicated by the interrupt signal r_cpl may be released or allocated to generate check data for other page stripes, and the address indicated by r_cpl is recorded.

A fifteenth aspect of the present invention provides a solid state storage device comprising a host interface, a control unit for controlling data transfer between the interface, the NVM chip and a firmware memory, an external memory and one or more NVM chips, one NVM chip comprising one or more logic units, the control unit comprising one or more media interface controllers as claimed in claims 15-23, one or more of the media interface controllers further coupled to a parity data calculator and a cache for xoring input data to obtain parity data.

A sixteenth aspect of the invention provides a program comprising instruction code which, when loaded into a solid state storage device and executed on a controller of the solid state storage device, causes the controller to perform a method of handling IO commands as described in the eleventh to thirteenth aspects of the invention, and possible implementations thereof.

A seventeenth aspect of the present invention provides a solid state storage device comprising one or more processors and a storage, the one or more processors executing the method of handling IO commands as described in the eleventh to thirteenth aspects and their possible embodiments by running a program in the storage.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a prior art solid state storage device;

FIG. 2 is a schematic view of a page stripe configuration;

FIG. 3 is a schematic diagram of control components of a solid state storage device in accordance with a first embodiment of the present invention;

FIG. 4 is a schematic diagram of a media interface controller according to a second embodiment of the present invention;

FIG. 5 is a schematic diagram of a media interface controller according to a third embodiment of the present invention;

FIG. 6 is a flowchart of IO command processing in a fourth embodiment of the present invention;

FIG. 7 is a schematic diagram of a media interface controller according to a fifth embodiment of the present invention; and

fig. 8 is a flowchart of IO command processing in the sixth embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

FIG. 3 is a block diagram of control components of a solid state storage device according to an embodiment of the present invention. The control component 104 of the solid state storage device includes therein a host interface 310, a front end processing module 320, a flash memory management module 330, and one or more media interface controllers 340. The host interface 310 is used to exchange commands and data with a host. Flash management module 330 provides logical address to physical address mapping, wear leveling, garbage collection, etc. functions and generates IO commands to be sent to media interface controller 340. The media interface controller is coupled to the NVM chip 105. The media interface controllers have one or more, each coupled to a respective NVM chip 105. The media interface controller receives the IO command and issues IO commands (commands such as read, program, erase, pause, read feature and/or set feature) to the NVM chip according to the IO command.

In one example, the media interface controller provides multiple queues with different priorities (e.g., queue 342 and queue 344, where queue 342 is a high priority queue and queue 344 is a low priority queue) to receive IO commands. The flash management module 330 fills the read command into the high priority queue of the interface controller, causing the media interface controller to process the read command preferentially. While program commands, erase commands, and/or read commands (e.g., read commands that do not require processing delays) are filled into the low priority queues of the media interface controller. The media interface controller will prioritize commands in the high priority queue 342 and process commands in the low priority queue 344. It will be appreciated that other types of IO commands may be filled into the high priority queue by the flash management module.

In accordance with an embodiment of the present invention, the media interface controller typically prioritizes IO commands in the high priority queue and handles IO commands in the low priority queue at a low priority.

According to one embodiment of the invention, in order to reduce the processing delay of IO commands of a solid state storage device, if there is a program command (P1) or an erase command (E1) being executed on a logic unit (L1), there is a read command (R1) to be processed in a high priority queue. It should be noted that the read command R1 accesses the same logic cell (L1) as the program command P1. The media interface controller issues a pause command to the logic unit (L1), pauses the processing of the program command (P1) or the erase command (E1), and processes the read command (R1). And after the read command (R1) processing is completed, issuing a recovery command to the logic unit (L1), and recovering the processing of the program command (P1) or the erase command (E1).

It will be appreciated that the IO commands in the high priority queue/low priority queue may have a different morphology than the IO commands sent to the logic unit, but the same command in different phases, having a different morphology but the same meaning, is indicated with the same label (R1, P1, E1, etc.).

According to yet another embodiment of the present invention, the media interface controller discovers that there is a read command (R2) pending in the high priority queue and a program command (P2) pending in the low priority queue. The media interface controller does not process the read command (R2) first, but processes the program command (P2) in the low priority queue first. After issuing the programming command (P2) to the logic unit (L2), if the read command (R2) accesses the same logic unit (L2) as the programming command (P2), a pause command is issued to the logic unit (L2) to pause the processing of the programming command (P2). And the media interface controller processes the read command (R2) from the high priority queue, issues the read command (R2) to the logic unit (L2), and issues a resume command to the logic unit (L2) after the read command (R2) processing is completed, to resume processing of the program command (P2). If the read command (R2) accesses a different logical unit than the program command (P2), the read command (R2) is processed directly without suspending the program command (P2).

According to another embodiment of the invention, the media interface controller discovers a read command (R3) pending in the high priority queue and an erase command (E3) pending in the low priority queue. The media interface controller does not process the read command first (R3), but processes the erase command in the low priority queue first (E3). After issuing the erase command (E3) to the logical unit (L3), if the read command (R3) accesses the same logical unit (L3) as the erase command (E3), a suspend command is issued to the logical unit (L3) immediately to suspend the processing of the erase command (E3). And the media interface controller processes the read command (R3) from the high priority queue, issues the read command (R3) to the logic unit (L3), and issues a resume command to the logic unit (L3) after the read command (R3) processing is completed, to resume processing of the erase command (E3). If the read command (R3) accesses a different logical unit than the erase command (E3), the read command (R3) is processed directly without suspending the erase command (E3). Further, if a program (P4)/erase (E4) command accessing another logic unit (other logic unit than the logic unit L3) appears in the low priority queue next, a read command (R4) appears in the high priority queue, the program (P4)/erase (E4) command is executed, and the program (P4)/erase (E4) command is suspended, and then the read command (R4) is executed and the processing of the program (P4)/erase (E4) command is resumed.

Optionally, each logical unit has a corresponding media interface controller or an execution state of the media interface controller, such that IO commands being processed by the same media interface controller access the same logical unit. In this case, the media interface controller does not need to determine whether the read command and the program/erase command access the same logic unit, but issues a pause command to the logic unit to pause the processing of the program/erase command when the read command is received from the high priority queue after the program/erase is performed. Then, a read command is issued, and execution of the program/erase command is resumed after the read command is completed.

Example two

Fig. 4 is a block diagram of a media interface controller 440 according to an embodiment of the invention. The media interface controller includes a plurality of queues (e.g., queue 342 and queue 344). Each queue has a different priority, e.g., queue 342 is a high priority queue and queue 344 is a low priority queue. The media interface controller 440 includes a command scheduling module 410, a check data calculator 420. As an example, an XOR buffer (422/424/426) is also included in the check data calculator 420, the check data calculator 420 XORs the input data with the data in the XOR buffer (422/424/426) to obtain check data, and the calculated check data is stored in the XOR buffer (422/424/426).

Optionally, the media interface controller 440 is also coupled to DRAM (see FIG. 1, DRAM 110).

The command scheduling module 410 fetches commands from the queues 342/344 and executes the commands to access the NVM chips. For the program command, during the process of sending the data corresponding to the program command to the NVM chip, an XOR buffer (e.g., XOR buffer 422) is specified, and the check data calculator 420 performs an XOR operation on the data corresponding to the program command and the data buffered by the XOR buffer (e.g., XOR buffer 422), the result of the XOR operation being stored in the XOR buffer (e.g., XOR buffer 422).

By way of example, one physical page is allocated on each of the NVM chips 405/415/425 to construct a page stripe (S1). 2 physical pages in the page stripe (S1) are used to store user data, and 1 physical page is used to store parity data.

Command scheduler module 410 retrieves the programming command (P5) from the command queue, allocates XOR buffers (422), XORs the data of the programming command (P5) with XOR buffers (422), stores the calculation results in XOR buffers (422), and sends the programming command (P5) to NVM chip 405.

Next, command scheduling module 410 retrieves the programming command (P7) from the command queue, allocates XOR buffers (426), XORs the data of the programming command (P7) with XOR buffers (426), stores the calculation results in XOR buffers (426), and sends programming command (P7) to NVM chip 435.

Wherein the program command (P5) writes data to the page stripe (S1), and the XOR buffer (422) is occupied to generate check data for the page stripe (S1) before the page stripe (S1) is completely written. Similarly, the program command (P7) writes data to the page stripe (S2), and the XOR buffer (426) is occupied to generate check data for the page stripe (S2).

Next, a read command occurs in the high priority queue (R5), while a program command occurs in the low priority queue (P6). Although the read command (R5) has a higher priority than the program command (P6), in order to reduce the time taken for the XOR buffer (422), the command scheduling module 410 prioritizes the program command (P6), the program command (P6) writing data to the page stripe (S1). The data corresponding to the program command (P6) is exclusive-ored with the XOR buffer (422), and the exclusive-or result is stored in the XOR buffer (422). And send a program command (P6) to NVM chip 415.

At this time, since all 2 pages of user data to be written to the page stripe (S1) have been received, the data stored in the XOR buffer (422) is used as the check data of the page stripe (S1) and written to the NVM chip 425 (by generating the program command PX 5), and the XOR buffer (422) is released.

In an embodiment according to the invention, the data corresponding to the program command (P6) is exclusive-ored with the XOR buffer (422), and after the exclusive-or result is stored in the XOR buffer (422), the command dispatch module 410 processes the read command (R5) from the high priority queue 342. If the logic unit (L5) accessed by the read command (R5) has a program command (for example, program command P6/P7/PX 5) or an erase command being processed, a pause command is sent to the logic unit (L5), the program command or the erase command being executed on the logic unit (L5) is paused, the read command (R5) is sent to the logic unit (L5), and after the execution of the read command (R5) is completed, a resume command is sent to the logic unit (L5) to resume the paused program command or the paused erase command.

Optionally, the data corresponding to the program command is xored with an XOR buffer (e.g., XOR buffer 422), the exclusive or result is stored in the XOR buffer (e.g., XOR buffer 422), and after the program command is sent to the logic unit, the contents (e.g., user data or check data for page stripe (S1)) stored in XOR buffer (422) are written to DRAM (see fig. 1, DRAM 110), so that XOR buffer (422) can be released, and XOR buffer (422) is allocated to calculate the check data of another page stripe (e.g., page stripe (S3)). And in response to receiving a program command to write data to page stripe (S1), retrieving the contents of the stored XOR buffer (422) from the DRAM and storing to the XOR buffer (e.g., 422/426), and continuing to process the program command to write data to page stripe (S1).

Example III

FIG. 5 illustrates a media interface controller according to yet another embodiment of the present invention. In the embodiment of FIG. 5, the control component 104 (see FIG. 1) includes a plurality of media interface controllers (540/550). The media interface controller includes a plurality of queues (e.g., queues 542/544, 552/554). Each queue has a different priority, e.g., queue 542/552 is a high priority queue and queue 544/554 is a low priority queue. The media interface controller 540/550 is coupled to the verification data calculator 520. By way of example, the check data calculator 520 exclusive-ors the input data to obtain check data, and an XOR buffer (522/524/526) is further included in the check data calculator 520.

Optionally, the media interface controller 540/550 is also coupled to DRAM (see FIG. 1, DRAM 110).

Wherein media interface controller 540 is dedicated to accessing logical units (LUNs 505) and media interface controller 550 is dedicated to accessing logical units (LUNs 515). Thus, to access LUN 505, a corresponding command is added to queues 542/544, and to access LUN 515, a corresponding command is added to queues 552/554.

It will be appreciated that multiple sets of execution states may be stored in the media interface controller, each set of execution states being dedicated to accessing one of the logical units. The execution state of the medium interface controller is switched, so that at each moment, the medium interface controller is dedicated to accessing the (one) logic unit corresponding to the current execution state.

In the embodiment of FIG. 5, multiple media interface controllers (540/550) share the check data calculator 520, as well as the DRAM.

By way of example, in response to processing the program command (P10), the program command (P10) writes data to the page stripe (S10). The media interface controller 540 allocates an XOR buffer (522) for the programming command (P10), XORs the data corresponding to the programming command (P10) with the XOR buffer (522), stores the xored result in the XOR buffer (522), and sends the programming command (P10) to the LUN 505.

Next, a read command to be processed appears on the high priority queue 542 (R10). Since the media interface controller 540 is dedicated to accessing the logical unit (LUN 505), it is implied that both the read command (R10) and the program command (P10) access the logical unit (LUN 505). The media interface controller 540 finds that the programming command (P10) is executing on the LUN505, issues a pause command to the LUN505 in order to reduce the processing delay of the read command (R10), pauses the execution of the programming command (P10), and sends the read command (R10) to the LUN505. And in response to completion of the read command (R10) execution, issuing a resume command to the LUN505 to resume execution of the program command (P10).

Next, a read command to be processed appears on the high priority queue 542 (R11), and a program command to be processed appears on the low priority queue 544 (P11). And the program command (P10) has been executed. Since the media interface controller 540 is dedicated to accessing the logical unit (LUN 505), it is implied that both the read command (R11) and the program command (P11) access the logical unit (LUN 505), and the media access controller 540 need not check again whether the received command accesses the same logical unit. Although the read command (R11) has a higher priority than the program command (P11), the media access controller 540 preferentially processes the program command (P11). The program command (P11) is used to write data to the page stripe (S11). The media interface controller 540 allocates an XOR buffer (524) for the programming command (P11), XORs the data corresponding to the programming command (P11) with the XOR buffer (524), stores the xored result in the XOR buffer (524), and sends the programming command (P11) to the LUN505. Next, the media access controller 540 issues a suspend command to the LUN505, suspends execution of the program command (P11), and sends a read command (R11) to the LUN505. And in response to completion of the read command (R11) execution, issuing a resume command to the LUN505 to resume execution of the program command (P11).

Next, in response to the pending read command (R12) appearing on the high priority queue 552, the pending program command (P12) appearing on the low priority queue 554, since the media interface controller 550 is dedicated to accessing the logical unit (LUN 515), implying that both the read command (R12) and the program command (P12) access the logical unit (LUN 515), the media access controller 550 does not need to check again whether the received command accesses the same logical unit. Even if the read command (R12) has a higher priority than the program command (P12), the media access controller 550 preferentially processes the program command (P12). The program command (P12) is used to write data to the page stripe (S12). The media interface controller 550 allocates an XOR buffer (526) for the programming command (P12), XORs the data corresponding to the programming command (P12) with the XOR buffer (526), stores the exclusive or result in the XOR buffer (526), and sends the programming command (P12) to the LUN 515. Next, media access controller 550 issues a suspend command to LUN515, suspends execution of the program command (P12), and sends a read command (R12) to LUN 515. And in response to completion of read command (R12) execution, issuing a resume command to LUN515 to resume execution of programming command (P12).

Next, in response to the occurrence of a read command to be processed (R13) on the high priority queue 552, a program command to be processed (P13) is present on the low priority queue 554, and the media access controller 550 preferentially processes the program command (P13) even if the read command (R13) has a higher priority than the program command (P13). The program command (P13) is used to write data to the page stripe (S14). The media interface controller 550 allocates an XOR buffer for the program command (P13). Since the XOR buffers (522/524/526) are all occupied, the contents stored by one of the XOR buffers (e.g., XOR buffer 526) are transferred to the DRAM. Initializing the XOR buffer (526), xoring the data corresponding to the programming command (P13) with the XOR buffer (526), the exclusive-or result being stored in the XOR buffer (526), and sending the programming command (P13) to the LUN 515. Next, media access controller 550 issues a suspend command to LUN 515, suspends execution of programming command (P13), and sends a read command (R13) to LUN 515. And in response to completion of read command (R13) execution, issuing a resume command to LUN 515 to resume execution of program command (P13).

Next, whichever of the media interface controllers 540/550 receives a program command to write data to the page stripe (S12), the storage information for the page stripe (S12) of the XOR buffer (526) is transferred to the DRAM, and the previously stored contents of the XOR buffer for the page stripe (S12) are retrieved from the DRAM and stored into the XOR buffer (526).

Example IV

Fig. 6 shows a flowchart of an IO command processing method according to an embodiment of the present invention, which is used for processing IO commands in a queue by a media interface controller in the second embodiment and the third embodiment.

In one example, to reduce the processing delay of a read command by a program command, the media interface controller responds to commands that are pending in a command queue (e.g., queues 342/344 of FIG. 4, 542/544 of FIG. 5). If there are read commands pending in the high priority queue, programming commands from the low priority queue are executing (601); processing of programming commands from the low priority queue is suspended 632. To suspend processing of a program command, a program suspend command may be sent to the NVM that is executing the program command. And retrieving and processing read commands from the high priority queue 633. After the read command processing is completed, processing of the suspended program command is resumed (634). To resume processing of the suspended program command, a program resume command may be sent to the NVM for which the program command is intended.

In yet another example, to reduce the latency of programming commands to read commands and to reduce the time that programming commands occupy XOR cache resources, the media interface controller responds to commands that are pending in a command queue (e.g., queues 342/344 of fig. 4, 542/544 of fig. 5). If there are read commands to process in the high priority queue and programming commands to process in the low priority queue (610); then the programming command is preferentially fetched from the low priority queue and processed 611. To process a program command, the data of the program command to be written into the data XOR buffer of the NVM is xored, the result is stored in the XOR buffer, and the program command is sent to the NVM. Optionally, after the program command is sent to the NVM, the XOR cache is released (612). Still alternatively, the data in the XOR buffer may be moved to the DRAM before the XOR buffer is released, so that when the data in the XOR buffer is next needed, the data may be retrieved from the DRAM and moved to the XOR buffer. Next, processing of the program command is suspended (632). And processing read commands in the high priority queue 633. After the read command processing is completed, processing of the suspended program command is resumed (634).

In another example, to reduce the latency of processing read commands by erase commands, the media interface controller responds to commands that are pending in a command queue (e.g., queues 342/344 of FIG. 4, 542/544 of FIG. 5). If there are read commands to process in the high priority queue and erase commands to process in the low priority queue (620); then the erasure command is preferentially fetched from the low priority queue. And processing the erase command (621), for example, by sending the erase command to the NVM. Next, processing of the erase command is suspended by sending the erase suspend command to the NVM (622). And processing read commands in the high priority queue 633. After the read command processing is completed, processing of the suspended erase command is resumed (634).

Example five

FIG. 7 illustrates a media interface controller according to yet another embodiment of the present invention. In the embodiment of FIG. 7, media interface controller 740 includes a plurality of queues (e.g., queues 542/544). Each queue has a different priority, e.g., queue 542 is a high priority queue and queue 544 is a low priority queue. The media interface controller 740 is coupled to the verification data calculator 720. By way of example, the check data calculator 720 exclusive-ors the input data to obtain check data, and an XOR buffer (722/724/726) is also included in the check data calculator 720.

Optionally, the media interface controller 540 is also coupled to DRAM (see FIG. 1, DRAM 110).

Wherein the media interface controller 740 is dedicated to accessing the logical unit (LUN 505) and thus adds queues 542/544 for accessing the LUN 505, respectively.

It will be appreciated that multiple sets of execution states may be included in the media interface controller, each set of execution states being dedicated to accessing one of the logical units. The execution state of the media interface controller is switched such that at each instant the media interface controller is dedicated to accessing the logical unit(s) corresponding to the current execution state.

The media interface controller 740 shown in fig. 7 is also coupled to the CPU and DRAM via bus 730 to more efficiently process IO commands with the assistance of the CPU. The check data calculator 720 exchanges data with the DRAM through the bus 730, and instructs the CPU of interrupts including an interrupt (r_cpl) indicating completion of check data calculation for the page stripe, and an interrupt (p_cpl) indicating completion of write operation processing to the page stripe through the bus 730. It is to be appreciated that the interrupt (p_cpl) may also be generated by the media interface controller 740. The write operation processing to the page stripe is completed, meaning that the user data and the check data of the page stripe are written to NVM chip 105 by a plurality of program commands, and NVM chip 105 indicates that the plurality of program commands are all complete. In some cases, one or more programming commands fail to execute, and by responding to an interrupt (pcl), the CPU will also be aware of the programming command that failed to execute.

By way of example, data is written to a page stripe (S14), the page stripe (S14) including 3 physical pages for storing 2 pages of user data and 1 page of parity data. Wherein 1 page of user data has been written to the page stripe (S14). The media interface controller 740 receives a program command (P14), and the program command (P14) is used to write page 2 user data to the page stripe (S14). The check data for the page stripe (S14) is recorded in the XOR buffer (722) of the check data calculator 720. The media interface controller 740 allocates an XOR buffer (722) for the program command (P14), XORs data corresponding to the program command (P14) stored in the DRAM with data stored in the XOR buffer (722), stores the xored result in the XOR buffer (722), and transmits the program command (P14) to the LUN 505.

Next, since exclusive or calculation of all the user data of the page stripe (S14) has been completed, the check data (X1) for the page stripe (S14) is stored in the XOR buffer (722). The check data calculator 740 transfers the check data in the XOR buffer (722) to the DRAM via the bus, generates an interrupt (r_cpl) and sends it to the CPU (e.g., via the bus 730). The CPU knows that the check data for the page stripe (S14) has been calculated based on the interrupt (R_CPL), and that the memory location of the check data for the page stripe (S14) in the DRAM. Next, CPU or media interface controller 740 may initialize and allocate XOR buffers (722) to other page stripes to which data is to be written.

At any next time, the CPU fills the command queue 542/544 with a program command (P15) to write the parity data (X1) in the DRAM to the page stripe (S14), and indicates to the media interface controller 740 that the parity data need not be calculated for the program command (P15). And

Next, in response to the LUN505 indicating that the execution of the program command (P15) is completed, the media interface controller 740 generates an interrupt (p_cpl) to the CPU, in which the execution result of the program command (P15) is indicated. If the program command (P15) is successfully executed, the CPU discards the check data (X1) in the DRAM; if the program command (P15) fails to execute, the CPU generates another program command (P15) to write the verification data (X1) in the DRAM to the NVM chip again. Further, if the program command (P15) fails to be executed, since the page stripe (S14) is not completely written, it is necessary to read the data to which the page stripe (S14) has been written and write another page stripe.

With continued reference to FIG. 7, in another embodiment, in response to receiving and executing the program command (P14), check data (X1) for the page stripe (S14) is generated in the XOR cache (722). The media interface controller 740 writes the data (X1) in the XOR buffer (722) to the LUN505 through the program command (P16), and writes the data in the XOR buffer (722) to the DRAM through the bus. In response to the check data (X1) being written to the registers of the LUN505 and the DRAM, an interrupt (R_CPL) is generated to the CPU. In response to the interrupt (R_CPL), the CPU knows that the parity data (X1) has been sent to the LUN505 and that a copy of the parity data (X1) exists in the DRAM. Next, CPU or media interface controller 740 may initialize and allocate XOR buffers (722) to other page stripes to which data is to be written. And when the LUN505 indicates to the media interface controller 740 that the execution of the programming command (P16) is complete, the media interface controller 740 generates an interrupt (P_CPL) to indicate to the CPU that the operation on the page stripe (S14) is complete.

In the embodiment of fig. 7, when writing the page stripe, the XOR buffer may be released earlier, and the released XOR buffer may be allocated to other program commands, so that more program commands can be concurrently executed in the solid-state storage device, thereby reducing the limit of the limited XOR buffer resource on the number of concurrently executed program commands, reducing the probability that the program commands wait for the XOR buffer resource, reducing the processing delay of the program commands, and improving the performance of the solid-state storage device.

Example six

Fig. 8 shows a flowchart of an IO command processing method according to still another embodiment of the present invention. The media interface controller (see also FIG. 7, media interface controller 740)/check data calculator (see FIG. 7, check data calculator 720) cooperates with the CPU (see FIG. 7) to send IO commands to the logical units (see FIG. 7, e.g., LUN 505).

The CPU generates a programming command (P17) for writing user data to the logical unit (LUN 505) and writes the programming command to a command queue (see FIG. 7, queues 545/544) of the media interface controller (810).

Next, in response to receiving the programming command (P17), the media interface controller sends data corresponding to the programming command (P17) to the logical unit (LUN 505) (801). The check data calculator exclusive-ors the data corresponding to the program command (P17) with the data buffered by the XOR buffer (see also fig. 7, XOR buffer (722/724/726)), and the result is stored in the XOR buffer (722/724/726) (802). In response to completion of the check data calculation of the page stripe (S15), the check data calculator stores the check data of the XOR buffer (722/724/726) into the DRAM (see FIG. 7, also see FIG. 1, DRAM 110), generates an interrupt R_CPL, and sends the interrupt R_CPL to the CPU, and indicates to the CPU the address of the check data in the DRAM (803).

In response to receiving the interrupt R_CPL (820), the CPU generates a program command (P18) for writing check data in the DRAM or XOR buffer (722/724/726) to the logical unit (LUN 505) and sends it to the media interface controller (830). Optionally, in response to receiving the interrupt R_CPL (820), the CPU also releases the XOR buffer (722/724/726) indicated by the interrupt R_CPL or allocates it to generate check data for other page stripes. Still alternatively, the CPU also records the address of the check data in the DRAM indicated by the interrupt r_cpl; or in response to receiving the interrupt r_cpl (820), the CPU ignores the interrupt r_cpl.

In response to receiving the program command (P18), the media interface controller sends the verification data from the DRAM to the logical unit (LUN 505) (804), the verification data being the verification data for the page stripe (S15). Further, in response to the check data of the page stripe (S15) being written to the NVM, the media interface controller or the check data calculator generates an interrupt p_cpl and sends the interrupt p_cpl to the CPU and indicates its execution result of the check data programming to the CPU (805).

Next, in response to receiving the interrupt p_cpl, the CPU confirms the success or failure of the execution of the check data programming command (P18) (840). If successful, indicating that the data write to the page stripe (S15) is complete, the check data in the DRAM may be discarded (850); if it fails, the CPU generates a program command (P19) for writing the check data in the DRAM again into the logical unit (LUN 505), and sends it to the media interface controller. Alternatively, if the program command (P18) fails to execute, the CPU reads out data from the page stripe (S15), generates a program command (P20) for writing the data read out from the page stripe (S15) to the page stripe (S16), and writes the check data in the DRAM to the page stripe (S16).

The methods and apparatus of the present invention may be implemented in hardware, software, firmware, or any combination of the preceding. The hardware may include digital circuits, analog circuits, digital Signal Processors (DSPs), application specific legacy circuits (ASICs), and the like. The software may comprise computer readable programs which, when executed by a computer, implement the methods described herein.

The software of the present invention may also be stored in a computer readable storage medium, such as a hard disk, an optical disk, etc., which stores a program which, when executed by a device, causes the device to perform the above-described method.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An IO command processing method in which an IO command to be processed is acquired from a high-priority command queue or a low-priority command queue, and the IO command in the high-priority command queue is processed preferentially with respect to the low-priority command queue, comprising:

in response to completion of the second command processing, resuming processing of the first command;

wherein the first command of the first type is a program command or an erase command and the second command of the second type is a read command;

wherein at least one physical block within at least one first logical unit constitutes a first page stripe, the cache storing check data for the first page stripe, the IO command processing method further comprising:

in response to fetching and processing the first command from the low priority command queue, performing exclusive-or on data corresponding to the first command and data stored in the cache, and storing an exclusive-or result in the cache; storing the cached verification data to a DRAM; releasing the cache; or (b)

If the exclusive OR result of at least one page of user data in the first page stripe is stored in the cache; writing the cached verification data into the first page stripe; releasing the cache;

The method further comprises the steps of: if the exclusive OR result of the N pages of user data in the first page stripe is stored in the cache, sending the cached check data to the logic units corresponding to the P physical pages of the page stripe; storing the data in the cache to a DRAM; releasing the cache; if the write check data to one of the P physical pages is erroneous, the check data associated with the first page stripe is stored from the DRAM to the cache.

2. An IO command processing method in which an IO command to be processed is acquired from a high-priority command queue or a low-priority command queue, and the IO command in the high-priority command queue is processed preferentially with respect to the low-priority command queue, comprising:

if a first command of a first type accessing the first logic unit exists in the low-priority command queue and a second command of a second type accessing the first logic unit exists in the high-priority command queue, the first command is fetched and processed, data corresponding to the first command is sent to the first logic unit, processing of the first command is suspended, and the second command is fetched and processed; wherein the first command of the first type is a program command or an erase command and the second command of the second type is a read command;

3. The IO command processing method according to claim 1 or 2, further comprising: when a command accessing other logic units except the first logic unit exists in the high-priority command queue in the process of processing the first command, the processing of the first command is not suspended, and the command accessing the other logic units is processed.

4. The IO command processing method according to claim 1 or 2, further comprising: and placing the IO command into a high-priority command queue or a low-priority command queue according to the type of the IO command.

5. The IO command processing method of claim 4, wherein a read command is placed in a high priority command queue and a program command, an erase command, or a read command that does not require processing delay is placed in a low priority command queue.

6. The IO command processing method of claim 5, wherein when there is a read command to be processed in the high priority queue, if there is a program command or an erase command being processed on the first logic unit, if the read command accesses the first logic unit, suspending the program command or the erase command being processed, and taking the read command from the high priority command queue and processing; and resuming processing of the program command or the erase command in response to the read command processing being completed.

7. The IO command processing method according to claim 1, wherein if a read command to be processed is in the high-priority command queue, a program command or an erase command to be processed is in the low-priority command queue, and the program command or the erase command is taken out and processed in the low-priority command queue; and

If the read command and the programming command or the erasing command both access the first logic unit, suspending processing of the programming command or the erasing command, and taking out the read command from the high-priority command queue for processing; and

in response to the processing of the read command being completed, processing of the program command or the erase command is resumed.

8. The IO command processing method according to claim 1 or 2, further comprising: in response to a subsequent write of data to the first page stripe, reallocating the cache, transferring check data associated with the first page stripe from the DRAM to the cache, xoring user data corresponding to the programming command with the data in the cache, and storing the xored result in the cache; and sending the programming command to the logic unit.

9. The IO command processing method of claim 1, further comprising: distributing page strips; a cache is allocated.

10. The IO command processing method of claim 9, wherein in response to having written all user data to the first page stripe, the check data for the page stripe is written to P physical pages of the page stripe; the cache is released.

11. A media interface controller coupled to one or more NVM chips, each NVM chip including one or more logic cells; the media interface controller is further coupled to a high priority command queue and a low priority command queue, wherein if there is a first command of a first type accessing the first logical unit in the low priority command queue, the media interface controller fetches and processes the first command from the low priority command queue; when a second command accessing the first logic unit exists in the high-priority command queue in the process of processing the first command, the medium interface controller pauses the processing of the first command, and takes out and processes the second command; and in response to completion of the second command processing, the media interface controller resumes processing of the first command; wherein the first command of the first type is a program command or an erase command and the second command of the second type is a read command;

Wherein at least one physical block within at least one first logical unit constitutes a first page stripe, the cache storing parity data for the first page stripe;

if the exclusive OR result of the N pages of user data in the first page stripe is stored in the cache, sending the cached check data to the logic units corresponding to the P physical pages of the page stripe; storing the data in the cache to a DRAM; releasing the cache; if the write check data to one of the P physical pages is erroneous, the check data associated with the first page stripe is stored from the DRAM to the cache.

12. A media interface controller coupled to one or more NVM chips, each NVM chip including one or more logic cells; the medium interface controller is further coupled to the high priority command queue and the low priority command queue, wherein if a first command of a first type accessing the first logic unit exists in the low priority command queue and a second command of a second type accessing the first logic unit exists in the high priority command queue, the medium interface controller fetches and processes the first command from the low priority command queue, sends data corresponding to the first command to the first logic unit, and pauses processing of the first command, fetches and processes the second command; wherein the first command of the first type is a program command or an erase command and the second command of the second type is a read command;

And in response to completion of the second command processing, the media interface controller resumes processing of the first command;

wherein at least one physical block within at least one first logical unit forms a first page stripe, and caches check data for the first page stripe

13. The media interface controller of claim 12, wherein if a read command is pending in the high priority command queue, a program command or an erase command is pending in the low priority command queue, the media interface controller is configured to fetch and process the program command or the erase command in the low priority command queue; and

14. A media interface controller coupled to a logic unit, the media interface controller further coupled to a high priority command queue and a low priority command queue, wherein if there is a first command of a first type accessing the logic unit in the low priority command queue and there is a second command of a second type accessing the logic unit in the high priority command queue, the media interface controller fetches and processes the first command from the low priority command queue and sends data corresponding to the first command to the logic unit, and pauses processing of the first command, fetches and processes the second command; wherein the first command of the first type is a program command or an erase command and the second command of the second type is a read command;

15. A solid state memory device comprising a host interface, a control unit, a DRAM, and one or more NVM chips, the control unit being for controlling data transfer between the interface, the NVM chips, and a firmware memory, wherein the control unit comprises one or more media interface controllers as claimed in any one of claims 11-14.

16. A solid state storage device comprising one or more processors and memory, the one or more processors executing the IO command processing method of one of claims 1-10 by running a program in the memory.