CN113838875A - Preparation method of image sensor based on bare wafer - Google Patents

Preparation method of image sensor based on bare wafer Download PDF

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Publication number
CN113838875A
CN113838875A CN202010583460.7A CN202010583460A CN113838875A CN 113838875 A CN113838875 A CN 113838875A CN 202010583460 A CN202010583460 A CN 202010583460A CN 113838875 A CN113838875 A CN 113838875A
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layer
bare wafer
ion
doped layer
photosensitive
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CN113838875B (en
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刘斌武
肖德元
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

The invention provides a preparation method of an image sensor based on a bare wafer, which comprises the steps of providing the bare wafer, forming an ion doped layer in the bare wafer through ion implantation, forming a photosensitive functional structure on the upper surface of the bare wafer, providing a semiconductor substrate, bonding the bare wafer and the semiconductor substrate, thinning the bare wafer from one side of the bare wafer far away from the photosensitive structure to the ion doped layer, and preparing a light filtering functional structure on the ion doped layer. The preparation method of the image sensor based on the bare wafer can adopt the bare wafer to prepare the image sensor, reduces the process cost, can form a structure of the bare wafer, the ion doped layer and the bare wafer based on the formation of the ion doped layer, and can be used as an etching barrier layer in the subsequent thinning etching process to replace the traditional SOI structure.

Description

Preparation method of image sensor based on bare wafer
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a preparation method of an image sensor based on a bare wafer.
Background
A CMOS Image Sensor (CIS) is widely used in many fields, for example, in digital cameras and other electro-optical devices, because of its advantages of good performance, low power consumption, high integration level, and the like.
Back-illuminated image sensors (BSI CIS) are an emerging technology that has many advantages over conventional FSI CIS image sensors. However, the existing back-illuminated image sensor is generally manufactured using an SOI substrate, and the cost of the SOI wafer is too high, and therefore, how to reduce the cost and to use a simple manufacturing process is a key to mass-produce the image sensor.
Therefore, how to provide a method for manufacturing an image sensor to solve the above problems in the prior art is necessary.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a bare wafer-based image sensor, which is used to solve the problems of high manufacturing cost of the backside illuminated image sensor in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a bare wafer-based image sensor, the method comprising the steps of:
providing a bare wafer, and forming an ion doping layer in the bare wafer through ion implantation, wherein the upper surface of the ion doping layer is lower than that of the bare wafer;
forming a photosensitive functional structure on the upper surface of the bare wafer;
providing a semiconductor substrate, and bonding one side of the photosensitive functional structure, which is far away from the bare wafer, with the semiconductor substrate;
thinning the bare wafer from one side of the bare wafer far away from the photosensitive structure to the ion doped layer;
and preparing a light filtering functional structure on the ion doping layer.
Optionally, the ion doped layer comprises a nitrogen ion doped layer or an oxygen ion doped layer.
Optionally, the ion doping amount in the ion doping layer is between 1015-1016at/cm2To (c) to (d); the ion doping energy is between 150Kev-500 Kev.
Optionally, the etching rate of the ion doped layer is less than or equal to 2/3 of the etching rate of the bare wafer.
Optionally, the ion doped layer has a thickness between 200nm and 400 nm; the distance between the upper surface of the ion doped layer and the upper surface of the bare wafer is 300nm-500 nm.
Optionally, an ion implantation layer is formed in the bare wafer, the ion implantation layer is formed on the ion doping layer, and an upper surface of the ion implantation layer is lower than an upper surface of the bare wafer.
Optionally, the ion doping amount of the ion implantation layer is between 1011-1012at/cm2To (c) to (d); the thickness is between 100nm and 500 nm.
Optionally, forming the ion implantation layer further includes forming a surface epitaxial layer on the upper surface of the bare wafer.
Optionally, the photosensitive functional structure comprises a photosensitive layer and a metal interconnection layer formed on the photosensitive layer; the light filtering function structure comprises a light filtering structure and a lens structure formed on the light filtering structure.
Optionally, the step of removing the ion doped layer by using a wet etching process is further included after the bare wafer is thinned.
Optionally, the step of annealing the ion-doped layer is further included after the ion-doped layer is formed.
Optionally, the annealing temperature of the annealing treatment is between 800 ℃ and 1100 ℃, and the annealing time is between 5s and 30 s.
As described above, according to the method for manufacturing an image sensor based on a bare wafer of the present invention, the image sensor can be manufactured by using the bare wafer, so that the process cost is reduced, and based on the formation of the ion doped layer, the structure of the bare wafer, the ion doped layer and the bare wafer can be formed, and can be used as an etching barrier layer in the subsequent thinning etching process to replace the conventional SOI structure.
Drawings
FIG. 1 shows a process flow diagram for the fabrication of a graphic sensor of the present invention.
FIG. 2 is a schematic diagram of a bare wafer for manufacturing an image sensor according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating formation of an ion doped layer in the fabrication of an image sensor according to an embodiment of the invention.
FIG. 4 is a schematic structural diagram illustrating the formation of an annealed ion-doped layer in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 5 is a schematic diagram illustrating a structure of an ion implantation layer formed in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 6 is a schematic structural diagram illustrating a surface epitaxial layer formed in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 7 is a schematic structural diagram illustrating a photosensitive functional structure formed in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 8 is a schematic structural diagram illustrating bonding of a bare wafer and a semiconductor substrate in the fabrication of an image sensor according to an embodiment of the invention.
Fig. 9 is a schematic structural diagram of a thinned bare wafer in the fabrication of an image sensor according to an embodiment of the invention.
FIG. 10 is a schematic structural diagram of wet etching removal of an ion-doped layer in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 11 is a schematic structural diagram of a structure for forming a light filtering function in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 12 is a schematic diagram illustrating a structure of an encapsulation layer formed in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 13 is a schematic structural diagram of a thinned semiconductor substrate in the fabrication of an image sensor according to an embodiment of the present invention.
FIG. 14 is a schematic diagram illustrating a structure of connecting pillars formed in the fabrication of an image sensor according to an embodiment of the present invention.
Description of the element reference numerals
100 bare wafer
101 ion doped layer
102 annealing the ion doped layer
103 ion implantation layer
104 surface epitaxial layer
105 photosensitive functional structure
106 photosensitive layer
106a photosensitive area
106b isolation region
107 metal connection layer
107a metal interconnection structure
107b dielectric layer
200 semiconductor substrate
300 light filtering functional structure
301 light filtering structure
302 lens structure
303 anti-reflective barrier layer
304 encapsulation layer
305 connecting column
S1-S5
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, a method for manufacturing a bare wafer-based image sensor is provided, the method comprising the steps of:
s1: providing a bare wafer, and forming an ion doping layer in the bare wafer through ion implantation, wherein the upper surface of the ion doping layer is lower than that of the bare wafer;
s2: forming a photosensitive functional structure on the upper surface of the bare wafer;
s3: providing a semiconductor substrate, and bonding one side of the photosensitive functional structure, which is far away from the bare wafer, with the semiconductor substrate;
s4: thinning the bare wafer from one side of the bare wafer far away from the photosensitive structure to the ion doped layer;
s5: and preparing a light filtering functional structure on the ion doping layer.
The semiconductor structure and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings. The method for manufacturing a semiconductor structure provided by the present invention is not limited to the above-mentioned sequence of steps, and can be adjusted according to common knowledge in the art, and this embodiment provides only one example of the method for manufacturing a semiconductor structure of the present invention.
First, as shown in S1 of fig. 1 and fig. 2-3, step S1 is performed to provide a bare wafer 100, and an ion doped layer 101 is formed in the bare wafer 100 by ion implantation, wherein an upper surface of the ion doped layer 101 is lower than an upper surface of the bare wafer 100. In the invention, the image sensor is prepared based on the bare wafer 100, and the problems of high cost and the like of the preparation by adopting the SOI substrate can be solved. The material of the bare wafer 100 may be silicon, germanium (Ge), or the like, and in this embodiment, is selected to be monocrystalline silicon.
In addition, an ion doped layer 101 is formed in the bare wafer 100 by ion implantation, and the ion doped layer 101 may be used as an etching stop layer in the subsequent etching process for manufacturing the image sensor. In one example, the ion doping amount in the ion doping layer 101 is between 1015-1016at/cm2May be, for example, 1.5 x 1015at/cm2、6*1015at/cm2、8*1015at/cm2(ii) a The ion doping energy is between 150Kev-500Kev, for example, 180Kev, 200Kev, 350 Kev. In another example, the ion doped layer 101 includes a nitrogen ion doped layer, nitrogen ion implantation is performed, nitrogen ions may form a Si — N polycrystalline material layer with Si in the die wafer 100 or nitrogen ions are doped in a gap of Si in the die wafer 100 to form the ion doped layer 101. Based on the above design, a structure similar to SOI, such as a silicon substrate-ion doped layer-silicon substrate, may be formed to prepare an image sensor, so that the ion doped layer may be used as an etching stop layer in a subsequent thinning process of the bare wafer 100, and it may be determined when to stop etching according to a difference in etching rate. In this embodiment, the dopant layer is selected to be a nitrogen or oxygen ion doped layer, and preferably a nitrogen doped dopant ion layer. Improvement in favor of etching rateAnd the machine monitoring is convenient.
As an example, the thickness of the ion doped layer 101 is between 200nm-400nm, as shown by d1 in fig. 3, and may be 250nm, 300nm, 350nm, for example; the distance between the upper surface of the ion doped layer 101 and the upper surface of the bare wafer 100 is between 300nm and 500nm, as shown by d2 in fig. 3, and may be, for example, 350nm, 400nm, or 450 nm. Thereby facilitating the fabrication of structural layers close to SOI.
As shown in fig. 4, as an example, a step of annealing the ion doping layer after forming the ion doping layer 101 is further included to form an annealed ion doping layer 102. Optionally, the annealing treatment is carried out at an annealing temperature between 800 ℃ and 1100 ℃, for example 850 ℃, 900 ℃, 1000 ℃. The annealing time for the annealing treatment is between 5s and 30s, and may be, for example, 10s, 15s, 20s, or 25 s. The extraction of the annealing treatment process can rearrange the doping ions in the ion doping layer 101 to form the annealed ion doping layer 102, thereby further facilitating the preparation of the image sensor instead of the SOI.
As an example, as shown in fig. 5, an ion implantation layer 103 is formed in the bare wafer 100, the ion implantation layer 103 is formed on the ion doped layer 102, and an upper surface of the ion implantation layer 103 is lower than an upper surface of the bare wafer 100.
The ion implantation layer 103 is formed on the ion doped layer 102, and the ion implantation layer 103 can reduce device leakage and reduce dark current. The ion implantation layer 103 may be a conventional graded implant layer (GradientImplant). In one example, the ion implantation layer 103 has an ion doping amount between 1011-1012at/cm2To (c) to (d); the thickness is between 100nm and 500nm, for example, 200nm or 300nm, wherein the dopant ions can be selected according to actual requirements, and in one example, the dosage of the dopant ions in the ion implantation layer 103 decreases in an arithmetic progression from the ion doped layer 102 to the surface of the bare wafer 100, of course, in other examplesThe doping dose can also be set in an arithmetic progression and decreased according to the actual requirement.
As shown in fig. 6, as an example, the step of forming the ion implantation layer 103 further includes forming a surface epitaxial layer 104 on the upper surface of the bare wafer 100. Wherein, in an example, the material of the surface epitaxial layer 104 includes but is not limited to Si, and the surface epitaxial layer 104 is formed by an epitaxial process. The thickness of the surface epitaxial layer 104 is between 3-4um and the resistivity is between 8-15 ohm cm, so that the surface damage of the bare wafer 100 can be repaired, and the implementation of replacing the SOI structure is further facilitated, in this example, the thickness of the surface epitaxial layer 104 is 3.5um and the resistivity is 10 ohm cm. In an example, the step of annealing the surface epitaxial layer 104 is further included after the surface epitaxial layer is formed.
Next, as shown in S2 of fig. 1 and fig. 7, step S2 is performed to form a photosensitive functional structure 105 on the upper surface of the bare wafer 100, wherein in an example, when the surface epitaxial layer 104 is formed, the photosensitive functional structure 105 is formed in the surface epitaxial layer 104, and in a cross-sectional view in a certain direction, the surface epitaxial layer 104 is not shown because the photosensitive functional structure is fabricated and thus the surface epitaxial layer 104 cannot be seen. As an example, the photosensitive functional structure 105 includes a photosensitive layer 106 and a metal interconnection layer 107 formed on the photosensitive layer 106. As an example, the photosensitive layer 106 includes a plurality of photosensitive regions 106a and Isolation regions 106b for isolating adjacent photosensitive regions 106a, a Photodiode (Photodiode) may be formed in the photosensitive region 106a, and is configured to convert a received external optical signal into an excitation electrical signal and an image output signal, and in addition, each photosensitive region 106a may be isolated by the Isolation regions 106b, in an example, each Isolation region 106b is composed of two parts, i.e., a Deep Trench Isolation structure (DTI) and a shallow Trench Isolation Structure (STI), which are disposed in an up-down correspondence manner in an example to isolate the photosensitive regions, in an example, the Deep Trench Isolation structure may be, but is not limited to, filled with silicon oxide, and the shallow Trench Isolation structure may be, but is not limited to, filled with silicon oxide.
In addition, in an example, the Metal interconnection layer 107 includes Metal interconnection structures (BEOL Metal)107a and dielectric layers (BEOL IMD)107b located between the Metal interconnection structures, the Metal interconnection structures 107a are located in the dielectric layers 107b, the dielectric layers 107b are used for insulating and isolating the Metal interconnection structures 107a, and in addition, the Metal interconnection layers 107 are electrically connected with the photosensitive layer 106, such as in a back-illuminated image sensor, the photodiode is used for converting a received external optical signal into an excitation electrical signal and an image output signal and outputting the excitation electrical signal and the image output signal through the Metal interconnection layers 107.
Next, as shown in S3 of fig. 1 and fig. 8, step S3 is performed to provide a semiconductor substrate 200, and bond the side of the photosensitive functional structure 105 away from the bare wafer 100 to the semiconductor substrate 200. The Bonding manner can be selected according to actual requirements, and in an example, the Bonding between the two can be achieved by forming a Bonding layer, i.e., forming a Bonding interface (Bonding interface) between the two, and the material of the Bonding layer includes, but is not limited to, an oxide. In addition, the semiconductor substrate 200 may be a supporting substrate structure formed by a single material layer, or a structure including a supporting substrate and a desired functional layer formed on the supporting substrate according to actual selection.
Next, as shown in S4 of fig. 1 and fig. 9-10, in step S4, the bare wafer 100 is thinned from the side of the bare wafer 100 away from the photosensitive structure 105 to the ion-doped layer 101 or the annealed ion-doped layer 102. The structure formed with the semiconductor substrate 200 is turned over to perform the above-mentioned thinning process, for example, a dry etching process may be used to perform thinning. The ion doped layer 101 or the annealed ion doped layer 102 may be used as an etching stop layer in the thinning etching process, and at this time, the ion doped layer 101 or the annealed ion doped layer 102 may replace the function of the intermediate oxide layer in the SOI. In one example, whether to stop etching can be determined by monitoring the etching rate during the etching thinning process, for example, when the etching rate is monitored by a machine table to change, the etching is stopped immediately. In an alternative example, the etching rate of the ion-doped layer 101 is less than the etching rate of the bare wafer 100, for example, 2/3, for example, 1/2, 1/3, 1/5, etc., which may be less than or equal to the etching rate of the bare wafer 100, so that thinning is stopped immediately when the etching rate is reduced, which may be realized by implanting ions, implantation dose, implantation energy, etc., into the ion-doped layer 101.
In addition, in an example, after the thinning is stopped, a step of performing a wet cleaning may be further included to further remove the ion doped layer 101 or the annealed ion doped layer 102, and for example, an acid cleaning, such as a cleaning with HF, may be performed. In another example, a Chemical Mechanical Polishing (CMP) process may be performed, for example, one CMP process after the acid cleaning, so that the interface of the prepared structure of bare wafer-ion doped layer-bare wafer may be further improved. Here, the bare wafer in the bare wafer-ion doped layer-bare wafer is not a finished bare wafer, which can be understood by those skilled in the art, for example, when the material of the bare wafer is silicon, a structure of silicon-ion doped layer-silicon is formed after ion implantation.
Finally, as shown in S5 of fig. 1 and fig. 11, step S5 is performed to prepare the light filtering functional structure 300 on the ion doping layer 102, and if the ion implantation layer 103 exists, to prepare the light filtering functional structure 300 on the ion implantation layer 103. In one example, the light filtering structure 300 includes a light filtering structure 301 and a lens structure 302 formed on the light filtering structure 301. In an example, the filtering structure 301 may be a color filter, and the filtering structure may convert incident light into corresponding color light, and may be formed by forming a filtering structure groove in the insulating layer and then filling the filtering structure groove with the filtering structure by an etching process, and may be formed by any RGB filter materials. In addition, as an example, the method further includes, after forming the filter structure 301: a lens structure 302 is formed on each of the filter structures 301, and in an example, the lens structure 302 is disposed in an up-and-down correspondence with each of the filter structures 301.
In addition, in an example, before forming the light filtering function structure 300, a step of forming an anti-reflection barrier layer 303 on the ion doping layer 102 or further on the ion implantation layer 103 is further included, a material of the anti-reflection barrier layer 303 includes but is not limited to silicon nitride, the anti-reflection barrier layer 303 may function as an anti-reflection layer (ARC), and may also function as an etching barrier layer of a subsequent process, for example, as an etching barrier layer of a trench between the light filtering structures formed by subsequent etching, so as to ensure that a sidewall of the trench and the like have good etching uniformity during etching, and a thickness of the trench and the like can be set according to actual requirements. In addition, a high-dielectric-constant dielectric layer can be formed before the anti-reflection barrier layer is formed, and the anti-reflection barrier layer is formed on the high-dielectric-constant dielectric layer.
As shown in fig. 12-14, after the optical filtering structure 300 is formed, a packaging process is further included, the image sensor can be manufactured by packaging using a conventional packaging process, in an example, a bonding process (glass bonding) is performed in fig. 12, a packaging layer 304 is formed, the material of which includes but is not limited to glass, then the step of grinding and thinning the semiconductor substrate 200 shown in fig. 13 is performed, and finally, a connection via 305 shown in fig. 14 is prepared, wherein the connection via can be a through silicon via (3D TSV). Of course, the method is not limited to the above steps, and may be selected according to the actual method.
In summary, the method for manufacturing an image sensor based on a bare wafer according to the present invention can adopt the bare wafer to manufacture the image sensor, so as to reduce the process cost, and can form a structure of the bare wafer, the ion doped layer and the bare wafer based on the formation of the ion doped layer, and the structure can be used as an etching barrier layer in the subsequent thinning etching process to replace the conventional SOI structure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. A method for preparing an image sensor based on a bare wafer is characterized by comprising the following steps:
providing a bare wafer, and forming an ion doping layer in the bare wafer through ion implantation, wherein the upper surface of the ion doping layer is lower than that of the bare wafer;
forming a photosensitive functional structure on the upper surface of the bare wafer;
providing a semiconductor substrate, and bonding one side of the photosensitive functional structure, which is far away from the bare wafer, with the semiconductor substrate;
thinning the bare wafer from one side of the bare wafer far away from the photosensitive structure to the ion doped layer;
and preparing a light filtering functional structure on the ion doping layer.
2. The method of claim 1, wherein the ion doped layer comprises a nitrogen ion doped layer or an oxygen ion doped layer.
3. The method of claim 1, wherein an ion doping amount in the ion doped layer is between 1015-1016at/cm2To (c) to (d); the ion doping energy is between 150Kev-500 Kev.
4. The method of claim 1, wherein an etching rate of the ion-doped layer is less than or equal to 2/3 of the etching rate of the bare wafer.
5. The method of claim 1, wherein the ion doped layer has a thickness of 200nm to 400 nm; the distance between the upper surface of the ion doped layer and the upper surface of the bare wafer is 300nm-500 nm.
6. The method of claim 1, wherein an ion implantation layer is formed in the bare wafer, the ion implantation layer is formed on the ion doping layer, and an upper surface of the ion implantation layer is lower than an upper surface of the bare wafer.
7. The method of claim 1, further comprising forming a surface epitaxial layer on the top surface of the die after forming the ion implanted layer.
8. The method of claim 1, wherein the photosensitive functional structure comprises a photosensitive layer and a metal interconnection layer formed on the photosensitive layer; the light filtering function structure comprises a light filtering structure and a lens structure formed on the light filtering structure.
9. The method of claim 1, further comprising removing the ion-doped layer by wet etching after thinning the bare wafer.
10. The method as claimed in any one of claims 1 to 9, wherein the method further comprises annealing the ion-doped layer after forming the ion-doped layer.
11. The method of claim 10, wherein the annealing is performed at an annealing temperature of 800-1100 ℃ for an annealing time of 5-30 s.
CN202010583460.7A 2020-06-23 Preparation method of image sensor based on bare wafer Active CN113838875B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110089524A1 (en) * 2009-10-16 2011-04-21 Sumco Corporation Semiconductor device and method of manufacturing the same
CN107578990A (en) * 2017-09-06 2018-01-12 德淮半导体有限公司 The forming method of imaging sensor
CN109192741A (en) * 2018-08-23 2019-01-11 德淮半导体有限公司 The forming method of back side illumination image sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110089524A1 (en) * 2009-10-16 2011-04-21 Sumco Corporation Semiconductor device and method of manufacturing the same
CN107578990A (en) * 2017-09-06 2018-01-12 德淮半导体有限公司 The forming method of imaging sensor
CN109192741A (en) * 2018-08-23 2019-01-11 德淮半导体有限公司 The forming method of back side illumination image sensor

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