JP4061609B2 - Image sensor having stretched pinned photodiode and method for manufacturing the same - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to an image sensor, that in particular related to CMOS (Complementary Metal Oxide Semiconductor) image sensor and a manufacturing method thereof with stretched pinned photodiode.
[0002]
[Prior art]
In general, a CMOS image sensor is a device that uses CMOS manufacturing technology to convert an optical image into an electrical signal, and creates a MOS transistor of the number of pixels and uses it to detect the output sequentially. Adopted. Compared to the CCD (Charge Coupled Device) image sensor, which is currently widely used as an image sensor, the CMOS image sensor has a simple driving method and can implement various scanning methods. The signal processing circuit is integrated on a single chip. It is well known that not only the product can be miniaturized, but also has the advantages of using a compatible CMOS technology, which can reduce the unit cost of manufacture and also has a very low power consumption.
[0003]
FIG. 1 is a circuit diagram of a unit pixel of a CMOS image sensor according to the prior art.
[0004]
As shown in FIG. 1, the unit pixel of the CMOS image sensor is composed of one pinned photodiode (PPD) and four NMOS transistors. The four NMOS transistors are a transfer transistor (102) for transferring the photocharge generated by the pinned photodiode (PPD) to the sensing node, and a reset transistor (for resetting the sensing node for the next signal detection). 104), a drive transistor (106) for performing the role of a source follower, and a select transistor (108) for outputting data to the output terminal in response to an address signal. Here, the reset transistor (104) and the transfer transistor (102) are composed of native NMOS transistors so that the charge transfer efficiency is improved. That is, a native NMOS transistor having a negative threshold voltage can prevent an electron loss caused by a voltage drop due to a positive threshold voltage and can improve charge transfer efficiency.
[0005]
FIG. 2 is a cross-sectional view of a unit pixel of a conventional CMOS image sensor.
[0006]
As shown in FIG. 2, the unit pixel of the conventional CMOS image sensor is P + silicon substrate (201), P-type-epi layer (202), P-type-well (203), field oxide film (204), gate oxide film (205), a gate electrode (206), an N− diffusion region (207), a P0 diffusion region (208), an N + diffusion region (209), and an oxide film spacer (210).
[0007]
A pinned photodiode (PPD) is a PNP junction structure in which a P-type epi layer (202), an N-diffusion region (207), and a P0 diffusion region (208) are stacked. The N-diffusion region (207) is stably and completely depleted so that the two P-type regions are equipotential to each other at 3.3V or lower (for example, 1.2V to 2.8V).
[0008]
In addition, since the transfer transistor having the transfer gate (Tx) is composed of a native transistor, the P-type epi layer (202), which functions as a channel under the transfer gate (Tx), has transistor characteristics (threshold voltage). And an ion implantation step for adjusting punch-through characteristics) can be omitted.
[0009]
Therefore, the NMOS transistor (native transistor) having a negative threshold voltage can maximize the charge transfer efficiency and is formed on the surface of the P-type epi layer (202) between the transfer gate (Tx) and the reset gate (Rx). and N + diffusion region (sensing node) is configured to amplify the potential of the sensing node with the amount of charge transport is considered a high concentration N + realm without LDD regions. On the other hand, since the P-type epi layer (202) has a lower substrate doping concentration than the P + silicon substrate (201), the P type epi layer (202) increases the depth of the depletion layer of the pinned photodiode. it is possible to increase the photosensitivity, it is possible to reduce crosstalk (cross talk) effect between the lower and the photogenerating deep in the recombination is a unit pixel of the depletion layer by the presence of P + silicon substrate (201) Because.
[0010]
Since the conventional pinned photodiode is formed in a certain region of the P-type-epi layer (202) between the field oxide film (204) and the transfer gate (Tx), it is a unit of the pinned photodiode without reducing the degree of integration. It was impossible to increase the area. In addition, since the conventional pinned photodiode cannot increase the unit area exceeding the design rule, if the design rule of the CMOS image sensor is 0.25 μm or less, the photosensitivity is significantly reduced and the resolution of the image sensor is increased. There was a downside.
[0011]

[Technical Problem to be Solved by the Invention]
The object of the present invention has been devised to solve the above-mentioned problems of the prior art, and it is possible to increase the area per unit pixel of the photodiode and thus increase the photosensitivity while maintaining the degree of integration. An image sensor that can be used and a method for manufacturing the image sensor.
[0012]
[Means for Solving the Problems]
In order to achieve the above object , the present invention provides a CMOS image sensor manufacturing method , the first step of preparing a first conductivity type semiconductor layer, and forming an interlayer insulating film on the entire surface of the semiconductor layer, in the interlayer insulating film, a second step of forming a contact hole exposing a portion of the pre-Symbol semiconductor layer in a region where the photodiode is formed, said to be in contact with the semi-conductor layer by embedding the contact holes, a third step of growing an epitaxial layer on the interlayer insulating film, a fourth step of the second conductivity type impurity is implanted into the epitaxial layer to the epitaxial layer on the second conductive type diffusion layer, first by implanting first conductivity type impurities prior Symbol second conductivity type diffusion layer, the first conductivity type diffusion layer on the surface of a second conductivity type diffusion layer with a thickness smaller than the thickness of the second conductive type diffusion layer a fifth stage floors for forming the front Stories second conductivity type diffusion layer and And a sixth step of serial pattern over two packaging a first conductivity type diffusion layer, pattern over two ring surface area of said first conductivity type diffusion layer, the semi-conductor layer and patterned the second conductivity type wide diffusion layers Ri by surface product of the portion in contact in the contact hole, PN junction is made form the interface of the second conductive type diffusion layer and the first conductivity type diffusion layer.
[0013]
Further, the present invention provides a first step of preparing a first conductivity type semiconductor layer, and forming an interlayer insulating film on the entire surface of the semiconductor layer, and before the region where the photodiode is formed in the interlayer insulating film. a second step of forming a contact hole exposing a portion of the serial semiconductor layer includes an inner wall surface of the contact hole, so as to cover the interlayer insulating film above, and, epitaxial to contact the semi-conductor layer a third step of growing a layer, the second conductivity type impurity is implanted into the epitaxial layer, and a fourth step of the epitaxial layer to the second conductive type diffusion layer, wherein on the interlayer insulating film first by removing the second conductivity type diffusion layer, before Symbol a fifth step of pattern over two ring a second conductivity type diffusion layer on the cylindrical shape, the ion implantation mask to expose the second conductive type diffusion layer prior Symbol of cylindrical shape a sixth step you formed, of the first conductivity type not Net objects to be injected into the second conductive type diffusion layer prior Symbol of the cylinder shape, the semiconductor layer and in direct contact, the surface of the cylindrical shape of the thick second conductivity type diffusion layer with a thickness smaller than and a seventh step of forming a first conductivity type diffusion layer beneath, the surface area of the pre-Symbol first conductivity type diffusion layer, the semi-conductor layer and the second conductive type diffusion layer of the cylindrical shape is in said contact hole widely Ri by surface product of part in contact, PN junction is made form the interface of the prior SL second conductivity type diffusion layer and the first conductivity type diffusion layer.
[0014]
Further, the present invention is an image sensor including a photodiode and a large number of MOS transistors electrically connected to the photodiode, wherein the first conductivity type semiconductor layer in which the large number of MOS transistors are formed; An insulating layer formed on the surface of the semiconductor layer including the MOS transistor and exposing the surface of the semiconductor layer on which the photodiode is formed, and the photodiode is formed by embedding the contact hole. A first conductivity type first epitaxial layer that is in contact with the semiconductor layer in a region and extends horizontally on the insulating layer, and a first conductivity type second epitaxial layer formed below the surface of the first epitaxial layer. and a diffusion region, the first conductivity type semiconductor layer, the second conductive type first epitaxial layer, and a second diffusion region of the first conductivity type It is stacked, that make up a stacked-type pinned photodiode of the PNP junction structures.
[0015]
According to another aspect of the present invention, there is provided an image sensor including a photodiode and at least one MOS transistor electrically connected to the photodiode , wherein the first conductivity type semiconductor layer includes the at least one MOS transistor; A cylinder-shaped second conductivity type first epitaxial layer that is in contact with the semiconductor layer in a region where the photodiode is formed and extends perpendicularly to the semiconductor layer, and is formed below the surface of the first epitaxial layer. A first conductivity type second diffusion region, and the first conductivity type semiconductor layer, the second conductivity type first epitaxial layer, and the first conductivity type second diffusion region are laminated. , that make up a cylindrical pin photodiode of PNP junction structures.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
[0017]
3 to 10 are cross-sectional views for explaining a method of manufacturing a unit pixel of a CMOS image sensor according to an embodiment of the present invention. A cylindrical pinned photodiode is a unit area of a pinned photodiode having a predetermined integration degree. To increase the photosensitivity.
[0018]
As illustrated in FIG. 3, energy in the range of about 50-100 KeV and 7 × 10 ¹² -9 × on a silicon substrate (311) with a P-type epi layer (312) having a specific resistance of about 10-100 Ωcm. 10 ¹² / cm ² range of dough's weight condition with B (boron) atoms ion-implanted with P-type - after forming a well (313), elements having a channel stop implant region thereunder in a known manner An isolation oxide film (314) is formed, and a gate electrode (316) having a mask oxide film (317) and a gate oxide film (315) on the upper and lower portions is formed. At this time, the gate electrode 316 may be formed of a polysilicon film, a transition metal silicide / polysilicon polycide structure, or a metal silicide film. As the transition metal silicide, for example, tungsten silicide, titanium silicide, tantalum silicide, molybdenum silicide, or the like can be used. The transfer gate (Tx) and the reset gate (Rx) have a channel size of about 1 μm or more, and the drive gate (MD) and the select gate (Sx) have a channel size of about 0.5 μm or less.
[0019]
Thereafter, as shown in FIG. 4, the first mask pattern 318 is formed so that the upper portion of the P-type well 313 region is opened, and the energy in the range of about 20-60 KeV and 1 × 10 ¹³ − 5 × the 10 ¹³ / cm ² range of dough's weight condition with P (phosphorus) atoms are ion-implanted to form the LDD low concentration N- region for (lightly Doped Drain) structure (319).
[0020]
Thereafter, as shown in FIG. 5, after removing the first mask pattern (318), about 2,000-2,500mm TEOS (Tetra-Ethyl-Ortho) is formed on the entire structure by low pressure chemical vapor deposition (LPCVD). -Silicate) The portion where the pinned photodiode is formed after forming the oxide spacer (320) on the exposed side wall of the gate electrode (316) by forming the oxide film and performing anisotropic plasma etching and a field oxide film (314) is a second mask pattern (321) formed so as to be covered, about 50-90KeV range of energy and ^{1 × 10 15 -9 × 10 15} / cm 2 range of dough's volume conditions As a result of ion implantation of As (arsenic) atoms, an N + region (322) serving as a source / drain region is formed. Thereafter, heat treatment is performed at about 850-950 ° C. in a nitrogen atmosphere for about 20-60 minutes. As a result, the As (arsenic) atoms implanted in the P-type-epi layer (312) in the region where the P-type well (313) is not formed are not disturbed by diffusion by other impurities. It increases and spreads sufficiently under the gate electrode (316) of the transfer gate (Tx) and the reset gate (Rx).
[0021]
Thereafter, as shown in FIG. 6, after removing the second mask pattern (321), a nitride film (323) is formed to a thickness of about 100-500 mm by LPCVD, and TEOS is formed on the nitride film (323). oxide film (324) formed at about 8,000-10,000Å thick, chemically the TEOS oxide film (324) - mechanical Migaku Ken: be one which Migaku Ken in (chemical mechanical polishing CMP) technique, the alumina such slurries using about 0.3~0.5kg / cm2 of Ken Migaku圧, by setting condition so as to Ken MigakuAtsushi of rotational speed and about 3,000~4,000Å about 30～40RPM, TEOS oxide The membrane (324) is flattened. Then, P-type regions photo diodes are formed - to form epitaxial layer (312) contact holes (325) exposing the photographic etching method. At this time, the contact hole (325) is formed so that a part of the P-type epi layer (312) is covered with the nitride film (323). This P0 diffusion region of the pin photodiode which is finally formed later is P-type - is a order to you to have equipotential are electrically well connected to the epitaxial layer (312).
[0022]
Thereafter, as shown in FIG. 7, a P-type epi layer (326) having a thickness of about 0.7 to 1.5 μm is formed on the entire surface of the substrate including the contact hole (325) by a step on the surface of the substrate. after forming, the entire ion-implanting P (phosphorus) atoms dough's weight conditions of energy and ^{1 × 10 12 -3 × 10 12} / cm 2 range of about 250-500KeV range, N- diffusion region (327 ), and contact holes (325) the bottom surface of the P-type - is formed on the surface of a epilayer (312).
[0023]
P (phosphorus) atom to form a N- diffusion region (327) is P-type - are injected into the epitaxial layer (326). That dew out the P-type - epitaxial layer (3 26) to P (phosphorus) by implanting ions into the N-type epitaxial layer (hereinafter, P-type - epi layer (326) N-type - epitaxial layer ( 326 ')). The N-type epi layer (326 ′) is formed by various epitaxial growth methods. Impurity concentration can be controlled between the growth of the epitaxial layer, P-type - can provide N-type impurity for the epitaxial layer grown by the epitaxial layer (312). On the other hand, a contact hole (325) the bottom surface of the P-type - epitaxial layer (312) on the even N-type - for epi layer (326 ') exists, N- diffusion region (327) contact holes (325) of the bottom surface P-type - is deeply formed under the surface of the epitaxial layer (312). In particular, it should be noted that the “A” region of the N-type epi layer (326 ′) is in direct contact with the P-type epi layer (312).
[0024]
Thereafter, as shown in FIG. 8, after the oxide film (328) is filled in the opening (200), the oxide film (328) outside the opening (200) is removed by etch back or CMP.
[0025]
Thereafter, as shown in FIG. 9, the N-type epi layer (326 ′) on the TEOS oxide film (324) is etched back so that the surface of the TEOS oxide film (324) is exposed, and the cylinder-shaped Complete the pattern of the N-type epi layer (326 '). Using the nitride film (323) as an etching stop layer, the TEOS oxide film (324) and the oxide film (328) buried in the opening (200) are removed by wet etching with an HF solution, and the nitride film By removing (323) with a phosphoric acid solution, an N-type epi layer (326 ′) patterned in a cylinder shape remains on the side wall and bottom surface of the contact hole (325). In addition, a third mask pattern (330) is formed so that the N-type epi layer (326 ′) patterned in a cylinder shape is exposed. BF ₂ is ion-implanted so that it is tilted by about 5-10 ° with an energy in the range of 20-40 KeV and a dose condition in the range of 3 × 10 ¹² -5 × 10 ¹² / cm ^2. A P0 diffusion region (331) having a thickness is formed. At this time, since the P0 diffusion region (331) is in direct contact with the surface of the P-type epi layer (312) in the vicinity of the channel stop ion implantation region, the pinned photodiode is stably depleted stably at a low voltage. Is possible .
[0026]
Thereafter, as shown in FIG. 10, by removing the third mask pattern (330), P0 diffusion region (331), N-type - epitaxial layer (326 '), and P-type - epitaxial layer (312) laminated is cylindrical pinned photodiode (300) stacked on top of the substrate PNP junction structure to complete the. Cylindrical pinned photodiode (300), P-type optical sensing area - in contact with the epitaxial layer (312), P-type - stretched in the vertical direction on the epitaxial layer (312).
[0027]
11 to 16 are cross-sectional views for explaining a method of manufacturing a unit pixel of a CMOS image sensor according to another embodiment of the present invention. A stacked pinned photodiode is a unit of a pinned photodiode having a predetermined integration degree. Increase the photosensitivity by increasing the area.
[0028]
As shown in FIG. 11, an energy in the range of about 50-100 KeV and 7 × 10 ¹² -9 × on a silicon substrate (411) having a P-type epi layer (412) having a specific resistance of about 15-25 Ωcm. 10 ¹² / cm ² range of dough's weight condition with B (boron) atoms ion-implanted with P-type - after forming a well (413), to form a field oxide film (414) in a known manner, the gate A gate electrode (416) composed of an oxide film (415) and a doped polysilicon film is formed. At this time, the channel size of the transfer gate (Tx) and the reset gate (Rx) is about 1 μm or more, and the channel size of the drive gate (MD) and the select gate (Sx) is about 0.5 μm or less.
[0029]
Thereafter, as shown in FIG. 12, the first mask pattern 417 is formed so that the upper portion of the P-type well 413 region is exposed, and energy in the range of about 20-60 KeV and 1 × 10 ¹³ − 5 × the 10 ¹³ / cm ₂ range of dough's weight condition with P (phosphorus) atoms are ion-implanted to form the lightly doped N- region (418) for the LDD structure.
[0030]
Thereafter, as shown in FIG. 13, after removing the first mask pattern (417), a TEOS oxide film (not shown) of about 2,000-2,500 mm is formed on the entire structure by low pressure chemical vapor deposition. and, by an anisotropic plasma etch, sidewall to form an oxide film spacer (419) of the exposed gate electrode (416), partial and field oxide pinned photodiode is formed (414) is A second mask pattern (420) is formed so as to be covered. In dough's weight conditions of energy and ^{1 × 10 15 -9 × 10 15} / cm 2 ranging from about 60-90KeV range using the second mask pattern (420) and the oxide film spacer (419) an ion implantation mask By ion-implanting As (arsenic) atoms, an N + diffusion region (421) serving as a source / drain region is formed.
[0031]
Thereafter, as shown in FIG. 14, after removing the second mask pattern (420), a planarization oxide film (422) such as a TEOS (Tetra-Ethyl-Ortho-Silicate) oxide film is formed at about 8,000-10,000. Å was formed at a thickness of, is intended to Migaku Ken planarization oxide film (422) by chemical mechanical Migaku Ken technology, research about 0.3~0.5kg / cm ² using a slurry such as alumina grinding pressure, to planarize the planarization oxide film (422) by setting condition so as to Ken MigakuAtsushi of rotational speed and about 3,000~4,000Å about 30～40RPM.
[0032]
Thereafter, as shown in FIG. 15, a contact hole for exposing the P-type-epi layer (412) in the region where the photodiode is formed is formed by photolithography. After the contact hole is formed, a P-type epi layer (427) having a thickness of about 0.5 to 1.5 μm is formed on the entire surface of the substrate including the contact hole . About 250-500KeV range of energy and ^{1 × 10 12 -3 × 10 12} / cm 2 range of dose (dose) amount condition P (phosphorus) atoms ion-implanted with P-type - N epi layer (427) in - type P to form a diffusion region - epitaxial layer (427) the N-type epitaxial layer (or less, P-type - epitaxial layer (427) the N-type - epitaxial layer (referred to 427 ')) because it, P-type -A portion of the epi layer (412) is in contact with the N-type epi layer (427 '). Furthermore, the BF ₂ in dough's weight conditions of energy and ^{3 × 10 12 -5 × 10 12} / cm 2 ranging from about 20-40KeV range by ion implantation, P0 spread with junction depth of about 0.1μm and out Region (426) is formed under the surface of the N-type epi layer (427 ').
[0033]
At this time, the method of forming the N-type epi layer (427 ′) is as follows. That is, after a polysilicon film or an amorphous silicon film is formed on the entire structure by a known method, the polysilicon film or the amorphous silicon film is irradiated with an energy beam such as a laser or a rod heater. The silicon film can be melted and crystallized to be transformed into a single crystal epitaxial silicon layer having a size of several μm to millimeter grains.
[0034]
Thereafter, as shown in FIG. 16, the P0 diffusion region (426) and the N- type epi layer (427 ′) are patterned by photolithography to form the P0 diffusion region (426), the N type epi layer (427 ′). And a stacked pinned photodiode having a PNP junction structure in which a P-type epi layer (412) is stacked. The stacked pinned photodiode is in contact with the P-type epi layer (412) in the light sensing region in the contact hole and extends in the horizontal direction on the oxide film (422).
[0035]
Although the technical idea of the present invention has been specifically described by the preferred embodiment, it should be noted that the above-described embodiment is for the purpose of illustration and not for the limitation.
[0036]
In addition, it is possible for a general expert in the technical field of the present invention to understand the possibility of various embodiments within the scope of the technical idea of the present invention.
[0037]
【The invention's effect】
As described above, the present invention can improve the resolution of the CMOS image sensor by forming a stretched pinned photodiode and increasing the unit area of the photodiode.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a unit pixel of a CMOS image sensor according to a conventional technique.
FIG. 2 is a cross-sectional view of a unit pixel of a CMOS image sensor according to a conventional technique.
FIG. 3 is a cross-sectional view for explaining a method for manufacturing a unit pixel of a CMOS image sensor according to an embodiment of the present invention.
[Fig. 4] Same as above [Fig. 5] Same as above [Fig. 6] Same as above [Fig. 7] Same as above [Fig. 8] Same as above [Fig. 9] Same as above [Fig. 10] Same as above [Fig. 11] CMOS image according to another embodiment of the present invention Sectional drawing for demonstrating the manufacturing method of the unit pixel of a sensor.
[Figure 12] Same as above [Figure 13] Same as above [Figure 14] Same as above [Figure 15] Same as above [Figure 16] Same as above [Description of symbols]
311 P + silicon substrate
411 P + silicon substrate
312 P + silicon substrate
326 P + silicon substrate
412 P + silicon substrate
427 P-type epi layer
313 P-epi layer
413 P-well
314 Field oxide film
414 Field oxide film
315 Gate oxide film
415 Gate oxide film
316 Gate electrode
416 Gate electrode
320 Oxide spacer
419 Oxide film spacer
322 N + diffusion region
421 N + diffusion region
331 P0 diffusion region
426 P0 diffusion region
326 'N-type epitaxial layer
427 'N-type epitaxial layer

Claims (24)

A CMOS image sensor manufacturing method comprising:
A first stage of preparing a semiconductor layer of a first conductivity type;
Forming an interlayer insulating film on the entire surface of the semiconductor layer, and forming a contact hole in the interlayer insulating film to expose a part of the semiconductor layer in a region where a photodiode is formed;
A third step of growing an epitaxial layer on the interlayer insulating film so as to fill the contact hole and contact the semiconductor layer;
A fourth step of injecting a second conductivity type impurity into the epitaxial layer to make the epitaxial layer a second conductivity type diffusion layer;
Impurities of the first conductivity type are implanted into the second conductivity type diffusion layer, and the first conductivity type diffusion is formed below the surface of the second conductivity type diffusion layer with a thickness smaller than the thickness of the second conductivity type diffusion layer. A fifth stage of forming a layer;
A sixth step of patterning the second conductive type diffusion layer and the first conductive type diffusion layer to form a stacked type photodiode,
The surface area of the patterned first conductivity type diffusion layer is wider than the area of the portion where the semiconductor layer and the patterned second conductivity type diffusion layer are in contact with the contact hole,
A CMOS image sensor manufacturing method, wherein a PN junction is formed at an interface between a second conductive type diffusion layer and the first conductive type diffusion layer.   2. The method of manufacturing a CMOS image sensor according to claim 1, wherein in the third step, the epitaxial layer is grown so as to fill the contact hole and extend horizontally on the interlayer insulating film.   2. The method of manufacturing a CMOS image sensor according to claim 1, wherein a dose amount of the second conductivity type impurity implanted in the fourth step is smaller than a dose amount of the first conductivity type impurity implanted in the fifth step.   2. The method of manufacturing a CMOS image sensor according to claim 1, wherein, in the second stage, the interlayer insulating film is polished after the interlayer insulating film is formed and before the contact hole is formed.   2. The CMOS according to claim 1, wherein in the third stage, the epitaxial layer is formed to a thickness of 0.5-1.5 μm, and in the fifth stage, the first conductivity type diffusion layer is formed to a junction depth of 0.1 μm. Image sensor manufacturing method. A CMOS image sensor manufacturing method comprising:
A first stage of preparing a semiconductor layer of a first conductivity type;
Forming an interlayer insulating film on the entire surface of the semiconductor layer, and forming a contact hole in the interlayer insulating film to expose a part of the semiconductor layer in a region where a photodiode is formed;
A third stage including an inner wall surface of the contact hole, covering the interlayer insulating film, and growing an epitaxial layer so as to contact the semiconductor layer;
A fourth step of injecting a second conductivity type impurity into the epitaxial layer to make the epitaxial layer a second conductivity type diffusion layer;
Removing the second conductivity type diffusion layer on the interlayer insulating film and patterning the second conductivity type diffusion layer into a cylinder shape; and
A sixth step of forming an ion implantation mask exposing the cylinder-shaped second conductivity type diffusion layer;
Impurities of the first conductivity type are injected into the cylinder-shaped second conductivity type diffusion layer, and are in direct contact with the semiconductor layer, and the second conductivity type diffusion is thinner than the thickness of the cylinder shape. Forming a first conductivity type diffusion layer below the surface of the layer, and
The surface area of the first conductivity type diffusion layer is wider than the area of the portion where the semiconductor layer and the cylindrical second conductivity type diffusion layer are in contact with the contact hole,
A CMOS image sensor manufacturing method, wherein a PN junction is formed at an interface between the second conductivity type diffusion layer and the first conductivity type diffusion layer. In the fourth stage,
7. The method of manufacturing a CMOS image sensor according to claim 6, wherein the second conductivity type impurity is also implanted into the semiconductor layer under the epitaxial layer grown on the bottom surface of the contact hole.   8. The method of manufacturing a CMOS image sensor according to claim 7, wherein in the third step, the epitaxial layer is grown on a bottom surface of the contact hole, a sidewall of the contact hole, and an upper surface of the interlayer insulating film. In the fifth stage,
7. The method of manufacturing a CMOS image sensor according to claim 6, wherein the second conductivity type diffusion layer on the interlayer insulating film is etched back, and the second conductivity type diffusion layer is patterned into a cylinder shape.   7. The method of manufacturing a CMOS image sensor according to claim 6, wherein the ion implantation mask exposes an upper portion and a side surface of the patterned second conductivity type diffusion layer.   11. The method of manufacturing a CMOS image sensor according to claim 10, wherein in the seventh step, the first conductivity type impurity is implanted by lick ion implantation.   7. The method of manufacturing a CMOS image sensor according to claim 6, wherein a dose amount of the second conductivity type impurity implanted in the fourth step is smaller than a dose amount of the first conductivity type impurity implanted in the seventh step.   7. The CMOS according to claim 6, wherein in the third step, the epitaxial layer is formed to a thickness of 0.7-1.5 μm, and in the seventh step, the first conductivity type diffusion layer is formed to have a junction depth of 0.1 μm. Image sensor manufacturing method.   12. The method of manufacturing a CMOS image sensor according to claim 11, wherein an angle of the lick ion implantation is 5 to 10 °. An image sensor comprising a photodiode and a number of MOS transistors electrically connected to the photodiode,
A first conductive type semiconductor layer in which a plurality of MOS transistors are formed;
An insulating layer formed on a surface of the semiconductor layer including the MOS transistor and having a contact hole exposing the surface of the semiconductor layer on which the photodiode is formed;
A first conductivity type first epitaxial layer that fills the contact hole, contacts the semiconductor layer in a region where the photodiode is formed, and extends horizontally on the insulating layer;
A second diffusion region of the first conductivity type formed under the surface of the first epitaxial layer,
The first conductive type semiconductor layer, the second conductive type first epitaxial layer, and the first conductive type second diffusion region are stacked to form a stacked pinned photodiode having a PNP junction structure. Sensor.   16. The image sensor according to claim 15, wherein the semiconductor layer is a second epitaxial layer epitaxially grown on a silicon substrate.   17. The image sensor according to claim 16, wherein the first epitaxial layer is epitaxially grown and contacts the second epitaxial layer. An image sensor comprising a photodiode and at least one MOS transistor electrically connected to the photodiode,
A semiconductor layer of a first conductivity type in which at least the one MOS transistor is formed;
A first epitaxial layer of a cylinder-shaped second conductivity type that is in contact with the semiconductor layer in a region where the photodiode is formed and extends perpendicular to the semiconductor layer;
A second diffusion region of the first conductivity type formed under the surface of the first epitaxial layer,
The first conductive type semiconductor layer, the second conductive type first epitaxial layer, and the first conductive type second diffusion region are stacked to form a cylindrical pinned photodiode having a PNP junction structure. Sensor. The MOS transistor includes a transfer gate formed in close proximity to the photodiode;
19. The image sensor according to claim 18, wherein the transfer gate includes a gate electrode having a mask insulating film formed on a surface thereof and an insulating film spacer formed on a side wall through a gate insulating film between the transfer gate and the semiconductor layer.   20. The image sensor according to claim 19, wherein the first epitaxial layer is formed on the transfer gate including the mask insulating film and the insulating film spacer.   21. The cylindrical sidewall of the first epitaxial layer having a cylindrical shape is separated from an element isolation film formed on the semiconductor layer around each unit pixel of the image sensor. The image sensor described. 22. The image sensor according to claim 21, wherein the channel stop ion implantation region below the element isolation film and the second diffusion region are electrically connected to each other.   23. The image sensor according to claim 22, wherein the semiconductor layer is a second epitaxial layer epitaxially grown on a silicon substrate.   24. The image sensor according to claim 23, wherein the first epitaxial layer is epitaxially grown and contacts the second epitaxial layer.

Images