CN113838805A - 一种FinFET结构的固相源掺杂方法 - Google Patents

一种FinFET结构的固相源掺杂方法 Download PDF

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CN113838805A
CN113838805A CN202010584726.XA CN202010584726A CN113838805A CN 113838805 A CN113838805 A CN 113838805A CN 202010584726 A CN202010584726 A CN 202010584726A CN 113838805 A CN113838805 A CN 113838805A
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明提供一种FinFET结构的固相源掺杂方法，Fin结构及其上的缓冲层、缓冲层上的硬掩膜层构成叠层，用作PMOS的叠层为第一结构；用作NMOS的叠层为第二结构；沉积BSG层覆盖叠层及基底上表面；去除第一结构上的BSG层；沉积PSG层覆盖第二结构上的BSG层、第一结构以及基底上表面；去除第二结构上的PSG层；在基底上表面的PSG层和BSG层上形成介质层；去除介质层以上的PSG层和BSG层；去除介质层将Fin结构侧壁剩余的PSG层和BSG层及基底上表面的PSG层和BSG层暴露；沉积帽层以覆盖叠层及Fin结构侧壁的PSG层和BSG层；退火以使Fin结构侧壁的PSG层中的磷和BSG层中的硅向Fin结构内部侧向扩散；刻蚀去除PSG层和BSG层以上的帽层后沉积氧化层；去除硬掩膜层及缓冲层，将Fin结构的顶部暴露。

Description

一种FinFET结构的固相源掺杂方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种FinFET结构的固相源掺杂方法。
背景技术
随着MOS规模的不断扩大，FinFET(鳍式晶体管)器件成为了CMOS的进一步技术拓展，FinFET器件结构的主要优点是其优越的静电完整性，它在很大程度上依赖于沟道形貌，图1a显示为现有技术中的FinFET结构示意图，其中FIN(鳍式部分)被金属栅极(MG)包裹在FIN顶部的深度H以下，FIN下部有更大的穿透风险，特别是当源漏沟道越深、掺杂浓度越高时。
目前APT(抗穿通)掺杂注入后，存在损伤问题，FIN的顶部掺杂浓度极低，载流子的迁移率较高，对FIN器件性能较好；FIN结构的底部掺杂较高，且掺杂体向上扩散到沟道的能力较差，不利于载流子迁移率的提高。
如图1b和图1c所示，图1b显示为现有技术中FIN结构体区中具有抗穿通(APT)掺杂分布示意图；图1c显示为FIN底部APT掺杂分布示意图，由此可见，FIN高度(HFIN)和宽度(WFIN)，APT掺杂峰位和尾部的参数是研究的关键。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种FinFET结构的固相源掺杂方法，用于解决现有技术中在FinFET结构的制程中，不能同时满足FIN底部的沟道中高迁移率和FIN底部抗穿透风险的问题。
为实现上述目的及其他相关目的，本发明提供一种FinFET结构的固相源掺杂方法，该方法至少包括以下步骤：
步骤一、提供基底，在所述基底上刻蚀形成多个Fin结构，所述Fin结构上形成有缓冲层；所述缓冲层上形成有硬掩膜层；所述Fin结构、缓冲层以及硬掩膜层构成叠层，其中用作PMOS的所述叠层为第一结构；用作NMOS的所述叠层为第二结构；
步骤二、沉积BSG层覆盖所述叠层及所述基底上表面；
步骤三、去除所述第一结构上的BSG层，保留所述第二结构上的BSG层；
步骤四、沉积PSG层，所述PSG层覆盖所述第二结构上的BSG层、所述第一结构以及所述基底上表面；
步骤五、去除所述第二结构上的所述PSG层；
步骤六、在所述基底上表面的所述PSG层和BSG层上形成填充所述叠层之间空间的介质层；所述介质层的厚度为所述Fin结构高度的三分之一；
步骤七、去除所述介质层以上的所述叠层侧壁和顶部的PSG层和BSG层；
步骤八、去除所述介质层将所述Fin结构侧壁剩余的PSG层和BSG层以及所述基底上表面的所述PSG层和BSG层暴露出来；
步骤九、沉积帽层以覆盖所述叠层及所述Fin结构侧壁的PSG层和BSG层；
步骤十、进行退火，以使所述Fin结构侧壁的PSG层中的磷和BSG层中的硅向所述Fin结构内部进行侧向扩散；
步骤十一、刻蚀去除PSG层和BSG层以上的帽层，并沉积氧化层填充所述叠层之间的空间；
步骤十二、刻蚀去除所述硬掩膜层以及缓冲层，将所述Fin结构的顶部暴露。
优选地，步骤一中的所述缓冲层为二氧化硅。
优选地，步骤一中的硬掩膜层为氮化硅、a-C、a-Si、AlN、SIOC、SIC中的一种。
优选地，步骤二中的所述BSG层为硼酸硅玻璃，其中硼的浓度为1E20～5E21/cm^3。
优选地，步骤四中的所述PSG层为磷酸硅玻璃，其中磷的浓度为1E20～5E21/cm^3。
优选地，步骤二中沉积的所述BSG层的厚度为2～5nm。
优选地，步骤四中沉积所述PSG层的厚度为2～5nm。
优选地，步骤六中的所述介质层包括有机层、SiBARC中的一种。
优选地，步骤六中形成所述介质层的方法为沉积法。
优选地，步骤九中沉积的所述帽层覆盖所述Fin结构侧壁的PSG层和BSG层的同时也覆盖了所述基底上表面的PSG层和BSG层。
优选地，步骤十中进行退火后，所述基底上表面的PSG层中的磷和BSG层中的硼向所述基底进行扩散。
优选地，步骤九中沉积所述帽层之前先将所述基底上表面的所述PSG层和BSG层去除，保留所述Fin结构侧壁的所述PSG层和BSG层。
优选地，步骤十一中沉积所述氧化层的方法为流动式化学气相沉积法。
优选地，步骤十一中刻蚀去除PSG层和BSG层以上的帽层之后，将剩余的所述PSG层、BSG层以及帽层全部去除，之后沉积所述氧化层填充所述叠层之间的空间。
如上所述，本发明的FinFET结构的固相源掺杂方法，具有以下有益效果：本发明的固相源掺杂方法分别针对NMOS和PMOS的Fin结构进行不同种类的抗穿透掺杂，并且利用一定厚度和高度以及一定浓度的硼酸硅玻璃和磷酸硅玻璃有效控制了Fin结构中的掺杂区域，可以阻止掺杂注入后对Fin结构的损伤，提高注入的抗穿透性，并且使得掺杂离子能有效地在Fin结构中进行扩散，改善磷和硼在Fin结构中的分布，从而提高载流子的迁移率，提高了器件的性能。
附图说明
图1a显示为现有技术中的FinFET结构示意图；
图1b显示为现有技术中FIN结构体区中具有抗穿通(APT)掺杂分布示意图；
图1c显示为现有技术中FIN底部APT掺杂分布示意图；
图2a至图2k显示为本发明实施例一中FinFET固相源掺杂方法过程中形成的各结构示意图；
图3a至图3e本发明实施例二中FinFET固相源掺杂方法过程中形成的各结构示意图；
图4显示为本发明的FinFET固相源掺杂方法流程图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图2a至图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
本发明提供一种FinFET结构的固相源掺杂方法，如图4所示，图4显示为本发明的FinFET固相源掺杂方法流程图。本实施例中，该方法包括以下步骤：
步骤一、提供基底，在所述基底上刻蚀形成多个Fin结构，所述Fin结构上形成有缓冲层；所述缓冲层上形成有硬掩膜层；所述Fin结构、缓冲层以及硬掩膜层构成叠层，其中用作PMOS的所述叠层为第一结构；用作NMOS的所述叠层为第二结构；如图2a所示，在所述基底01上刻蚀形成多个Fin结构A，所述基底为单晶硅，因此所述Fin结构也为单晶硅，所述Fin结构A上形成有缓冲层02；所述缓冲层02上形成有硬掩膜层03；制作所述Fin结构之前，现在所述基底上沉积一层缓冲材料，之后在所述缓冲材料上沉积一层硬掩膜材料，之后刻蚀所述硬掩膜材料、缓冲材料以及所述基底，形成如图2a中所示的结构。本发明中将所述Fin结构A、缓冲层02以及硬掩膜层03构成的结构定义为叠层，其中将用作PMOS的所述叠层定义为第一结构，如图2a中，假设右边的两个叠层用于制作PMOS，即为第一结构；本发明中将用于制作NMOS的所述叠层为第二结构，图2a中，假设最左边的一个叠层用于制作NMOS，即为第二结构。
本发明进一步地，本实施例的步骤一中的所述缓冲层02为二氧化硅。进一步地，本实施例的步骤一中的硬掩膜层03为氮化硅。在其他实施例中也可以为a-C、a-Si、AlN、SIOC、SIC中的一种。
步骤二、沉积BSG层覆盖所述叠层及所述基底上表面；如图2b所示，在所述基底01上表面、所述叠层的侧壁以及顶部沉积一层BSG层04，所述BSG层04覆盖了所述Fin结构A的侧壁、缓冲层02的侧壁以及硬掩膜层03的侧壁和顶部，同时覆盖了所述基底上表面。进一步地，步骤二中的所述BSG层为硼酸硅玻璃，其中硼的浓度为1E20～5E21/cm^3。更进一步地，本发明步骤二中沉积的所述BSG层的厚度为2～5nm，本实施例中沉积的所述BSG层的厚度为5nm。
步骤三、去除所述第一结构上的BSG层，保留所述第二结构上的BSG层；如图2c所示，将所述第一结构(右边两个用于制作PMOS的叠层)上的所述BSG层04去除，所述第二结构(左边一个用于制作NMOS的叠层)上的BSG层04被保留。
步骤四、沉积PSG层，所述PSG层覆盖所述第二结构上的BSG层、所述第一结构以及所述基底上表面；如图2c所示，对于所述第二结构，该步骤四中沉积的所述PSG层05覆盖了所述第二结构上的BSG层04，同时所述PSG层覆盖了所述第一结构的侧壁和顶部，并且所述PSG层覆盖了基底上表面。
进一步地，步骤四中的所述PSG层05为磷酸硅玻璃，其中磷的浓度为1E20～5E21/cm^3。再进一步地，本发明中步骤四中沉积所述PSG层的厚度为2～5nm，本实施例中沉积的所述PSG层的厚度为5nm。
步骤五、去除所述第二结构上的所述PSG层05；得到的结构如图2d所示，所述第一结构上的PSG层05被保留。
步骤六、在所述基底上表面的所述PSG层和BSG层上形成填充所述叠层之间空间的介质层；所述介质层的厚度为所述Fin结构高度的三分之一；进一步地，步骤六中的所述介质层包括有机层、SiBARC(抗反射层)中的一种。进一步地，步骤六中形成所述介质层的方法为沉积法。如图2e所示，该步骤六中沉积的所述介质层06填充所述叠层之间空间的同时覆盖了所述基底上的PSG层和BSG层，并且形成的所述介质层06的厚度为所述Fin结构A高度的三分之一。
步骤七、去除所述介质层以上的所述叠层侧壁和顶部的PSG层和BSG层；如图2f所示，构成所述第一、第二结构的所述叠层顶部的PSG层和BSG层被去除，同时构成所述第一、第二结构的所述叠层侧壁的一部分PSG层和BSG层也被去除，并且去除的PSG层和BSG层位于所述介质层06以上的部分。
步骤八、去除所述介质层将所述Fin结构侧壁剩余的PSG层和BSG层以及所述基底上表面的所述PSG层和BSG层暴露出来；如图2g所示，去除所述介质层后，位于所述第一结构侧壁剩余的PSG层以及位于所述第二结构侧壁剩余的BSG层被暴露，被暴露的所述BSG层和PSG层的高度为所述Fin结构A的高度的三分之一，同时位于所述基底上表面的所述PSG层和BSG层也被暴露。
步骤九、沉积帽层以覆盖所述叠层及所述Fin结构侧壁的PSG层和BSG层；如图2h所示，该步骤九沉积的所述帽层07覆盖了构成所述第一、第二结构的硬掩膜层03的顶部和侧壁，同时覆盖了所述缓冲层02的侧壁，也覆盖了位于所述PSG层和BSG层以上部分的Fin结构的侧壁，同时沉积的所述帽层07还覆盖了所述PSG层和BSG层。本发明进一步地，本实施例中的步骤九中沉积的所述帽层覆盖所述Fin结构侧壁的PSG层和BSG层的同时也覆盖了所述基底上表面的PSG层和BSG层。也就是说，所述PSG层和BSG层的一部分位于所述Fin结构的侧壁，另一部分位于所述基底上表面，沉积的所述帽层07将这两部分PSG层和BSG层全部覆盖。
步骤十、进行退火，以使所述Fin结构侧壁的PSG层中的磷和BSG层中的硅向所述Fin结构内部进行侧向扩散；进一步地，步骤十中进行退火后，所述基底上表面的PSG层中的磷和BSG层中的硼向所述基底进行扩散。如图2i所示，由于所述PSG层和所述BSG层分别包含有两部分，其中一部分分别依附于所述Fin结构的侧壁上，另一部分分别位于所述基底上表面，因此依附于所述Fin结构侧壁上的所述PSG层和所述BSG层分别向各自所在的Fin结构的内部进行侧向扩散；而位于所述基底上的所述PSG层和所述BSG层分别向其下方的基底中扩散，扩散后的分布显示如图2i所示。
步骤十一、刻蚀去除PSG层和BSG层以上(上方)的帽层，并沉积氧化层填充所述叠层之间的空间；如图2j所示，紧贴所述Fin结构侧壁的所述帽层被去除，同时所述缓冲层02侧壁的帽层以及所述硬掩膜层03侧壁和顶部的所述帽层07被全部去除，被保留的帽层依附于所述PSG层和BSG层；之后沉积所述氧化层08，该氧化层填充了所述叠层之间的空间，亦即所述氧化层08覆盖了所述叠层及所述叠层之间的所述帽层，进一步地，步骤十一中沉积所述氧化层的方法为流动式化学气相沉积法。沉积所述氧化层后对其进行退火和CMP(化学机械研磨)，直至露出所述硬掩膜顶部为止，形成的结构如图2j。
在其他实施例中，步骤十一中刻蚀去除PSG层和BSG层以上的帽层之后，也可以将剩余的所述PSG层、BSG层以及帽层全部去除，之后沉积所述氧化层填充所述叠层之间的空间。将剩余的所述PSG层、BSG层以及帽层全部去除更加有利于后续所述氧化层在所述叠层之间进行有效填充。
步骤十二、刻蚀去除所述硬掩膜层以及缓冲层，将所述Fin结构的顶部暴露。如图2k所示，刻蚀所述硬掩膜层和所述缓冲层，同时所述氧化层也被刻蚀，刻蚀至将所述Fin结构的顶部暴露为止，形成如图2k所示的结构。
实施例二
本实施例二与实施例一的不同之处在于，本实施例中在进行与实施例一相同的步骤八后、在步骤九中沉积所述帽层之前先将所述基底上表面的所述PSG层和BSG层去除，保留所述Fin结构侧壁的所述PSG层和BSG层。如图3a所示，该步骤九中基底上表面的所述PSG层和BSG层被去除，剩余的所述PSG层和BSG层分别位于Fin结构的侧壁。并且剩余的PSG层和BSG层的高度为所述Fin结构高度的三分之一。
之后进行步骤九、沉积帽层以覆盖所述叠层及所述Fin结构侧壁的PSG层和BSG层；本实施例中由于所述基底上表面的所述叠层之间的区域不存在PSG层和BSG层，因此，所述基底上表面所述叠层之间的区域也覆盖了一层所述帽层07，形成的结构如图3b所示。
本实施例的步骤十、进行退火，以使所述Fin结构侧壁的PSG层中的磷和BSG层中的硅向所述Fin结构内部进行侧向扩散，如图3c所示，由于所述基底上表面的Fin结构之间的区域不存在所述PSG层和BSG层，因此，依附于所述Fin结构侧壁的PSG层中的磷和BSG层中的硅分别进行侧向扩散进入Fin结构底部的区域，形成如图3c所示的结构。
步骤十一、刻蚀去除PSG层和BSG层以上的帽层，并沉积氧化层填充所述叠层之间的空间，形成的结构如图3d所示。
在其他实施例中，步骤十一中刻蚀去除PSG层和BSG层以上的帽层之后，也可以将剩余的所述PSG层、BSG层以及帽层全部去除，之后沉积所述氧化层填充所述叠层之间的空间。将剩余的所述PSG层、BSG层以及帽层全部去除更加有利于后续所述氧化层在所述叠层之间进行有效填充。
步骤十二、刻蚀去除所述硬掩膜层以及缓冲层，将所述Fin结构的顶部暴露，形成的结构如图3e所示。
综上所述，本发明的固相源掺杂方法分别针对NMOS和PMOS的Fin结构进行不同种类的抗穿透掺杂，并且利用一定厚度和高度以及一定浓度的硼酸硅玻璃和磷酸硅玻璃有效控制了Fin结构中的掺杂区域，可以阻止掺杂注入后对Fin结构的损伤，提高注入的抗穿透性，并且使得掺杂离子能有效地在Fin结构中进行扩散，改善磷和硼在Fin结构中的分布，从而提高载流子的迁移率，提高了器件的性能。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (14)

1.一种FinFET结构的固相源掺杂方法，其特征在于，该方法至少包括以下步骤：
步骤一、提供基底，在所述基底上刻蚀形成多个Fin结构，所述Fin结构上形成有缓冲层；所述缓冲层上形成有硬掩膜层；所述Fin结构、缓冲层以及硬掩膜层构成叠层，其中用作PMOS的所述叠层为第一结构；用作NMOS的所述叠层为第二结构；
步骤二、沉积BSG层覆盖所述叠层及所述基底上表面；
步骤三、去除所述第一结构上的BSG层，保留所述第二结构上的BSG层；
步骤四、沉积PSG层，所述PSG层覆盖所述第二结构上的BSG层、所述第一结构以及所述基底上表面；
步骤五、去除所述第二结构上的所述PSG层；
步骤六、在所述基底上表面的所述PSG层和BSG层上形成填充所述叠层之间空间的介质层；所述介质层的厚度为所述Fin结构高度的三分之一；
步骤七、去除所述介质层以上的所述叠层侧壁和顶部的PSG层和BSG层；
步骤八、去除所述介质层将所述Fin结构侧壁剩余的PSG层和BSG层以及所述基底上表面的所述PSG层和BSG层暴露出来；
步骤九、沉积帽层以覆盖所述叠层及所述Fin结构侧壁的PSG层和BSG层；
步骤十、进行退火，以使所述Fin结构侧壁的PSG层中的磷和BSG层中的硅向所述Fin结构内部进行侧向扩散；
步骤十一、刻蚀去除PSG层和BSG层以上的帽层，并沉积氧化层填充所述叠层之间的空间；
步骤十二、刻蚀去除所述硬掩膜层以及缓冲层，将所述Fin结构的顶部暴露。
2.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤一中的所述缓冲层为二氧化硅。
3.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤一中的硬掩膜层为氮化硅、a-C、a-Si、AlN、SIOC、SIC中的一种。
4.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤二中的所述BSG层为硼酸硅玻璃，其中硼的浓度为1E20～5E21/cm^3。
5.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤四中的所述PSG层为磷酸硅玻璃，其中磷的浓度为1E20～5E21/cm^3。
6.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤二中沉积的所述BSG层的厚度为2～5nm。
7.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤四中沉积所述PSG层的厚度为2～5nm。
8.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤六中的所述介质层包括有机层、SiBARC中的一种。
9.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤六中形成所述介质层的方法为沉积法。
10.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤九中沉积的所述帽层覆盖所述Fin结构侧壁的PSG层和BSG层的同时也覆盖了所述基底上表面的PSG层和BSG层。
11.根据权利要求10所述的FinFET结构的固相源掺杂方法，其特征在于：步骤十中进行退火后，所述基底上表面的PSG层中的磷和BSG层中的硼向所述基底进行扩散。
12.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤九中沉积所述帽层之前先将所述基底上表面的所述PSG层和BSG层去除，保留所述Fin结构侧壁的所述PSG层和BSG层。
13.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤十一中沉积所述氧化层的方法为流动式化学气相沉积法。
14.根据权利要求1所述的FinFET结构的固相源掺杂方法，其特征在于：步骤十一中刻蚀去除PSG层和BSG层以上的帽层之后，将剩余的所述PSG层、BSG层以及帽层全部去除，之后沉积所述氧化层填充所述叠层之间的空间。
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