CN113835487B - System and method for realizing memory pool expansion of high-density server - Google Patents

System and method for realizing memory pool expansion of high-density server Download PDF

Info

Publication number
CN113835487B
CN113835487B CN202111080761.9A CN202111080761A CN113835487B CN 113835487 B CN113835487 B CN 113835487B CN 202111080761 A CN202111080761 A CN 202111080761A CN 113835487 B CN113835487 B CN 113835487B
Authority
CN
China
Prior art keywords
memory
port
cpu
expansion
server
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111080761.9A
Other languages
Chinese (zh)
Other versions
CN113835487A (en
Inventor
张明哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Inspur Intelligent Technology Co Ltd
Original Assignee
Suzhou Inspur Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Inspur Intelligent Technology Co Ltd filed Critical Suzhou Inspur Intelligent Technology Co Ltd
Priority to CN202111080761.9A priority Critical patent/CN113835487B/en
Publication of CN113835487A publication Critical patent/CN113835487A/en
Application granted granted Critical
Publication of CN113835487B publication Critical patent/CN113835487B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/184—Mounting of motherboards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/185—Mounting of expansion boards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a system and a method for realizing the expansion of a memory pool of a high-density server, wherein the system comprises a server main board card and a memory expansion card; the server main board card is provided with a CPU, the CPU is provided with an integrated memory controller and a PE port, and the integrated memory controller is connected with an integrated memory; the memory expansion card is provided with a memory quick controller which is connected with an expansion memory; the memory rapid controller is connected with the PE port of the CPU. According to the system and the method for realizing the memory pool expansion of the high-density server, the memory expansion is realized through the cooperation of the CPU and the memory quick controller, and the system and the method can be used for a single CPU and a plurality of CPUs, so that the scheme that the original memory is increased only for increasing the server board card is avoided, the cost is reduced, the cache consistency among the CPUs is improved, PE port resources of the CPUs are more balanced, and the performance of the CPUs is exerted to the greatest advantage.

Description

System and method for realizing memory pool expansion of high-density server
Technical Field
The invention belongs to the technical field of server memory expansion, and particularly relates to a system and a method for realizing high-density server memory pool expansion.
Background
With the rapid development of servers, the application fields of the servers are more and more, and the demands on the capacity of the hard disk, the capacity of the memory, the number of GPUs and the number of cores of the CPU of the servers are more and more. With the increasing demand for CPU functions, the CPU package is increasingly larger, and the current CPU package size reaches 102mmx142mm, so that the normal 2U (2 x44 mm) 2-way server motherboard cannot meet the 24 (2 DPC) sizes of each CPU, and the 19 inch cabinet with 48 memories can be put down, so that the normal 2U 2-way motherboard can only support 24 memories, namely, each CPU outputs 12 (1 DPC).
The standard size of the traditional 2U 2-way motherboard is 425mm in width, the size of the new CPU package plus 24 (2 DP) memories is 277mm, the size of the 2-way motherboard is 277mm x 2=554 mm, therefore, the new CPU package plus 24 (2 DP) memories cannot be put down in a standard cabinet of 19 inches, and therefore, under the condition of the latest CPU, the current scheme can only use a scheme of 1DPC, namely 2 CPUs, and each CPU outputs a scheme of 24 memories in total to meet the size of the 425mm motherboard.
Compared with the prior mainboard size, the existing scheme cannot meet the main stream requirements of most customers in memory quantity and capacity, and the additional mainboard expansion scheme is needed to expand the memory, so that the price is far beyond expectations.
This is a deficiency of the prior art, and therefore, it is desirable to provide a system and method for implementing high-density server memory pool expansion in response to the above-mentioned deficiencies of the prior art.
Disclosure of Invention
Aiming at the defect that the increase of the prior CPU packaging in the prior art causes that the original size of a main board cannot meet the requirements of the quantity and capacity of the memory, and the additional expansion of the main board is needed to expand the memory and the cost is increased, the invention provides a system and a method for realizing the expansion of a memory pool of a high-density server, so as to solve the technical problems.
In a first aspect, the present invention provides a system for implementing expansion of a memory pool of a high-density server, including a server motherboard and a memory expansion card;
the server main board card is provided with a CPU, the CPU is provided with an integrated memory controller and a PE port, and the integrated memory controller is connected with an integrated memory;
the memory expansion card is provided with a memory quick controller which is connected with an expansion memory;
the memory rapid controller is connected with the PE port of the CPU.
Further, the memory rapid controller is provided with a CXL port;
the CXL port is connected with the PE port. And the CPU is connected with the CXL port of the memory rapid controller through the PE port to expand the memory.
Further, the CXL port is an X16 model CXL port;
the CXL port is connected with the PE port through an X16 data line. The PE ports are connected with CXL ports in a one-to-one correspondence manner, and support X16 data lines.
Further, the CXL port is an X16 model CXL port;
the number of PE ports of the CPU is at least two;
wherein, two PE ports are connected with CXL port through an X8 data line respectively. The CXL port can be simultaneously connected with two PE ports of the same CPU, namely an X16 signal of the CXL port is simultaneously connected with the two PE ports of the same CPU through two X8 data lines, so that when a server main board system is designed, the average resource is achieved, the power and the PE ports are uniformly distributed, and the layout and the wiring of the server main board are facilitated; and when DDR data transmission is performed, the transmission delay is better than the situation that one CXL port is connected with a single PE port through an X16 data line.
Further, the CXL port is an X16 model CXL port;
the number of the CPUs is at least two;
the PE port of each CPU is connected with the CXL port through an X8 data line respectively. The CXL port can be simultaneously connected with two PE ports arranged on different CPUs, namely X16 signals of the CXL port are simultaneously connected with the two PE ports of the different CPUs through two X8 data lines, so that cache consistency of the different CPUs is guaranteed, the transmission rate is more stable and reliable compared with the situation of connection with the PE ports of the same CPU, the data delay is lower, and the PE port resource balance of the CPU is realized.
Further, the CXL port is an X16 model CXL port;
the number of the CPUs is two, and the CPU comprises a first CPU and a second CPU;
each CPU is provided with three integrated memory controllers, each integrated memory controller comprises two control units, and each control unit is connected with one integrated memory;
the number of PE ports of each CPU is six;
the number of the memory quick controllers is twelve;
each PE port is connected with one or two memory fast controllers. When each PE port is connected with one memory quick controller, one memory quick controller is correspondingly connected with one PE port at the same time, and the PE port is connected with the CXL port through an X16 data line; when each PE port is connected with two memory quick controllers, each memory quick controller is correspondingly connected with two PE ports at the same time, and the two PE ports are two PE ports of the same CPU, or the two PE ports are two PE ports of different CPUs;
the server main board card supports 2 new packaged CPUs of the 2U 2-way server and a plurality of memory quick controllers to expand CXL memory pools, the quantity and the capacity of memories required to be expanded can be customized and allocated according to application scenes or use environments, meanwhile, the CPU cache consistency can be met, compared with the traditional server system which is limited to 24 memories of one server main board card, the scheme of the server main board card can only be increased during expansion, the cost performance is higher, and the effect is better.
Further, the first CPU and the second CPU are connected through a UPI bus. The two CPUs are respectively provided with six UPI ports, including a first UPI port, a second UPI port, a third UPI port, a fourth UPI port and a fifth UPI port; the first UPI port of the first CPU is connected with the second UPI port of the second CPU, the second UPI port of the first CPU is connected with the first UPI port of the second CPU, the third UPI port of the first CPU is connected with the third UPI port of the second CPU, the fourth UPI port of the first CPU is connected with the fourth UPI port of the second CPU, the fifth UPI port of the first CPU is connected with the fifth UPI port of the second CPU, and the sixth UPI port of the first CPU is connected with the sixth UPI port of the second CPU. The UPI bus enables communication between the two CPUs. The two UPI ports connected with each other between the first CPU and the second CPU are connected through an X24 data line.
Further, the memory rapid controller is provided with a DDR port, a first SMBUS port, an SPI port, a first JTAG debugging port, a first I3C port and a first GPIO port;
the CPU is provided with a second SMBUS port, a second JTAG debugging port, a second I3C port and a second GPIO port;
the DDR port is connected with the extended memory, the first SMBUS port is connected with the second SMBUS port, the SPI port is connected with the FLASH, the first JTAG debug port is connected with the second JTAG debug port, and the first I3C port is connected with the second I3C port and the extended memory. The CXL port of the memory rapid controller supports the data line of X8 or X16; DDR port of the memory fast controller supports DDR memory in CXL format; the first SMBUS port and the first I3C port of the memory quick controller are used for managing memory, temperature and power information; the SPI port of the memory rapid controller is used for mounting FLASH to provide additional configuration requirements, so that the requirements of different environments and applications are met; the first GPIO port of the memory quick controller is used as a reserved configuration port, and the configurable parameters meet the required application scene; the required application scenes include an AI server application scene, a GPU server application scene and a general server application scene.
In a second aspect, the present invention provides a method for implementing memory pool expansion of a high-density server, including the following steps:
s1, setting a memory expansion card in a server cabinet, and setting an expansion memory on the memory expansion card;
s2, the server main board card is inserted into the memory expansion card, so that the CPU is connected with the expansion memory through the memory rapid controller, and memory expansion is achieved.
Further, the specific steps of step S1 are as follows:
s11, setting a memory expansion card in a server cabinet;
s12, acquiring the number of CPU (Central processing Unit) in a server and the number of memory to be expanded, and setting an expanded memory and a memory quick controller on a memory expansion card according to the number of the memory to be expanded;
the specific steps of the step S2 are as follows:
s21, plugging the server main board card with the memory expansion card through a connector;
s22, each CPU is connected with the required expansion memory through a memory quick controller, so that memory expansion is realized. The memory is expanded through the memory quick controller, so that the scheme that the memory is limited after the CPU package of the original server main board is increased, and the memory can only be increased by increasing the memory is avoided.
The invention has the advantages that,
according to the system and the method for realizing the memory pool expansion of the high-density server, the memory expansion is realized through the cooperation of the CPU and the memory quick controller, and the system and the method can be used for a single CPU and a plurality of CPUs, so that the scheme that the original memory is increased only for increasing the server board card is avoided, the cost is reduced, the cache consistency among the CPUs is improved, PE port resources of the CPUs are more balanced, and the performance of the CPUs is exerted to the greatest advantage.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
It can be seen that the present invention has outstanding substantial features and significant advances over the prior art, as well as the benefits of its implementation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic diagram of a system embodiment 1 for implementing high-density server memory pool expansion according to the present invention.
FIG. 2 is a block diagram of an embodiment 2 of a system for implementing high density server memory pool expansion.
FIG. 3 is a block diagram of an embodiment 3 of a system for implementing high density server memory pool expansion.
FIG. 4 is a block diagram of an embodiment 4 of a system for implementing high density server memory pool expansion.
FIG. 5 is a block diagram of an embodiment 5 of a system for implementing high density server memory pool expansion.
FIG. 6 is a block diagram of an embodiment 6 of a system for implementing high density server memory pool expansion.
Fig. 7 is a schematic structural diagram of a method embodiment 7 of implementing the high-density server memory pool expansion according to the present invention.
Fig. 8 is a schematic structural diagram of a method embodiment 7 of implementing the high-density server memory pool expansion of the present invention.
In the figure, a 1-server motherboard card; 2-memory expansion card; 3-CPU; 3.1-a first CPU; 3.2-a second CPU; 4-an integrated memory controller; a 5-PE port; 5.1-a first PE port; 5.2-a second PE port; 6-integrating a memory; 7-a memory fast controller; 8-expanding a memory; a 9-CXL port; a 10-DDR port; 11.1-a first SMBUS port; 11.2-a second SMBUS port; 12-SPI port; 13.1-a first JTAG debug port; 13.2-a second JTAG debug port; 14.1-a first I3C port; 14.2-a second I3C port; 15.1-a first GPIO port; 15.2-a second GPIO port; 16-FLASH; a-a first control unit; b-a second control unit; UPI 0-a first UPI port; UPI 1-a second UPI port; UPI 2-third UPI port; UPI 3-fourth UPI port; UPI 4-fifth UPI port; UPI 5-sixth UPI port.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
CXL is the abbreviation of Computer express Link, computer quick connect.
The PE port is short for PPPOE port. PPPoE, which is a Point-to-Point Protocol Over Ethernet protocol for short, is a network tunneling protocol that encapsulates a Point-to-Point protocol (PPP for short) in an Ethernet frame.
JTAG is a short for Joint Test Action Group, joint test workgroup.
DDR, a short term Double Data Rate SDRAM, double Rate synchronous dynamic random Access memory.
Example 1:
as shown in fig. 1, the present invention provides a system for implementing expansion of a high-density server memory pool, which comprises a server motherboard 1 and a memory expansion card 2;
the server main board card 1 is provided with a CPU3, the CPU3 is provided with an integrated memory controller 4 and a PE port 5, and the integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory quick controller 7, and the memory quick controller 7 is connected with an expansion memory 8;
the memory fast controller 7 is connected with the PE port 5 of the CPU3.
The system for realizing the memory pool expansion of the high-density server provided by the invention realizes the memory expansion by matching the CPU with the memory quick controller, can be used for a single CPU and a plurality of CPUs, avoids the scheme that the original memory is increased only by adding a server board card, reduces the cost, is beneficial to increasing the cache consistency among the CPUs, ensures more balanced PE port resources of the CPUs and exerts the performance of the CPU with the greatest advantage.
Example 2:
as shown in fig. 1 and 2, the present invention provides a system for implementing expansion of a memory pool of a high-density server, which comprises a server motherboard 1 and a memory expansion card 2;
the server main board card 1 is provided with a CPU3, the CPU3 is provided with an integrated memory controller 4 and a PE port 5, and the integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory quick controller 7, and the memory quick controller 7 is connected with an expansion memory 8;
the memory rapid controller 7 is connected with the PE port 5 of the CPU 3;
the memory rapid controller 7 is provided with a CXL port 9; the CXL port 9 is an X16 model CXL port;
the CXL port 9 is connected with the PE port 5 through an X16 data line;
the memory quick controller 7 is provided with a DDR port 10, a first SMBUS port 11.1, an SPI port 12, a first JTAG debugging port 13.1, a first I3C port 14.1 and a first GPIO port 15.1;
the CPU3 is provided with a second SMBUS port 11.2, a second JTAG debug port 13.2, a second I3C port 14.2 and a second GPIO port 15.2;
the DDR port 10 is connected with the expansion memory 8, the first SMBUS port 11.1 is connected with the second SMBUS port 11.2, the SPI port 12 is connected with the FLASH16, the first JTAG debug port 13.1 is connected with the second JTAG debug port 13.2, and the first I3C port 14.1 is connected with the second I3C port 14.2 and the expansion memory 8;
DDR port 10 of the memory fast controller supports DDR memory in CXL format; the first SMBUS port 11.1 and the first I3C port 14.1 of the memory fast controller 7 are used to manage memory, temperature and power information; the SPI port 12 of the memory quick controller 7 is used for mounting the FLASH16 to provide additional configuration requirements, so that the requirements of different environments and applications are met; the first GPIO port 15.1 of the memory quick controller 7 is used as a reserved configuration port, and the configurable parameters meet the required application scene; the required application scenes include an AI server application scene, a GPU server application scene and a general server application scene.
Example 3:
as shown in fig. 3, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard 1 and a memory expansion card 2;
the server main board card 1 is provided with a CPU3, the CPU3 is provided with an integrated memory controller 4 and a PE port 5, and the integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory quick controller 7, and the memory quick controller 7 is connected with an expansion memory 8;
the memory rapid controller 7 is connected with the PE port 5 of the CPU 3;
the memory rapid controller 7 is provided with a CXL port 9; the CXL port 9 is an X16 model CXL port;
the number of PE ports 5 of the CPU3 is at least two, including a first PE port 5.1 and a second PE port 5.2;
the first PE port 5.1 and the second PE port 5.2 are respectively connected with the CXL port 9 through an X8 data line;
the memory quick controller 7 is provided with a DDR port 10, a first SMBUS port 11.1, an SPI port 12, a first JTAG debugging port 13.1, a first I3C port 14.1 and a first GPIO port 15.1;
the CPU3 is provided with a second SMBUS port 11.2, a second JTAG debug port 13.2, a second I3C port 14.2 and a second GPIO port 15.2;
the DDR port 10 is connected with the expansion memory 8, the first SMBUS port 11.1 is connected with the second SMBUS port 11.2, the SPI port 12 is connected with the FLASH16, the first JTAG debug port 13.1 is connected with the second JTAG debug port 13.2, and the first I3C port 14.1 is connected with the second I3C port 14.2 and the expansion memory 8;
DDR port 10 of the memory fast controller supports DDR memory in CXL format; the first SMBUS port 11.1 and the first I3C port 14.1 of the memory fast controller 7 are used to manage memory, temperature and power information; the SPI port 12 of the memory quick controller 7 is used for mounting the FLASH16 to provide additional configuration requirements, so that the requirements of different environments and applications are met; the first GPIO port 15.1 of the memory quick controller 7 is used as a reserved configuration port, and the configurable parameters meet the required application scene; the required application scenes include an AI server application scene, a GPU server application scene and a general server application scene.
Example 4:
as shown in fig. 4, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard 1 and a memory expansion card 2;
the server main board card 1 is provided with a first CPU 3.1 and a second CPU3.2, the first CPU 3.1 and the second CPU3.2 are respectively provided with an integrated memory controller 4 and PE ports 5, and the number of the PE ports 5 on each CPU3 is two; each integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory quick controller 7, and the memory quick controller 7 is connected with an expansion memory 8;
the memory rapid controller 7 is provided with a CXL port 9; the CXL port 9 is an X16 model CXL port;
the PE port 5 of the first CPU 3.1 and the PE port 5 of the second CPU3.2 are respectively connected with the CXL port 9 through an X8 data line;
the CXL port 9 can be simultaneously connected with the two PE ports 5 of the CPU3, namely X16 signals of the CXL port 9 are simultaneously connected with the two PE ports 5 through two X8 data lines, so that when a server main board system is designed, the average resource is achieved, the power and the PE ports 5 are uniformly distributed, and the layout and the wiring of the server main board are facilitated; and when DDR data is transmitted, the transmission delay is better than the situation that one CXL port 9 is connected with a single PE port 5 through an X16 data line.
Example 5:
as shown in fig. 5, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard 1 and a memory expansion card 2;
the server main board card 1 is provided with a first CPU 3.1 and a second CPU3.2, the first CPU 3.1 and the second CPU3.2 are respectively provided with an integrated memory controller 4 and PE ports 5, and the number of the PE ports 5 on each CPU is six; the number of the integrated memory controllers 4 on each CPU is six, each integrated memory controller 4 comprises a first control unit A and a second control unit B, and each control unit B is connected with one integrated memory 6;
the number of the memory quick controllers 7 arranged on the memory expansion card 2 is twelve, and each memory quick controller 7 is connected with an expansion memory 8;
each memory quick controller 7 is provided with a CXL port 9;
the CXL port 9 is an X16 model CXL port;
each PE port 5 of the first CPU 3.1 is connected with the CXL port 9 of the corresponding memory fast controller 7 through an X16 data line, and each PE port 5 of the second CPU3.2 is connected with the CXL port 9 of the corresponding memory fast controller 7 through an X16 data line; the PE ports 5 are connected with the memory rapid controller 7 in one-to-one correspondence through X16 data lines;
six UPI ports are arranged on the first CPU 3.1 and the second CPU3.2, and the six UPI ports comprise a first UPI port UPI0, a second UPI port UPI1, a third UPI port UPI2, a fourth UPI port UPI3, a fifth UPI port UPI4 and a sixth UPI port UPI5; the first UPI port UPI0 of the first CPU 3.1 is connected with the second UPI port UPI1 of the second CPU3.2, the second UPI port UPI1 of the first CPU 3.1 is connected with the first UPI port UPI0 of the second CPU3.2, the third UPI port UPI2 of the first CPU 3.1 is connected with the third UPI port UPI2 of the second CPU3.2, the fourth UPI port UPI3 of the first CPU 3.1 is connected with the fourth UPI port UPI3 of the second CPU3.2, the fifth UPI port UPI4 of the first CPU 3.1 is connected with the fifth UPI port UPI4 of the second CPU3.2, and the sixth UPI port UPI5 of the first CPU 3.1 is connected with the sixth UPI port UPI5 of the second CPU 3.2; the UPI bus realizes communication between two CPUs; the two UPI ports which are mutually connected between the first CPU 3.1 and the second CPU3.2 are connected through an X24 data line;
the CXL port 9 can be simultaneously connected with two PE ports 5 arranged on different CPUs 3, namely X16 signals of the CXL port 9 are simultaneously connected with the two PE ports 5 of the different CPUs 3 through two X8 data lines, so that cache consistency of the different CPUs 3 is ensured, the transmission rate is more stable and reliable compared with the connection situation with the PE ports 5 of the same CPU3, the data delay is lower, and the resource balance of the PE ports 5 of the CPU3 is realized;
the memory control unit of the memory controller of each CPU on the original 2U 2-way server mainboard board can support 24 memories, two CPUs are 48 memories, and as the CPU functions develop, after the package size of the CPUs becomes large, the original 2U 2-way server mainboard board can not put down the original 48 memories, only 24 memories can be put down, and when 24 memories are not used, the memories are required to be increased in a mode of increasing the server mainboard board, so that the cost is greatly increased;
according to the invention, only the server main board card is required to be spliced with the memory expansion card, 2 new packaging CPUs (Central processing Unit) of the 2U 2-way server and a plurality of memory quick controllers are supported by the server main board card to expand the CXL memory pool, the quantity and the capacity of the memory which are required to be expanded can be customized and allocated according to application scenes or use environments, and compared with the prior server system which is limited to 24 memories of one server main board card, the scheme of the server main board card can only be increased during expansion, the cost performance is higher, and the effect is better; corresponding memory expansion can be performed according to the AI server application scene, the GPU server application scene and the general server application scene.
Example 6:
as shown in fig. 6, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard 1 and a memory expansion card 2;
the server main board card 1 is provided with a first CPU 3.1 and a second CPU3.2, the first CPU 3.1 and the second CPU3.2 are respectively provided with an integrated memory controller 4 and PE ports 5, and the number of the PE ports 5 on each CPU is six; the number of the integrated memory controllers 4 on each CPU is six, each integrated memory controller 4 comprises a first control unit A and a second control unit B, and each control unit B is connected with one integrated memory 6;
the number of the memory quick controllers 7 arranged on the memory expansion card 2 is twelve, and each memory quick controller 7 is connected with an expansion memory 8;
each memory quick controller 7 is provided with a CXL port 9;
the CXL port 9 is an X16 model CXL port;
the first CPU 3.1 and the second CPU3.2 each comprise a first side, a second side, a third side and a fourth side; the integrated memory controller 4 of the first CPU 3.1 is arranged on a first side of the first CPU 3.1, three PE ports 5 are arranged on a second side of the first CPU 3.1, three PE ports 5 are arranged on a fourth side of the first CPU 3.1, three PE ports are arranged on a second side of the second CPU3.2, and three PE ports 5 are arranged on a fourth side of the second CPU 3.2;
one PE port arranged on the fourth side of the first CPU 3.1 and one PE port 5 arranged on the fourth side of the second CPU3.2 form a first PE port pair, the PE ports 5 in each first PE port pair are correspondingly connected with two memory fast controllers 7, and each memory fast controller 7 is connected with the two PE ports 5 in the first PE port pair through X8 signal lines;
three PE ports arranged on the second side of the first CPU 3.1 form a first PE port queue along the direction from the first side to the third side of the first CPU 3.1, and three PE ports arranged on the second side of the second CPU3.2 form a second PE port queue along the direction from the first side to the third side of the second CPU 3.2;
the first PE port queue and the second PE port queue form a PE port queue along the direction of the first side of the first CPU 3.1 and the direction of the third side of the second CPU 3.2; adjacent PE ports 5 in the PE port queues form a second PE port pair, a PE port positioned at the head of the PE port queues and a PE port positioned at the tail of the PE port queues form a second PE port pair, and two PE ports 5 in the second PE port pair are correspondingly connected with a memory fast controller 7 through an X8 data line;
six UPI ports are arranged on the first CPU 3.1 and the second CPU3.2, and the six UPI ports comprise a first UPI port UPI0, a second UPI port UPI1, a third UPI port UPI2, a fourth UPI port UPI3 and a fifth UPI port UPI4; the first UPI port UPI0 of the first CPU 3.1 is connected with the second UPI port UPI1 of the second CPU3.2, the second UPI port UPI1 of the first CPU 3.1 is connected with the first UPI port UPI0 of the second CPU3.2, the third UPI port UPI2 of the first CPU 3.1 is connected with the third UPI port UPI2 of the second CPU3.2, the fourth UPI port UPI3 of the first CPU 3.1 is connected with the fourth UPI port UPI3 of the second CPU3.2, the fifth UPI port UPI4 of the first CPU 3.1 is connected with the fifth UPI port UPI4 of the second CPU3.2, and the sixth UPI port UPI5 of the first CPU 3.1 is connected with the sixth UPI port UPI5 of the second CPU 3.2; the two UPI ports which are mutually connected between the first CPU 3.1 and the second CPU 3.1 are connected through an X24 data line;
six UPI ports of the first CPU 3.1 are provided on the third side of the first CPU 3.1 and six UPI ports of the second CPU3.2 are provided on the first side of the second CPU 3.2.
The memory control unit of the memory controller of each CPU on the original 2U 2-way server mainboard board can support 24 memories, two CPUs are 48 memories, and as the CPU functions develop, after the package size of the CPUs becomes large, the original 2U 2-way server mainboard board can not put down the original 48 memories, only 24 memories can be put down, and when 24 memories are not used, the memories are required to be increased in a mode of increasing the server mainboard board, so that the cost is greatly increased;
according to the invention, only the server main board card is required to be spliced with the memory expansion card, 2 new packaged CPUs (Central processing Unit) of the 2U 2-way server and a plurality of memory quick controllers are supported by the server main board card to expand the CXL memory pool, the quantity and the capacity of the memory required to be expanded can be customized and allocated according to application scenes or use environments, namely, the cache consistency of the CPU can be met, compared with the traditional server system which is limited to 24 memories of one server main board card, the scheme of the server main board card can only be increased during expansion, the cost performance is higher, and the effect is better; corresponding memory expansion can be performed according to the AI server application scene, the GPU server application scene and the general server application scene.
Example 7:
as shown in fig. 7, the present invention provides a method for implementing memory pool expansion of a high-density server, which includes the following steps:
s1, setting a memory expansion card in a server cabinet, and setting an expansion memory on the memory expansion card;
s2, the server main board card is inserted into the memory expansion card, so that the CPU is connected with the expansion memory through the memory rapid controller, and memory expansion is achieved.
The method for realizing the memory pool expansion of the high-density server provided by the invention realizes the memory expansion by matching the CPU with the memory quick controller, can be used for a single CPU and a plurality of CPUs, avoids the scheme that the original memory is increased only by adding a server board card, reduces the cost, is beneficial to increasing the cache consistency among the CPUs, ensures that PE port resources of the CPUs are more balanced, and exerts the performance of the CPU with the greatest advantage.
Example 8:
as shown in fig. 8, the present invention provides a method for implementing memory pool expansion of a high-density server, which includes the following steps:
s1, setting a memory expansion card in a server cabinet, and setting an expansion memory on the memory expansion card; the method comprises the following specific steps:
s11, setting a memory expansion card in a server cabinet;
s12, acquiring the number of CPU (Central processing Unit) in a server and the number of memory to be expanded, and setting an expanded memory and a memory quick controller on a memory expansion card according to the number of the memory to be expanded;
s2, setting a server main board card and a memory expansion card for plugging, so that a CPU (Central processing Unit) is connected with an expansion memory through a memory quick controller to realize memory expansion; the method comprises the following specific steps:
s21, plugging the server main board card with the memory expansion card through a connector;
s22, each CPU is connected with the required expansion memory through a memory quick controller, so that memory expansion is realized.
The method for realizing the expansion of the high-density server memory pool can realize the plug-in connection of the PE port of the CPU and the memory quick controller through the plug-in connection of the server main board and the memory expansion board and then connect the expansion memory, thereby completing the memory expansion without increasing the number of the server main board and having low cost.
The invention provides the memory transmission rate, improves the memory consistency among the CPUs of the multipath server, realizes the PE port resource distribution balance of the CPUs, thereby exerting the performance of the CPUs to the greatest advantage.
Although the present invention has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and it is intended that all such modifications and substitutions be within the scope of the present invention/be within the scope of the present invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. The system for realizing the memory pool expansion of the high-density server is characterized by comprising a server main board card and a memory expansion card;
the server main board card is provided with a CPU, the CPU is provided with an integrated memory controller and a PE port, and the integrated memory controller is connected with an integrated memory;
the memory expansion card is provided with a memory quick controller which is connected with an expansion memory;
the memory rapid controller is connected with the PE port of the CPU;
the memory rapid controller is provided with a CXL port;
the CXL port is connected with the PE port.
2. The system for implementing high-density server memory pool expansion of claim 1, wherein the CXL port is a model X16 CXL port;
the CXL port is connected with the PE port through an X16 data line.
3. The system for implementing high-density server memory pool expansion of claim 1, wherein the CXL port is a model X16 CXL port;
the number of PE ports of the CPU is at least two;
wherein, two PE ports are connected with CXL port through an X8 data line respectively.
4. The system for implementing high-density server memory pool expansion of claim 1, wherein the CXL port is a model X16 CXL port;
the number of the CPUs is at least two;
the PE port of each CPU is connected with the CXL port through an X8 data line respectively.
5. The system for implementing high-density server memory pool expansion of claim 1, wherein the CXL port is a model X16 CXL port;
the number of the CPUs is two, and the CPU comprises a first CPU and a second CPU;
each CPU is provided with three integrated memory controllers, each integrated memory controller comprises two control units, and each control unit is connected with one integrated memory;
the number of PE ports of each CPU is six;
the number of the memory quick controllers is twelve;
each PE port is connected with one or two memory fast controllers.
6. The system for implementing high-density server memory pool expansion of claim 5, wherein the first CPU and the second CPU are coupled via a UPI bus.
7. The system for implementing memory pool expansion of a high-density server of claim 1, wherein the memory express controller is provided with a DDR port, a first SMBUS port, an SPI port, a first JTAG debug port, a first I3C port, and a first GPIO port;
the CPU is provided with a second SMBUS port, a second JTAG debugging port, a second I3C port and a second GPIO port;
the DDR port is connected with the extended memory, the first SMBUS port is connected with the second SMBUS port, the SPI port is connected with the FLASH, the first JTAG debug port is connected with the second JTAG debug port, and the first I3C port is connected with the second I3C port and the extended memory.
8. A method for implementing high-density server memory pool expansion based on any one of claims 1-7, comprising the steps of:
s1, setting a memory expansion card in a server cabinet, and setting an expansion memory on the memory expansion card;
s2, the server main board card is inserted into the memory expansion card, so that the CPU is connected with the expansion memory through the memory rapid controller, and memory expansion is achieved.
9. The method for expanding the memory pool of the high-density server according to claim 8, wherein step S1 comprises the following specific steps:
s11, setting a memory expansion card in a server cabinet;
s12, acquiring the number of CPU (Central processing Unit) in a server and the number of memory to be expanded, and setting an expanded memory and a memory quick controller on a memory expansion card according to the number of the memory to be expanded;
the specific steps of the step S2 are as follows:
s21, plugging the server main board card with the memory expansion card through a connector;
s22, each CPU is connected with the required expansion memory through a memory quick controller, so that memory expansion is realized.
CN202111080761.9A 2021-09-15 2021-09-15 System and method for realizing memory pool expansion of high-density server Active CN113835487B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111080761.9A CN113835487B (en) 2021-09-15 2021-09-15 System and method for realizing memory pool expansion of high-density server

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111080761.9A CN113835487B (en) 2021-09-15 2021-09-15 System and method for realizing memory pool expansion of high-density server

Publications (2)

Publication Number Publication Date
CN113835487A CN113835487A (en) 2021-12-24
CN113835487B true CN113835487B (en) 2023-08-08

Family

ID=78959473

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111080761.9A Active CN113835487B (en) 2021-09-15 2021-09-15 System and method for realizing memory pool expansion of high-density server

Country Status (1)

Country Link
CN (1) CN113835487B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114020655A (en) * 2022-01-05 2022-02-08 苏州浪潮智能科技有限公司 Memory expansion method, device, equipment and storage medium
CN115509307A (en) * 2022-09-01 2022-12-23 超聚变数字技术有限公司 Server and electronic equipment
CN115952126B (en) * 2023-03-14 2023-05-12 沐曦集成电路(上海)有限公司 GPU processor system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008080323A1 (en) * 2006-12-30 2008-07-10 Phoenix Microelectronics (China) Co., Ltd. Smart card for supporting high performance computation, mass storage, high speed transmission and new application
CN111258763A (en) * 2020-01-15 2020-06-09 阿里巴巴集团控股有限公司 Server system and control method and device of server system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9734118B2 (en) * 2013-10-16 2017-08-15 The Regents Of The University Of California Serial bus interface to enable high-performance and energy-efficient data logging

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008080323A1 (en) * 2006-12-30 2008-07-10 Phoenix Microelectronics (China) Co., Ltd. Smart card for supporting high performance computation, mass storage, high speed transmission and new application
CN111258763A (en) * 2020-01-15 2020-06-09 阿里巴巴集团控股有限公司 Server system and control method and device of server system

Also Published As

Publication number Publication date
CN113835487A (en) 2021-12-24

Similar Documents

Publication Publication Date Title
CN113835487B (en) System and method for realizing memory pool expansion of high-density server
US20180024957A1 (en) Techniques to enable disaggregation of physical memory resources in a compute system
US7979616B2 (en) System and method for providing a configurable command sequence for a memory interface device
TW201015338A (en) Enhancing bus efficiency in a memory system
CN105531766A (en) Load reduced memory module
US8559190B2 (en) Memory systems and method for coupling memory chips
TW200527211A (en) Method and apparatus for shared I/O in a load/store fabric
CN101557379B (en) Link reconfiguration method for PCIE interface and device thereof
CN108090014A (en) The storage IO casees system and its design method of a kind of compatible NVMe
CN115686153B (en) Memory module and electronic equipment
CN209044589U (en) A kind of three slot position PCIE expanding units
CN209248436U (en) A kind of expansion board clamping and server
CN109669901A (en) A kind of server
CN210776403U (en) Server architecture compatible with GPUDirect storage mode
CN107168911A (en) A kind of PCIE extended methods and expansion equipment for processor
US20220342835A1 (en) Method and apparatus for disaggregation of computing resources
CN213276462U (en) Two-way server mainboard and two-way server
CN209248518U (en) A kind of solid state hard disk expansion board clamping and server
WO2022177573A1 (en) Dual-port memory module design for composable computing
CN113722110B (en) Computer system, memory access method and device
CN111159078B (en) Electronic equipment
CN216596943U (en) Large-capacity storage board card and storage device
CN217085673U (en) Data computing system and server with built-in data computing system
EP4312104A1 (en) Memory module adapter card with multiplexer circuitry
CN209928343U (en) Mainboard and server

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant