CN101557379B - Link reconfiguration method for PCIE interface and device thereof - Google Patents
Link reconfiguration method for PCIE interface and device thereof Download PDFInfo
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- CN101557379B CN101557379B CN2009101393952A CN200910139395A CN101557379B CN 101557379 B CN101557379 B CN 101557379B CN 2009101393952 A CN2009101393952 A CN 2009101393952A CN 200910139395 A CN200910139395 A CN 200910139395A CN 101557379 B CN101557379 B CN 101557379B
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Abstract
The embodiment of the invention provides a link reconfiguration method for a PCIE interface and a device thereof. The link reconfiguration method comprises the following steps: when the orientation ofthe PCIE interface link of a root complex is initialized again, if an endpoint device connected with the root complex by the PCIE interface in a physical manner exists and the electrical function of the link between the endpoint device and the root complex is in good condition, a channel number is allotted to an available channel of the link connected with the endpoint device; and data transmission is conducted between the available channel with the channel number and the endpoint device. With the method and device, the self-adaptive reconfiguration of the PCIE interface link is utilized to the full extent and the provisions of a protocol are reasonably utilized to improve the utilization ratio of the link, thereby ensuring the stability and continuity of the data transmission of a systemby the PCIE interface and avoiding the dead halt of the whole system.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of link recombination method and device of PCIE interface.
Background technology
PCIE (PCI-Express; Quick PCI (Peripheral Component Interconnect, peripheral component interconnect)) be a kind of high performance I/O bus, it is the bus that can be applied to all peripheral I/O apparatus interconnections such as mobile device, desktop computer, work station, server, embedded calculating and communications platform.The most significant advantage of PCIE bus is to have improved the device transmission bandwidth, the speed that transmits and receive data of current PC IE1.0 is 2.5Gbit/s, simultaneously the pin of every PCIE equipment seldom, thereby reduced the design cost of PCIE chip and integrated circuit board, and reduced the complexity of integrated circuit board design.
PCIE link (PCIE lane) is two physical connections between the equipment, the PCIE interconnection has the point-to-point link of X1, X2, X4, X8, X16 or an X32, passage on the both direction by signal to forming, for example, article one, the link of X1 has a passage, be that the pair of differential signal is arranged on each direction, totally four signals; Article one, the link of X32 has 32 passages, and 32 pairs of differential waves are promptly arranged on each direction, totally 128 signals, and the PCIE link is supported the passage of similar number on each direction.Because PCIE equipment is the interconnection mechanism that adopts point-to-point, so the integrity of PCIE physical link is most important, at present, after having a link channel to damage in the PCIE link, even if other link channel are intact, whole PCIE link also can't use, and this has caused great constant to system design, and has also improved cost.
In order to address this problem, following two kinds of solutions have been proposed in the prior art.
Wherein a kind of is after certain data transmission channel of PCIE interface damages, realize the transmission of data by descending chain road (lane), promptly, if a PCIE interface is the X16 link, when passage lane8 has a damage in passage lane15, then directly drop to the X8 link, if passage lane7 damages from the X16 link, then directly drop to the X4 link, drop to passage lane0 by that analogy always.The inventor finds in realizing process of the present invention, in this solution, the data path of passage lane0 is the most important, if damaging appears in passage lane0, even remaining 15 passage (lane) all stands intact, whole PCIE interface also can't use, and makes that like this flexibility of system and cost are all poor, brings very big inconvenience to the user.
Another solution is to reduce the importance of passage lane0, promptly, after the passage lane0 of PCIE interface damages, then by whole PCIE link is done training one time, carry out the transposition reorganization, be about to passage lane15 and become passage lane0, high-order step-down position, even passage lane0 damages like this, this PCIE interface still can use.
The inventor finds in realizing process of the present invention, in this solution, though the damage of passage lane0 can not cause scrapping of whole PCIE physical interface, if but passage lane0 and passage lane15 are simultaneously impaired, even other passage (lane) is still excellent, this PCIE interface still can't use, and causes the utilance of PCIE interface link low.
Summary of the invention
In order to solve problem pointed in the above-mentioned prior art, the embodiment of the invention provides a kind of link recombination method and device of PCIE interface, to improve the utilance of PCIE interface link.
The above-mentioned purpose of the embodiment of the invention is achieved by the following technical solution:
A kind of link recombination method of PCIE interface, described method is applied to root complex, described method comprises: when the PCIE of root complex interface link reinitializes orientation, if there is the endpoint device of carrying out physical connection by described PCIE interface, and and the electric function of the link between the described endpoint device is intact, then is that the available channel that is connected to the link of described endpoint device is distributed channel number; The available channel and the described endpoint device of distributing channel number are carried out transfer of data; Wherein, described is that the available channel that is connected to the PCIE interface link of described endpoint device is distributed channel number, comprising: the available channel of the PCIE interface that affirmation is connected with described endpoint device, the available channel on the described PCIE interface is carried out channel number; According to the bandwidth confirm of the PCIE interface link of the bandwidth of described PCIE interface link and described endpoint device and the total link width between the described endpoint device; According to described total link width, the link width of every available channel between affirmation and the described endpoint device.
A kind of link reconstruction unit of PCIE interface, described device comprises: dispensing unit, be used for when the PCIE of root complex interface link reinitializes orientation, if there is the endpoint device of carrying out physical connection by described PCIE interface, and and the electric function of the link between the described endpoint device is when intact, for the available channel of the link that is connected to described endpoint device is distributed channel number; Processing unit is used to utilize the available channel and the described endpoint device of distributing channel number to carry out transfer of data; Wherein, described dispensing unit comprises: first confirms module, is used to confirm the available channel of the PCIE interface that is connected with described endpoint device; Distribution module is used for after the described first affirmation module has been confirmed the available channel of PCIE interface the available channel of described PCIE interface being carried out channel number; Second confirms module, is used for the bandwidth according to the PCIE interface link of the bandwidth of described PCIE interface link and described endpoint device, confirm and described endpoint device between the total link width; The 3rd confirms module 514, is used for according to described total link width the link width of every available channel between affirmation and the described endpoint device.
Method and apparatus by the embodiment of the invention, after in the PCIE link, having a link channel to damage, reinitialize redirected by the distribution of the link channel that does not have to damage being carried out channel number, use the self adaptation reorganization of PCIE interface link to greatest extent, reasonable use the regulation of agreement, make the utilance of link improve, the system that guaranteed has reduced the probability that entire system crashes by PCIE interface transmission data stability, non-disruptive.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, does not constitute limitation of the invention.In the accompanying drawings:
Fig. 1 is the method flow diagram of the embodiment of the invention;
Fig. 2 is the method flow diagram of another embodiment of the present invention;
Fig. 3 is the directed schematic diagram of link initialization first embodiment illustrated in fig. 2;
Fig. 4 is a link assignment flow chart embodiment illustrated in fig. 2;
Fig. 5 is the device composition frame chart of the embodiment of the invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention is clearer,, the embodiment of the invention is described in further details below in conjunction with embodiment and accompanying drawing.At this, illustrative examples of the present invention and explanation thereof are used to explain the present invention, but not as a limitation of the invention.
Embodiment one
The embodiment of the invention provides a kind of link recombination method of quick peripheral component interconnect PCIE interface, below in conjunction with accompanying drawing present embodiment is elaborated.
Fig. 1 is the method flow diagram of present embodiment, the link recombination method of the PCIE interface of present embodiment is applied to use any apparatus of PCIE interface, wherein, the PCIE interface equipment of using the method for the embodiment of the invention is called root complex as main equipment, the slave unit that is connected with this main equipment is called endpoint device, as shown in Figure 1, the method for present embodiment mainly comprises:
101: when the PCIE interface link reinitializes orientation, if root complex finds to exist the endpoint device by described PCIE interface and its physical connection, and and the electric function of the link between the described endpoint device is intact, then is that the available channel that is connected to the link of described endpoint device is distributed channel number;
102: available channel and described endpoint device that channel number is distributed in the root complex utilization are carried out transfer of data.
In the present embodiment, if occurred the damage of link channel lane in the PCIE interface between root complex and the endpoint device, then can carry out one time the link initialization orientation again, carrying out the reinitializing in the orientation process of PCIE interface link, root complex not only will be by testing the endpoint device whether this root complex exists far-end to connect, whether the electric function of testing the link between this root complex and the endpoint device by poll is intact, also to redistribute channel number for available link channel on this PCIE interface, and then carry out the transmission of data according to link and endpoint device after the reorganization, reach the purpose of the utilance of raising PCIE interface link.
Wherein, the process of detection and poll all belongs to prior art, does not repeat them here.
In addition, the setting and the management of some states have also been comprised according to the link after the reorganization and the endpoint device transmission of carrying out data, for example recover (carrying out the phase compensation of channel-to-channel), L0 (sends and receives processing layer packet TLP (Transaction Layer Packet), data link layer packets DLLP (Data Link Layer Packet)), L0S be (low-power consumption, the mobile electric power controlled state), L1 (power management states), L2 (power management states), HOT resets, winding (test and Fault Isolation) and forbidding (link that forbidding has disposed) etc., this also is the content that PCIE agreement itself is had, and does not repeat them here.
Method by the embodiment of the invention, use the self adaptation reorganization of PCIE interface link to greatest extent, reasonable use the regulation of agreement, make the utilance of link improve, the system that guaranteed has avoided the entire system deadlock by PCIE interface transmission data stability, non-disruptive.
Embodiment two
The embodiment of the invention also provides a kind of link recombination method of PCIE interface, below in conjunction with accompanying drawing present embodiment is elaborated.
Fig. 2 is the method flow diagram of present embodiment, and the method for present embodiment is applied to use any apparatus of PCIE interface, in the present embodiment, with the PCIE interface is that the X16 link is that example is illustrated, and that is to say that this X16 link has 16 link channel, as shown in Figure 2, the method for present embodiment comprises:
201:, then described PCIE interface link is reinitialized orientation if occurred the link channel damage in the PCIE interface link;
Wherein, the link initialization orientation is the physical layer control of configuration and initialization apparatus physical layer, port and relevant link, makes link can transmit normal data packet flow.
Generally speaking, the PCIE interface is when work, advanced line link initialization orientation, by the link initialization orientation, for every link channel of PCIE interface is distributed a link No. and channel number, as shown in Figure 3, the channel number of this PCIE interface is respectively lane0 from left to right to lane15, and link No. is corresponding with channel number.And when the transfer of data interruption, when alarm prompt etc. perhaps occurring makeing mistakes, then be judged as the PCIE interface link and the passage damage occurred, in this case, the link initialization orientation is carried out in the capital again, to confirm this PCIE interface link whether the passage damage has taken place really.After reinitializing orientation and reaching pre-determined number, if still can not resume data transmission, or the alarm prompt that still occurs makeing mistakes etc. and can not carry out transfer of data, then be judged as this PCIE interface and damage.
202: when the PCIE interface link reinitializes orientation, whether exist by the interconnective endpoint device of described PCIE interface by detecting to test, and by poll test and described endpoint device between the electric function of link whether intact, carry out the endpoint device of physical connection and with the electric function of endpoint device when intact, then execution in step 203 when existing by described PCIE interface;
Wherein, electric function has comprised electric current, differential voltage and phase-locked loop hardware capabilitys such as (time clock feature are provided), does not repeat them here.
203: for the available channel of the link that is connected to described endpoint device is distributed channel number;
Wherein, distribute channel number for the available channel of the link that is connected to described endpoint device and can finish by step shown in Figure 4, as shown in Figure 4, this process comprises:
401: the available channel of the PCIE interface that affirmation is connected with described endpoint device, then the available channel on the described PCIE interface is carried out channel number;
In one embodiment, can be by send training sequence TS1 ordered set, the available channel of the PCIE interface that affirmation is connected with described endpoint device to endpoint device.
By sending TS1 ordered set, not have the link channel of damage to receive TS1 ordered set after, send a feedback message, so just can confirm the available channel of the PCIE interface that is connected with described endpoint device.Need to prove that in one embodiment, TS1 can be as described in the definition in the PCIE standard, TS1 also can be predefined orderly sequence of data packet in another embodiment.
Need to prove, in one embodiment, can carry out link number again, in another embodiment also can be not the link at passage place not be carried out link number, promptly use original link No. the link at passage place.
402:, determine the total link width between this root complex and the described endpoint device according to the bandwidth of the PCIE interface of the bandwidth of the PCIE interface of this root complex and described endpoint device;
Because the bandwidth of root complex and endpoint device may be inconsistent, therefore, in this step, also will further confirm the total link width of this root complex and endpoint device.
Here need to prove, the bandwidth of the bandwidth of the PCIE interface of root complex and the PCIE interface of connected endpoint device might be different, at this time just need to determine the bandwidth of less PCIE interface, as the total link width between root complex and the connected endpoint device.
For example, in one embodiment, the PCIE interface bandwidth of root complex is 2G, and the PCIE interface bandwidth of connected endpoint device is 1.6G, determines that then 1.6G is as the total link width between root complex and the coupled endpoint device.
In another embodiment, the PCIE interface bandwidth that root is united topic is 1G, and the PCIE interface bandwidth of a connected endpoint device is 1.5G, determines that then 1G is as the total link width between this root complex and this endpoint device; If the PCIE interface bandwidth of another endpoint device that is connected with root complex is 0.8G, determine that then 0.8G is as the total link width between root complex and this another endpoint device.
403:, confirm the link width of every available channel between this root complex and the described endpoint device according to the total link width between root complex and the connected endpoint device.
In one embodiment, according to the total link bandwidth between root complex and the connected endpoint device, can confirm the link width of every available channel between this root complex and the described endpoint device by send training sequence TS2 ordered set to endpoint device.
By sending TS2 ordered set, after every available channel receives TS2 ordered set, send a feedback message, feedback message can comprise the data type of this channel transfer in one embodiment, also can comprise information such as the type of service of this link or data volume in another embodiment, like this according to feedback message just and total link width just can determine the link width of every available channel.
For example, in one embodiment, suppose to have two available channel, one is mainly used to transmit image data, and one is mainly used to transmitting video data, and total link width is 2G.Can learn the main type or the content of the data of every link transmission so according to feedback message, difference according to the content of the data of every available channel transmission, determine the link width of every available channel, so just can give a little less link width of channel allocation of main transmit image data, such as being 0.5G, give the more link width of channel allocation of main transmitting video data, such as 1.5G.
Need to prove that in one embodiment, TS1 can be as described in the definition in the PCIE standard, TS1 also can be predefined orderly sequence of data packet in another embodiment.
Because the bandwidth of root complex and endpoint device may be inconsistent, some link of adding the PCIE interface damages, therefore, in this step, also to further confirm the link width of every available channel between this root complex and the endpoint device by send training sequence TS2 ordered set to endpoint device.
Process shown in Figure 4 is the link of PCIE interface link after the damaging process of training again, and by redefining arrangement channel number, the link that will not damage use once more, improve the utilance of PCIE interface link to greatest extent.
204: utilize the available channel and the described endpoint device of distributing channel number to carry out transfer of data.
In the present embodiment, according to step 201, when the PCIE interface exists link to damage, for example lane0 or lane15 damage, then carry out the link initialization orientation again, in the link initialization orientation process that this carries out again, when testing process and polling procedure by step 202 confirm to exist the endpoint device of carrying out physical connection by described PCIE interface, and with the electric function of described endpoint device when intact, also to carry out redistributing of channel number by available passage on step 203 pair this PCIE interface, the passage that allows all the other not have to damage once reorders, for example, original passage lane1 is become passage lane0, and the rest may be inferred, like this, even if because some passage has damaged in the PCIE interface physical link, as long as it is intact wherein also having passage, so just can continual transfer of data be finished, can't cause the deadlock of system.
Method by the embodiment of the invention, use the self adaptation reorganization of PCIE interface link to greatest extent, reasonable use the regulation of agreement, make the utilance of link improve, the system that guaranteed has reduced the probability that entire system crashes by PCIE interface transmission data stability, non-disruptive.
Embodiment three
The embodiment of the invention also provides a kind of link reconstruction unit of PCIE interface, below in conjunction with accompanying drawing present embodiment is elaborated.
Fig. 5 is the device composition frame chart of present embodiment, and the device of present embodiment can be applied to the equipment of any use PCIE interface, and as shown in Figure 4, the link reconstruction unit of the PCIE interface of present embodiment mainly comprises:
Dispensing unit 51, be used for when the PCIE interface link reinitializes orientation, if there is the endpoint device of carrying out physical connection by described PCIE interface, and and the electric function of the link between the described endpoint device is when intact, for the available channel of the link that is connected to described endpoint device is distributed channel number;
Processing unit 52 is used to utilize the available channel and the described endpoint device of distributing channel number to carry out transfer of data.
In the present embodiment, dispensing unit 51 can comprise: first confirms module 511, distribution module 512, the second affirmation module, 513, the three affirmation modules 514, wherein,
First confirms module 511, is used to confirm the available channel of the PCIE interface that is connected with described endpoint device, for example by send the available channel of the PCIE interface that the affirmation of TS1 ordered set is connected with described endpoint device to endpoint device.
Need to prove, in one embodiment, distribution module 512 can also be carried out link number again to the link at passage place, and distribution module 512 can be not be carried out link number to the link at passage place yet in another embodiment, promptly uses original link No..
Second confirms module 513, is used for the bandwidth according to the PCIE interface of the bandwidth of described PCIE interface and described endpoint device, confirm and described endpoint device between the total link width.
The 3rd confirms module 514, according to the total link width between root complex and the connected endpoint device, confirms the link width of every available channel between this root complex and the described endpoint device
For example, the 3rd confirm module 514 can by send to endpoint device that TS2 ordered set is confirmed and described endpoint device between the link width of every available channel.
In the present embodiment, this device can further include:
Detecting unit 54, be used for carry out the PCIE interface link reinitialize orientation the time, whether test exists the endpoint device of carrying out physical connection by described PCIE interface.
Each part of the device of present embodiment is respectively applied for each step of the method that realizes previous embodiment, each step is had been described in detail in method embodiment, does not repeat them here.
Device by the embodiment of the invention, carrying out link when the PCIE interface link damages dynamically recombinates, the availability and the reliability of PCIE interface link have been improved, use the self adaptation reorganization of PCIE interface link to greatest extent, reasonable use the regulation of agreement, make the utilance of link improve, the system that guaranteed has reduced the probability that entire system crashes by PCIE interface transmission data stability, non-disruptive.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.Software module can place the storage medium of any other form known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or the technical field.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the link recombination method of a quick peripheral component interconnect PCIE interface, described method are applied to it is characterized in that described method comprises between the root complex and endpoint device by the interconnection of PCIE interface:
When the PCIE of root complex interface link reinitializes orientation, if there is the endpoint device of carrying out physical connection by described PCIE interface, and and the electric function of the link between the described endpoint device is intact, then is that the available channel that is connected to the PCIE interface link of described endpoint device is distributed channel number;
Available channel and described endpoint device that channel number is distributed in utilization are carried out transfer of data;
Wherein, described is that the available channel that is connected to the PCIE interface link of described endpoint device is distributed channel number, comprising:
The available channel of the PCIE interface that affirmation is connected with described endpoint device is carried out channel number to the available channel on the described PCIE interface;
According to the bandwidth confirm of the PCIE interface link of the bandwidth of described PCIE interface link and described endpoint device and the total link width between the described endpoint device;
According to described total link width, the link width of every available channel between affirmation and the described endpoint device.
2. method according to claim 1 is characterized in that, the available channel of the PCIE interface that affirmation is connected with described endpoint device comprises:
Confirm the available channel of the PCIE interface that is connected with described endpoint device by sending training sequence TS1 ordered set.
3. method according to claim 1 is characterized in that, the link width between affirmation and the described endpoint device comprises:
By sending the link width between training sequence TS2 ordered set affirmation and the described endpoint device.
4. method according to claim 1 is characterized in that, describedly also comprises before the PCIE interface link reinitializes orientation:
If the passage damage occurred in the PCIE interface link of root complex, then described PCIE interface link is reinitialized orientation.
5. method according to claim 4 is characterized in that, when the PCIE interface link reinitialized orientation, described method also comprised:
By detecting to test whether have the endpoint device of carrying out physical connection by described PCIE interface.
6. method according to claim 5 is characterized in that, when the PCIE interface link reinitialized orientation, described method also comprised:
By poll test and described endpoint device between the electric function of link whether intact.
7. the link reconstruction unit of a PCIE interface is characterized in that, described device comprises:
Dispensing unit, be used for when the PCIE of root complex interface link reinitializes orientation, if there is the endpoint device of carrying out physical connection by described PCIE interface, and and the electric function of the link between the described endpoint device is when intact, for the available channel of the link that is connected to described endpoint device is distributed channel number;
Processing unit is used to utilize the available channel and the described endpoint device of distributing channel number to carry out transfer of data;
Wherein, described dispensing unit comprises:
First confirms module, is used to confirm the available channel of the PCIE interface that is connected with described endpoint device;
Distribution module is used for after the described first affirmation module has been confirmed the available channel of PCIE interface the available channel of described PCIE interface being carried out channel number;
Second confirms module, is used for the bandwidth according to the PCIE interface link of the bandwidth of described PCIE interface link and described endpoint device, confirm and described endpoint device between the total link width;
The 3rd confirms module (514), is used for according to described total link width the link width of every available channel between affirmation and the described endpoint device.
8. device according to claim 7 is characterized in that, described device also comprises:
Trigger element is used for triggering the PCIE interface link and reinitializing orientation when the passage damage has appearred in the PCIE interface link;
Detecting unit is used for when the PCIE interface link reinitializes orientation, and whether test exists the endpoint device of carrying out physical connection by described PCIE interface;
Poll units is used for when the PCIE interface link reinitializes orientation, and whether the electric function of the link between test and the described endpoint device is intact.
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| CN101930479B (en) * | 2010-08-27 | 2012-08-08 | 中国科学院上海微系统与信息技术研究所 | Peripheral-component interface express (PCIE)-based multi-channel data acquisition unit |
| US9690741B2 (en) * | 2013-07-15 | 2017-06-27 | Altera Corporation | Configuration via high speed serial link |
| CN104820649A (en) * | 2015-04-17 | 2015-08-05 | 苏州中晟宏芯信息科技有限公司 | Dynamic management method of high-speed serial heterogeneous link |
| CN104915312B (en) * | 2015-04-17 | 2017-12-29 | 苏州中晟宏芯信息科技有限公司 | A kind of channel resource recovery expanding method of high speed serialization link |
| CN107656884A (en) * | 2016-07-25 | 2018-02-02 | 中兴通讯股份有限公司 | A kind of data processing method and system, the quick interconnection equipment of peripheral assembly and main frame |
| CN111797046B (en) * | 2017-09-27 | 2022-04-08 | 成都忆芯科技有限公司 | PCIe controller and data transmission method thereof |
| CN108491039B (en) * | 2018-03-21 | 2021-01-26 | 英业达科技有限公司 | Multiplexing type hard disk backboard and server |
| CN109815043B (en) * | 2019-01-25 | 2022-04-05 | 华为云计算技术有限公司 | Fault processing method, related equipment and computer storage medium |
| CN112015683B (en) * | 2020-08-27 | 2022-06-07 | 深圳忆联信息系统有限公司 | Dynamic switching method and device of PCIE link, computer equipment and storage medium |
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| CN101102177A (en) * | 2007-08-20 | 2008-01-09 | 杭州华三通信技术有限公司 | An implementation method and device for switching master and slave controller |
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| CN101102177A (en) * | 2007-08-20 | 2008-01-09 | 杭州华三通信技术有限公司 | An implementation method and device for switching master and slave controller |
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Owner name: HUAWEI DIGITAL TECHNOLOGY (CHENGDU) CO., LTD. Free format text: FORMER NAME: CHENGDU HUAWEI SYMANTEC TECHNOLOGIES CO., LTD. |
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Address after: 611731 Chengdu high tech Zone, Sichuan, West Park, Qingshui River Patentee after: Huawei Symantec Technologies Co., Ltd. Address before: 611731 Chengdu high tech Zone, Sichuan, West Park, Qingshui River Patentee before: Chengdu Huawei Symantec Technologies Co., Ltd. |
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Granted publication date: 20111109 Termination date: 20190521 |