CN113835487A - System and method for realizing expansion of high-density server memory pool - Google Patents
System and method for realizing expansion of high-density server memory pool Download PDFInfo
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Abstract
The invention provides a system and a method for realizing the expansion of a high-density server memory pool, wherein the system comprises a server mainboard board card and a memory expansion card; the server mainboard board card is provided with a CPU, the CPU is provided with an integrated memory controller and a PE port, and the integrated memory controller is connected with an integrated memory; the memory expansion card is provided with a memory fast controller which is connected with an expansion memory; the memory fast controller is connected with the PE port of the CPU. The system and the method for realizing the expansion of the memory pool of the high-density server realize the expansion of the memory by matching the CPU with the memory fast controller, can be used for a single CPU and a plurality of CPUs, avoid the original scheme that only a server board card can be added by adding the memory, reduce the cost, be beneficial to increasing the cache consistency among the CPUs, ensure that the PE port resources of the CPUs are more balanced, and exert the performance of the CPUs with the greatest advantage.
Description
Technical Field
The invention belongs to the technical field of server memory expansion, and particularly relates to a system and a method for realizing high-density server memory pool expansion.
Background
With the rapid development of the server, the application fields of the server are more and more, and the demands on the capacity of the hard disk of the server, the capacity of the memory, the number of the GPUs and the number of cores of the CPU are more and more. With the increasing demand for CPU functions, the CPU package size is larger and larger, and at present, the CPU package size reaches 102mmx142mm, so that a normal 2U (2x44mm) 2-way server motherboard cannot meet 24(2DPC) cards from each CPU, and a 19-inch cabinet with 48 memories can be laid down, so that a normal 2U 2-way motherboard can only support 24 memories, that is, each CPU has 12 (1 DPC).
The standard size of the traditional 2U2 motherboard is 425mm in width, the size of the new CPU package plus 24(2DP) memories is 277mm, and the size of the 2-way motherboard is 277mm × 2 is 554mm, so the new CPU package plus 24(2DP) memories cannot be put down in a 19-inch standard cabinet, therefore, in the case of the latest CPU, the current scheme can only use the scheme of 1DPC, that is, 2 CPUs, and each CPU has a scheme of 24 memories in total to meet the size of the 425mm motherboard.
Compared with the prior mainboard size, the memory quantity and the capacity can not meet the mainstream requirements of most customers, and the memory needs to be expanded by adopting the scheme of additionally expanding the mainboard, so that the price is far beyond expectation.
Therefore, it is desirable to provide a system and method for expanding a high-density server memory pool in order to overcome the above-mentioned shortcomings in the prior art.
Disclosure of Invention
The invention provides a system and a method for realizing expansion of a memory pool of a high-density server, aiming at the defects that the size of an original mainboard cannot meet the requirements of the number and the capacity of memories due to the increase of the existing CPU package in the prior art, and the cost is increased due to the fact that the mainboard needs to be additionally expanded to expand the memories.
In a first aspect, the present invention provides a system for implementing expansion of a high-density server memory pool, including a server motherboard card and a memory expansion card;
the server mainboard board card is provided with a CPU, the CPU is provided with an integrated memory controller and a PE port, and the integrated memory controller is connected with an integrated memory;
the memory expansion card is provided with a memory fast controller which is connected with an expansion memory;
the memory fast controller is connected with the PE port of the CPU.
Further, the memory fast controller is provided with a CXL port;
the CXL port is connected with the PE port. And the CPU is connected with the CXL port of the memory fast controller through the PE port to expand the memory.
Further, the CXL port is an X16 model CXL port;
the CXL port and the PE port are connected by one X16 data line. The PE ports are connected with the CXL ports in a one-to-one correspondence mode and support X16 data lines.
Further, the CXL port is an X16 model CXL port;
the number of the PE ports of the CPU is at least two;
wherein, two PE ports are respectively connected with the CXL port through an X8 data line. The CXL port can be simultaneously connected with two PE ports of the same CPU, namely an X16 signal of the CXL port is simultaneously connected with the two PE ports of the same CPU through two X8 data lines, so that when a server mainboard system is designed, the resource is average, the power and the PE ports are distributed in a balanced manner, and the layout and the wiring of the server mainboard are facilitated; and in DDR data transmission, the transmission delay is superior to the situation that one CXL port and a single PE port are connected through an X16 data line.
Further, the CXL port is an X16 model CXL port;
the number of the CPUs is at least two;
the PE port of each CPU is connected to the CXL port via an X8 data line, respectively. The CXL port can be connected with two PE ports arranged on different CPUs at the same time, namely, an X16 signal of the CXL port is connected with the two PE ports of different CPUs at the same time through two X8 data lines, so that the cache consistency of different CPUs is ensured, the transmission rate is more stable and reliable compared with the connection situation of the PE ports of the same CPU, the data delay is lower, and the PE port resource balance of the CPU is realized.
Further, the CXL port is an X16 model CXL port;
the number of the CPUs is two, and the CPUs comprise a first CPU and a second CPU;
each CPU is provided with three integrated memory controllers, each integrated memory controller comprises two control units, and each control unit is connected with one integrated memory;
the number of PE ports of each CPU is six;
the number of the memory fast controllers is twelve;
each PE port is connected to one or two memory flash controllers. When each PE port is connected with one memory fast controller, one memory fast controller is correspondingly connected with one PE port at the same time, and the PE port is connected with the CXL port through an X16 data line; when each PE port is connected with two memory fast controllers, each memory fast controller is correspondingly connected with two PE ports at the same time, and the two PE ports are two PE ports of the same CPU, or the two PE ports are two PE ports of different CPUs;
the server mainboard board card supports 2 new packaged CPUs (central processing units) of 2U2 path servers and a plurality of memory rapid controllers to expand the CXL memory pool, the quantity and the capacity of the memory which needs to be expanded can be customized and distributed according to application scenes or use environments, the CPU cache consistency can be met, compared with the prior server system, the system is limited in 24 memories of one server mainboard board card, the scheme that the server mainboard board card can only be increased during expansion is adopted, the cost performance is higher, and the effect is better.
Further, the first CPU and the second CPU are connected through a UPI bus. The two CPUs are respectively provided with six UPI ports comprising a first UPI port, a second UPI port, a third UPI port, a fourth UPI port and a fifth UPI port; the first UPI port of the first CPU is connected with the second UPI port of the second CPU, the second UPI port of the first CPU is connected with the first UPI port of the second CPU, the third UPI port of the first CPU is connected with the third UPI port of the second CPU, the fourth UPI port of the first CPU is connected with the fourth UPI port of the second CPU, the fifth UPI port of the first CPU is connected with the fifth UPI port of the second CPU, and the sixth UPI port of the first CPU is connected with the sixth UPI port of the second CPU. The UPI bus enables communication between the two CPUs. The two mutually connected UPI ports of the first CPU and the second CPU are connected through an X24 data line.
Further, the memory fast controller is provided with a DDR port, a first SMBUS port, an SPI port, a first JTAG debugging port, a first I3C port and a first GPIO port;
the CPU is provided with a second SMBUS port, a second JTAG debugging port, a second I3C port and a second GPIO port;
the DDR port is connected with the expansion memory, the first SMBUS port is connected with the second SMBUS port, the SPI port is connected with the FLASH, the first JTAG debugging port is connected with the second JTAG debugging port, and the first I3C port is connected with the second I3C port and the expansion memory. The CXL port of the memory fast controller supports the data line of X8 or X16; a DDR port of the memory fast controller supports a DDR memory with a CXL format; the first SMBUS port and the first I3C port of the memory fast controller are used for managing memory, temperature and power information; the SPI port of the memory fast controller is used for mounting FLASH to provide additional configuration requirements, so that the requirements of different environments and applications are met; a first GPIO port of the memory fast controller is used as a reserved configuration port, and configurable parameters meet the requirement of a required application scene; the required application scenes comprise an AI server application scene, a GPU server application scene and a general server application scene.
In a second aspect, the present invention provides a method for implementing expansion of a memory pool of a high-density server, including the following steps:
s1, arranging a memory expansion card in a server cabinet, and arranging an expansion memory on the memory expansion card;
and S2, setting a server mainboard board card to be inserted into the memory expansion card, so that the CPU is connected with the expansion memory through the memory fast controller, and realizing memory expansion.
Further, the step S1 specifically includes the following steps:
s11, arranging a memory expansion card in a server cabinet;
s12, acquiring the quantity of CPUs (central processing units) in the server and the quantity of memories to be expanded, and setting an expansion memory and a memory fast controller on a memory expansion card according to the quantity of the memories to be expanded;
the step S2 includes the following steps:
s21, inserting the server mainboard board card and the memory expansion card through a connector;
and S22, connecting each CPU with the required expansion memory through a memory fast controller, thereby realizing memory expansion. The memory is expanded through the memory fast controller, so that the problem that the memory is limited after the original server mainboard card is encapsulated and enlarged by a CPU is solved, and the scheme that the increased memory can only increase the server mainboard card is solved.
The beneficial effect of the invention is that,
the system and the method for realizing the expansion of the memory pool of the high-density server realize the expansion of the memory by matching the CPU with the memory fast controller, can be used for a single CPU and a plurality of CPUs, avoid the original scheme that only a server board card can be added by adding the memory, reduce the cost, be beneficial to increasing the cache consistency among the CPUs, ensure that the PE port resources of the CPUs are more balanced, and exert the performance of the CPUs with the greatest advantage.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment 1 of the system for implementing expansion of a high-density server memory pool according to the present invention.
Fig. 2 is a schematic structural diagram of a system embodiment 2 for implementing high-density server memory pool expansion according to the present invention.
Fig. 3 is a schematic structural diagram of a system embodiment 3 for implementing high-density server memory pool expansion according to the present invention.
Fig. 4 is a schematic structural diagram of a system embodiment 4 for implementing expansion of a high-density server memory pool according to the present invention.
Fig. 5 is a schematic structural diagram of a system embodiment 5 for implementing expansion of a high-density server memory pool according to the present invention.
Fig. 6 is a schematic structural diagram of a system embodiment 6 for implementing high-density server memory pool expansion according to the present invention.
Fig. 7 is a schematic structural diagram of embodiment 7 of the method for implementing expansion of a high-density server memory pool according to the present invention.
Fig. 8 is a schematic structural diagram of embodiment 7 of the method for implementing expansion of a high-density server memory pool according to the present invention.
In the figure, 1-server motherboard card; 2-memory expansion card; 3-CPU; 3.1 — first CPU; 3.2-second CPU; 4-an integrated memory controller; 5-PE port; 5.1 — a first PE port; 5.2-a second PE port; 6-integrating the memory; 7-a memory fast controller; 8-expanding the memory; a 9-CXL port; a 10-DDR port; 11.1 — first SMBUS port; 11.2-a second SMBUS port; 12-SPI port; 13.1-first JTAG debug port; 13.2-second JTAG debug port; 14.1-first I3C port; 14.2-second I3C port; 15.1 — a first GPIO port; 15.2-a second GPIO port; 16-FLASH; a-a first control unit; b-a second control unit; UPI0 — first UPI port; UPI 1-second UPI port; UPI 2-third UPI port; UPI 3-fourth UPI port; UPI 4-fifth UPI port; UPI 5-sixth UPI port.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
CXL is short for Computer express Link, and is used for Computer fast connection.
The PE port is a short for PPPOE port. PPPoE is a short for Point-to-Point Protocol Over Ethernet, and a Point-to-Point Protocol Over Ethernet is a network tunneling Protocol that encapsulates a Point-to-Point Protocol (PPP) in an Ethernet frame.
JTAG is the short term Joint Test Action Group, the Joint Test work Group.
DDR is a Double Data Rate SDRAM (synchronous dynamic random access memory) for short.
Example 1:
as shown in fig. 1, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard card 1 and a memory expansion card 2;
a CPU3 is arranged on the server mainboard board card 1, the CPU3 is provided with an integrated memory controller 4 and a PE port 5, and the integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory fast controller 7, and the memory fast controller 7 is connected with an expansion memory 8;
the memory fast controller 7 is connected to the PE port 5 of the CPU3.
The system for realizing the expansion of the memory pool of the high-density server realizes the memory expansion by matching the CPU with the memory fast controller, can be used for a single CPU and a plurality of CPUs, avoids the original scheme that the memory is increased and only a server board card is added, reduces the cost, is beneficial to increasing the cache consistency among the CPUs, ensures that the PE port resources of the CPUs are more balanced, and exerts the performance of the CPUs with the greatest advantage.
Example 2:
as shown in fig. 1 and 2, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard card 1 and a memory expansion card 2;
a CPU3 is arranged on the server mainboard board card 1, the CPU3 is provided with an integrated memory controller 4 and a PE port 5, and the integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory fast controller 7, and the memory fast controller 7 is connected with an expansion memory 8;
the memory fast controller 7 is connected with the PE port 5 of the CPU 3;
the memory fast controller 7 is provided with a CXL port 9; the CXL port 9 is a CXL port of model X16;
the CXL port 9 and the PE port 5 are connected through an X16 data line;
the memory fast controller 7 is provided with a DDR port 10, a first SMBUS port 11.1, an SPI port 12, a first JTAG debugging port 13.1, a first I3C port 14.1 and a first GPIO port 15.1;
the CPU3 is provided with a second SMBUS port 11.2, a second JTAG debugging port 13.2, a second I3C port 14.2 and a second GPIO port 15.2;
the DDR port 10 is connected with the expansion memory 8, the first SMBUS port 11.1 is connected with the second SMBUS port 11.2, the SPI port 12 is connected with FLASH16, the first JTAG debugging port 13.1 is connected with the second JTAG debugging port 13.2, and the first I3C port 14.1 is connected with the second I3C port 14.2 and the expansion memory 8;
a DDR port 10 of the memory fast controller supports a DDR memory with a CXL format; the first SMBUS port 11.1 and the first I3C port 14.1 of the memory fast controller 7 are used to manage memory, temperature and power information; the SPI port 12 of the memory fast controller 7 is used for mounting the FLASH16 to provide additional configuration requirements, thereby meeting the requirements of different environments and applications; a first GPIO port 15.1 of the memory fast controller 7 is used as a reserved configuration port, and configurable parameters meet the requirement of a required application scene; the required application scenes comprise an AI server application scene, a GPU server application scene and a general server application scene.
Example 3:
as shown in fig. 3, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard card 1 and a memory expansion card 2;
a CPU3 is arranged on the server mainboard board card 1, the CPU3 is provided with an integrated memory controller 4 and a PE port 5, and the integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory fast controller 7, and the memory fast controller 7 is connected with an expansion memory 8;
the memory fast controller 7 is connected with the PE port 5 of the CPU 3;
the memory fast controller 7 is provided with a CXL port 9; the CXL port 9 is a CXL port of model X16;
the number of the PE ports 5 of the CPU3 is at least two, and the PE ports comprise a first PE port 5.1 and a second PE port 5.2;
the first PE port 5.1 and the second PE port 5.2 are connected to the CXL port 9 through an X8 data line, respectively;
the memory fast controller 7 is provided with a DDR port 10, a first SMBUS port 11.1, an SPI port 12, a first JTAG debugging port 13.1, a first I3C port 14.1 and a first GPIO port 15.1;
the CPU3 is provided with a second SMBUS port 11.2, a second JTAG debugging port 13.2, a second I3C port 14.2 and a second GPIO port 15.2;
the DDR port 10 is connected with the expansion memory 8, the first SMBUS port 11.1 is connected with the second SMBUS port 11.2, the SPI port 12 is connected with the FLASH16, the first JTAG debugging port 13.1 is connected with the second JTAG debugging port 13.2, the first I3C port 14.1 is connected with the second I3C port 14.2 and the expansion memory 8;
a DDR port 10 of the memory fast controller supports a DDR memory with a CXL format; the first SMBUS port 11.1 and the first I3C port 14.1 of the memory fast controller 7 are used to manage memory, temperature and power information; the SPI port 12 of the memory fast controller 7 is used for mounting the FLASH16 to provide additional configuration requirements, thereby meeting the requirements of different environments and applications; a first GPIO port 15.1 of the memory fast controller 7 is used as a reserved configuration port, and configurable parameters meet the requirement of a required application scene; the required application scenes comprise an AI server application scene, a GPU server application scene and a general server application scene.
Example 4:
as shown in fig. 4, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard card 1 and a memory expansion card 2;
a first CPU 3.1 and a second CPU3.2 are arranged on the server mainboard board 1, an integrated memory controller 4 and two PE ports 5 are arranged on the first CPU 3.1 and the second CPU3.2, and the number of the PE ports 5 on each CPU3 is two; each integrated memory controller 4 is connected with an integrated memory 6;
the memory expansion card 2 is provided with a memory fast controller 7, and the memory fast controller 7 is connected with an expansion memory 8;
the memory fast controller 7 is provided with a CXL port 9; the CXL port 9 is a CXL port of model X16;
the PE port 5 of the first CPU 3.1 and the PE port 5 of the second CPU3.2 are connected to the CXL port 9 through an X8 data line, respectively;
the CXL port 9 can be connected to two PE ports 5 of the CPU3 at the same time, that is, the X16 signal of the CXL port 9 is connected to two PE ports 5 at the same time through two X8 data lines, so that when the server motherboard system is designed, resource averaging is achieved, power and PE ports 5 are distributed in a balanced manner, and server motherboard layout and wiring are facilitated; and in DDR data transmission, the transmission delay is better than the case that one CXL port 9 and a single PE port 5 are connected through an X16 data line.
Example 5:
as shown in fig. 5, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard card 1 and a memory expansion card 2;
a first CPU 3.1 and a second CPU3.2 are arranged on the server mainboard board 1, an integrated memory controller 4 and PE ports 5 are arranged on the first CPU 3.1 and the second CPU3.2, and the number of the PE ports 5 on each CPU is six; the number of the integrated memory controllers 4 on each CPU is six, each integrated memory controller 4 comprises a first control unit A and a second control unit B, and each control unit B is connected with an integrated memory 6;
twelve memory fast controllers 7 are arranged on the memory expansion card 2, and each memory fast controller 7 is connected with an expansion memory 8;
each memory fast controller 7 is provided with a CXL port 9;
the CXL port 9 is a CXL port of model X16;
each PE port 5 of the first CPU 3.1 is connected to the CXL port 9 of a corresponding one of the memory flash controllers 7 through an X16 data line, and each PE port 5 of the second CPU3.2 is connected to the CXL port 9 of a corresponding one of the memory flash controllers 7 through an X16 data line; the PE ports 5 are connected with the memory fast controller 7 through X16 data lines in a one-to-one correspondence manner;
the first CPU 3.1 and the second CPU3.2 are each provided with six UPI ports, including a first UPI port UPI0, a second UPI port UPI1, a third UPI port UPI2, a fourth UPI port UPI3, a fifth UPI port UPI4 and a sixth UPI port UPI 5; a first UPI port UPI0 of the first CPU 3.1 is connected with a second UPI port UPI1 of the second CPU3.2, a second UPI port UPI1 of the first CPU 3.1 is connected with a first UPI port UPI0 of the second CPU3.2, a third UPI port UPI2 of the first CPU 3.1 is connected with a third UPI port UPI2 of the second CPU3.2, a fourth UPI port UPI3 of the first CPU 3.1 is connected with a fourth UPI port UPI3 of the second CPU3.2, a fifth UPI port UPI4 of the first CPU 3.1 is connected with a fifth UPI port UPI4 of the second CPU3.2, a sixth UPI port UPI5 of the first CPU 3.1 is connected with a sixth UPI port UPI5 of the second CPU 3.2; the UPI bus realizes the communication between the two CPUs; the two mutually connected UPI ports between the first CPU 3.1 and the second CPU3.2 are connected through an X24 data line;
the CXL port 9 can be connected with two PE ports 5 arranged on different CPUs 3 at the same time, namely, an X16 signal of the CXL port 9 is connected with the two PE ports 5 of different CPUs 3 at the same time through two X8 data lines, so that the cache consistency of different CPUs 3 is ensured, the transmission rate is more stable and reliable compared with the connection situation with the PE port 5 of the same CPU3, the data delay is lower, and the PE port 5 resource balance of the CPU3 is realized;
the memory control unit of each CPU memory controller on the original 2U2 path server mainboard board card can support 24 memories, two CPUs are just 48 memories, along with the development of CPU functions, after the packaging size of the CPUs is increased, the original 2U2 path server mainboard board card cannot put down the original 48 memories, only 24 memories can be put down, and when the 24 memories are not enough, the memories need to be increased by increasing the server mainboard board card, so that the cost is greatly increased;
the server mainboard board card supports 2U2 paths of servers and 2 newly packaged CPUs + a plurality of memory fast controllers to perform CXL memory pool expansion, the quantity and capacity of the memory to be expanded can be customized and distributed according to application scenes or use environments, compared with the scheme that an original server system is limited to 24 memories of one server mainboard board card, only the server mainboard board card can be added during expansion, cost performance is higher, and the effect is better; the corresponding memory expansion can be carried out according to an AI server application scene, a GPU server application scene and a general server application scene.
Example 6:
as shown in fig. 6, the present invention provides a system for implementing expansion of a high-density server memory pool, which includes a server motherboard card 1 and a memory expansion card 2;
a first CPU 3.1 and a second CPU3.2 are arranged on the server mainboard board 1, an integrated memory controller 4 and PE ports 5 are arranged on the first CPU 3.1 and the second CPU3.2, and the number of the PE ports 5 on each CPU is six; the number of the integrated memory controllers 4 on each CPU is six, each integrated memory controller 4 comprises a first control unit A and a second control unit B, and each control unit B is connected with an integrated memory 6;
twelve memory fast controllers 7 are arranged on the memory expansion card 2, and each memory fast controller 7 is connected with an expansion memory 8;
each memory fast controller 7 is provided with a CXL port 9;
the CXL port 9 is a CXL port of model X16;
the first CPU 3.1 and the second CPU3.2 each comprise a first side, a second side, a third side and a fourth side; the integrated memory controller 4 of the first CPU 3.1 is arranged on the first side of the first CPU 3.1, the second side of the first CPU 3.1 is provided with three PE ports 5, the fourth side of the first CPU 3.1 is provided with three PE ports 5, the second side of the second CPU3.2 is provided with three PE ports, and the fourth side of the second CPU3.2 is provided with three PE ports 5;
a PE port arranged on the fourth side of the first CPU 3.1 and a PE port 5 arranged on the fourth side of the second CPU3.2 form a first PE port pair, the PE port 5 in each first PE port pair is correspondingly connected with two memory fast controllers 7, and each memory fast controller 7 is connected with two PE ports 5 in the first PE port pair through an X8 signal line;
three PE ports disposed on the second side of the first CPU 3.1 form a first PE port queue along a direction from the first side to the third side of the first CPU 3.1, and three PE ports disposed on the second side of the second CPU3.2 form a second PE port queue along a direction from the first side to the third side of the second CPU 3.2;
the first PE port queue and the second PE port queue form a PE port queue along the direction of the first side of the first CPU 3.1 and the third side of the second CPU 3.2; adjacent PE ports 5 in the PE port queue form a second PE port pair, a PE port positioned at the head of the PE port queue and a PE port positioned at the tail of the PE port queue form a second PE port pair, and two PE ports 5 in the second PE port pair are correspondingly connected with one memory fast controller 7 through an X8 data line;
the first CPU 3.1 and the second CPU3.2 are each provided with six UPI ports including a first UPI port UPI0, a second UPI port UPI1, a third UPI port UPI2, a fourth UPI port UPI3 and a fifth UPI port UPI 4; a first UPI port UPI0 of the first CPU 3.1 is connected with a second UPI port UPI1 of the second CPU3.2, a second UPI port UPI1 of the first CPU 3.1 is connected with a first UPI port UPI0 of the second CPU3.2, a third UPI port UPI2 of the first CPU 3.1 is connected with a third UPI port UPI2 of the second CPU3.2, a fourth UPI port UPI3 of the first CPU 3.1 is connected with a fourth UPI port UPI3 of the second CPU3.2, a fifth UPI port UPI4 of the first CPU 3.1 is connected with a fifth UPI port UPI4 of the second CPU3.2, a sixth UPI port UPI5 of the first CPU 3.1 is connected with a sixth UPI port UPI5 of the second CPU 3.2; the two mutually connected UPI ports between the first CPU 3.1 and the second CPU 3.1 are connected through an X24 data line;
the six UPI ports of the first CPU 3.1 are arranged on the third side of the first CPU 3.1 and the six UPI ports of the second CPU3.2 are arranged on the first side of the second CPU 3.2.
The memory control unit of each CPU memory controller on the original 2U2 path server mainboard board card can support 24 memories, two CPUs are just 48 memories, along with the development of CPU functions, after the packaging size of the CPUs is increased, the original 2U2 path server mainboard board card cannot put down the original 48 memories, only 24 memories can be put down, and when the 24 memories are not enough, the memories need to be increased by increasing the server mainboard board card, so that the cost is greatly increased;
the server mainboard board card supports 2U2 paths of servers and 2 newly packaged CPUs + a plurality of memory fast controllers to perform CXL memory pool expansion, the quantity and the capacity of the memory to be expanded can be customized and distributed according to application scenes or use environments, the consistency of CPU cache can be met, compared with the scheme that an original server system is limited to 24 memories of one server mainboard board card, only the server mainboard board card can be increased during expansion, the cost performance is higher, and the effect is better; the corresponding memory expansion can be carried out according to an AI server application scene, a GPU server application scene and a general server application scene.
Example 7:
as shown in fig. 7, the present invention provides a method for implementing expansion of a memory pool of a high-density server, comprising the following steps:
s1, arranging a memory expansion card in a server cabinet, and arranging an expansion memory on the memory expansion card;
and S2, setting a server mainboard board card to be inserted into the memory expansion card, so that the CPU is connected with the expansion memory through the memory fast controller, and realizing memory expansion.
The method for realizing the expansion of the memory pool of the high-density server realizes the memory expansion by matching the CPU with the memory fast controller, can be used for a single CPU and a plurality of CPUs, avoids the original scheme that the memory is increased and only a server board card is added, reduces the cost, is beneficial to increasing the cache consistency among the CPUs, ensures that the PE port resources of the CPUs are more balanced, and exerts the performance of the CPUs with the greatest advantage.
Example 8:
as shown in fig. 8, the present invention provides a method for implementing expansion of a memory pool of a high-density server, comprising the following steps:
s1, arranging a memory expansion card in a server cabinet, and arranging an expansion memory on the memory expansion card; the method comprises the following specific steps:
s11, arranging a memory expansion card in a server cabinet;
s12, acquiring the quantity of CPUs (central processing units) in the server and the quantity of memories to be expanded, and setting an expansion memory and a memory fast controller on a memory expansion card according to the quantity of the memories to be expanded;
s2, setting a server mainboard board card to be inserted into a memory expansion card, so that a CPU is connected with an expansion memory through a memory fast controller to realize memory expansion; the method comprises the following specific steps:
s21, inserting the server mainboard board card and the memory expansion card through a connector;
and S22, connecting each CPU with the required expansion memory through a memory fast controller, thereby realizing memory expansion.
The method for realizing the expansion of the high-density server memory pool can realize the insertion of the PE port of the CPU and the memory fast controller through the insertion of the server mainboard board card and the memory expansion card, and then connect and expand the memory, thereby finishing the memory expansion without increasing the number of the server mainboard board cards and having low cost.
The invention provides the memory transmission rate, improves the memory consistency among the CPUs of the multi-path server, realizes the PE port resource distribution balance of the CPUs, thereby exerting the performance of the CPUs with the greatest advantage.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A system for realizing the memory pool expansion of a high-density server is characterized by comprising a server mainboard board card and a memory expansion card;
the server mainboard board card is provided with a CPU, the CPU is provided with an integrated memory controller and a PE port, and the integrated memory controller is connected with an integrated memory;
the memory expansion card is provided with a memory fast controller which is connected with an expansion memory;
the memory fast controller is connected with the PE port of the CPU.
2. The system for implementing expansion of a memory pool of a high-density server as claimed in claim 1, wherein the memory fast controller is provided with a CXL port;
the CXL port is connected with the PE port.
3. The system for implementing high-density server memory pool expansion of claim 2, wherein the CXL port is a CXL port of model X16;
the CXL port and the PE port are connected by one X16 data line.
4. The system for implementing high-density server memory pool expansion of claim 2, wherein the CXL port is a CXL port of model X16;
the number of the PE ports of the CPU is at least two;
wherein, two PE ports are respectively connected with the CXL port through an X8 data line.
5. The system for implementing high-density server memory pool expansion of claim 2, wherein the CXL port is a CXL port of model X16;
the number of the CPUs is at least two;
the PE port of each CPU is connected to the CXL port via an X8 data line, respectively.
6. The system for implementing high-density server memory pool expansion of claim 2, wherein the CXL port is a CXL port of model X16;
the number of the CPUs is two, and the CPUs comprise a first CPU and a second CPU;
each CPU is provided with three integrated memory controllers, each integrated memory controller comprises two control units, and each control unit is connected with one integrated memory;
the number of PE ports of each CPU is six;
the number of the memory fast controllers is twelve;
each PE port is connected to one or two memory flash controllers.
7. The system for implementing expansion of a memory pool of a high-density server of claim 6, wherein the first CPU and the second CPU are connected via a UPI bus.
8. The system for implementing expansion of a memory pool of a high-density server according to claim 1, wherein the memory fast controller is provided with a DDR port, a first SMBUS port, an SPI port, a first JTAG debug port, a first I3C port, and a first GPIO port;
the CPU is provided with a second SMBUS port, a second JTAG debugging port, a second I3C port and a second GPIO port;
the DDR port is connected with the expansion memory, the first SMBUS port is connected with the second SMBUS port, the SPI port is connected with the FLASH, the first JTAG debugging port is connected with the second JTAG debugging port, and the first I3C port is connected with the second I3C port and the expansion memory.
9. A method for realizing the expansion of a memory pool of a high-density server is characterized by comprising the following steps:
s1, arranging a memory expansion card in a server cabinet, and arranging an expansion memory on the memory expansion card;
and S2, setting a server mainboard board card to be inserted into the memory expansion card, so that the CPU is connected with the expansion memory through the memory fast controller, and realizing memory expansion.
10. The method for implementing expansion of a memory pool of a high-density server as claimed in claim 9, wherein step S1 comprises the following steps:
s11, arranging a memory expansion card in a server cabinet;
s12, acquiring the quantity of CPUs (central processing units) in the server and the quantity of memories to be expanded, and setting an expansion memory and a memory fast controller on a memory expansion card according to the quantity of the memories to be expanded;
the step S2 includes the following steps:
s21, inserting the server mainboard board card and the memory expansion card through a connector;
and S22, connecting each CPU with the required expansion memory through a memory fast controller, thereby realizing memory expansion.
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| CN115952126A (en) * | 2023-03-14 | 2023-04-11 | 沐曦集成电路(上海)有限公司 | GPU processor system |
| WO2024045752A1 (en) * | 2022-09-01 | 2024-03-07 | 超聚变数字技术有限公司 | Server and electronic device |
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