CN113782518A - 具有使emi屏蔽件接地的导电底部填充坝的半导体装置组件及其制造方法 - Google Patents
具有使emi屏蔽件接地的导电底部填充坝的半导体装置组件及其制造方法 Download PDFInfo
- Publication number
- CN113782518A CN113782518A CN202110635277.1A CN202110635277A CN113782518A CN 113782518 A CN113782518 A CN 113782518A CN 202110635277 A CN202110635277 A CN 202110635277A CN 113782518 A CN113782518 A CN 113782518A
- Authority
- CN
- China
- Prior art keywords
- semiconductor die
- conductive
- underfill
- dam
- fillet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
本申请涉及具有使EMI屏蔽件接地的导电底部填充坝的半导体装置组件及其制造方法。提供了一种半导体装置组件。所述组件包含衬底,所述衬底包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面。所述组件进一步包含耦合到所述多个内部接触垫的半导体裸片、耦合到所述至少一个接地垫的导电底部填充坝,以及至少安置在所述半导体裸片与所述衬底之间的底部填充材料。所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角。所述组件进一步包含安置在所述半导体裸片、所述圆角和所述导电底部填充坝上方的导电EMI屏蔽件。
Description
技术领域
本公开大体上涉及半导体装置组件,且更具体地说,涉及具有使EMI屏蔽件接地的导电底部填充坝的半导体装置组件及其制造方法。
背景技术
微电子装置大体上具有裸片(即,芯片),所述裸片包含具有高密度的极小部件的集成电路系统。通常,裸片包含电耦合到集成电路系统的极小键合垫阵列。间合垫是外部电接触件,供应电压、信号等通过所述键合垫传输到集成电路系统并从集成电路进行传输。在形成裸片之后,“封装”裸片以将键合垫耦合到可较容易地耦合到各种电力供应线、信号线及接地线的较大电端子阵列。用于包封裸片的常规工艺包含将裸片上的键合垫电耦合到引线阵列、球垫或其它类型的电端子,并且包封裸片以保护其免受环境因素(例如,湿气、微粒、静电和物理冲击)的影响。
发明内容
本申请的一方面涉及一种半导体装置组件,其包括:衬底,其包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面;半导体裸片,其耦合到所述多个内部接触垫;导电底部填充坝,其耦合到所述至少一个接地垫;底部填充材料,其至少安置在所述半导体裸片与所述衬底之间,所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角;以及导电EMI屏蔽件,其安置在所述半导体裸片、所述圆角和所述导电底部填充坝上方。
本申请的另一方面涉及一种制造半导体装置组件的方法,其包括:提供衬底,所述衬底包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面;在所述衬底的所述上表面上方形成导电底部填充坝,并且所述导电底部填充坝与所述至少一个接地垫进行电接触;将半导体裸片安置在所述多个内部接触垫上方,并且所述半导体裸片与所述多个内部接触垫进行电接触;将底部填充材料至少分配在所述半导体裸片与所述衬底之间,所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角;以及在所述半导体裸片、所述圆角和所述导电底部填充坝上方形成导电EMI屏蔽件。
本申请的又一方面涉及一种半导体装置组件,其包括:衬底,其包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面;至少一个半导体裸片,其耦合到所述多个内部接触垫;导电底部填充坝,其耦合到所述至少一个接地垫;底部填充材料,其至少安置在所述至少一个半导体裸片与所述衬底之间,所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角;导电EMI屏蔽件,其安置在所述至少一个半导体裸片、所述圆角和所述导电底部填充坝上方;以及包封材料,其至少部分地包封所述导电EMI屏蔽件。
附图说明
图1是示例半导体装置组件的简化示意性横截面视图。
图2是根据本发明技术的实施例的半导体装置组件的简化示意性横截面视图。
图3是根据本发明技术的实施例的半导体装置组件的简化示意性部分平面视图。
图4-9是示出根据本发明技术的实施例的半导体装置组件的一系列制造步骤的简化示意性横截面视图。
图10是根据本发明技术的实施例的半导体装置组件的简化示意性横截面视图。
图11是示出包含根据本发明技术的实施例配置的半导体装置组件的系统的示意图。
图12是示出根据本发明技术的实施例的制作半导体装置组件的方法的流程图。
具体实施方式
下文描述半导体装置的若干实施例和相关联系统和方法的具体细节。本领域的技术人员将认识到,本文所描述的方法的合适阶段可在晶片级或在裸片级执行。因此,取决于其使用情境,术语“衬底”可指晶片级衬底或单分的裸片级衬底。此外,除非情境另有指示,否则可使用常规的半导体制造技术来形成本文中所公开的结构。例如,可使用化学气相沉积、物理气相沉积、原子层沉积、镀覆、无电镀敷、旋涂和/或其它合适的技术沉积材料。类似地,例如,可使用等离子蚀刻、湿式蚀刻、化学机械平坦化或其它合适的技术来移除材料。
一些封装半导体装置包含在包封的半导体装置上方和周围的共形导电涂层,以提供对电磁干扰(EMI)的屏蔽。提供这种EMI屏蔽件的一种方法涉及在将例如铜、铝或其合金之类的金属以倒装芯片布置安装在衬底上之后以及在已经在裸片与衬底之间的互连件周围分配了底部填充之后,在裸片上方溅镀金属(例如,以防止溅镀屏蔽件与装置到封装的互连件之间的无意电接触)。在图1中通过实例示出了这样一个组件。
如参考图1可以看出,屏蔽半导体装置组件100包含其上安装有半导体裸片102的衬底101(例如,以倒装芯片布置在衬底101上的接触件103与半导体裸片102上的对应垫之间形成多个互连件)。衬底101进一步包含封装级接触垫104,用于通过衬底101中的迹线、线、通孔和其它电连接结构(图中未示)向半导体裸片102(例如,电力、接地和I/O信号)(例如,经由焊球)提供外部连接,所述衬底将封装级接触垫104电连接到接触件103。在半导体裸片102与衬底101之间提供底部填充材料105(例如,毛细管底填充料)以向互连件和接触件103提供电绝缘。共形EMI屏蔽件106设置在半导体裸片102、半导体裸片102的阴影外部的底部填充材料105的部分(例如,圆角)和未被底部填充材料覆盖的衬底101的部分上方。为了促进使EMI屏蔽件106接地,衬底101的未覆盖部分可以包含接地垫107(例如,通过衬底的电连接结构连接到封装级接触垫104和/或接触件103中接地的一个的接地垫)。在EMI屏蔽件106上方和周围提供包封材料109(例如,模制树脂化合物等),以防止与之进行电接触并向组件提供机械强度和保护。
这种布置的一个缺点是与在半导体裸片102的竖直侧壁上方共形地溅镀EMI屏蔽件106相关联的挑战。因为溅镀通常是定向涂覆技术,所以EMI屏蔽件106将在半导体裸片102的竖直侧壁上比在具有距竖直更远的斜率的其它区中薄(例如,半导体裸片102的水平上表面、倒圆角底部填充材料105的成角表面、衬底101的未覆盖部分的水平表面等)。由于厚度上的这种差异,溅镀工艺有时可能无法对半导体裸片102的竖直侧壁提供足够的覆盖,使得可以在EMI屏蔽件106的通常竖直的区106a中形成开口,从而损害其性能。此外,因为在EMI屏蔽件106形成之前,在底部填充材料105的分配期间,可部分或完全覆盖接地垫107,因此EMI屏蔽件106与接地垫107之间的可靠电接触还可能受到损害。
为了解决这些缺点和其它缺点,本申请的各种实施例提供了半导体装置组件,其中提供了接地的底部填充坝。接地的底部填充坝可限制底部填充材料的圆角,使得覆盖半导体裸片的竖直侧壁中的至少一些且甚至全部,从而提供可以可靠地形成溅镀EMI屏蔽件的倾斜表面。接地的底部填充坝可以在分配底部填充之前进一步连接到组件的衬底上的一个或多个接地接触件,以实现EMI屏蔽件的更可靠的电连接。
图2是根据本发明技术的实施例的半导体装置组件200的简化示意性横截面视图。如参考图2可以看出,组件200包含其上安装有半导体裸片202的衬底201(例如,以倒装芯片布置在衬底201上的接触件203与半导体裸片202上的对应垫之间形成多个互连件)。衬底201可进一步包含封装级接触垫204,用于通过衬底201中的迹线、线、通孔和其它电连接结构(图中未示)向半导体裸片202(例如,电力、接地和I/O信号)(例如,经由焊球)提供外部连接,所述衬底将封装级接触垫204电连接到接触件203。在半导体裸片202与衬底201之间可提供底部填充材料205(例如,毛细管底填充料)以向互连件和接触件203提供电绝缘。
根据本公开的一个方面,组件200可进一步包含至少部分地包围半导体裸片202的一或多个底部填充坝,例如底部填充坝208。底部填充坝208可经配置(例如,通过选择距半导体裸片202的外边缘的高度和横向距离)以限制底部填充材料205的圆角,使得所述圆角(例如,基于底部填充材料205的倾斜角,所述倾斜角是由于所述底部填充材料与半导体裸片202的材料的粘附性、其粘度、其体积等形成的)覆盖半导体裸片202的竖直侧壁的至少一部分(例如,至少一半、至少三分之二、基本上所有等)。由于如此受限制的圆角提供比半导体裸片202的侧壁更水平的表面(例如,从竖直方向进一步倾斜),因此在形成圆角之后形成(例如,溅镀)的共形EMI屏蔽件206的厚度均匀性将大于图1所示的屏蔽件106。组件200可进一步包含在EMI屏蔽件206上方和周围提供包封材料209(例如,模制树脂化合物等),以防止与之进行电接触并向组件提供机械强度和保护。
根据本公开的另一方面,因为底部填充坝208是在分配底部填充材料205之前形成的,所以它可以与例如接地垫207之类的一或多个接地垫(例如,通过衬底的电连接结构连接到封装级接触垫204和/或接触件203中接地的一个的接地垫)接触形成(例如,通过电镀在合适的位置建立,单独形成并用焊料粘附),而不存在因分配底部填充材料而首先污染接地垫的风险。
图3是根据本发明技术的实施例的半导体装置组件300的简化示意性部分平面视图。如参考图3可以看出,组件300包含衬底301,其中半导体裸片302已经(例如,以倒装芯片布置)安置在所述衬底上。组件300进一步包含至少部分地包围半导体裸片302的底部填充坝308。在这方面,如图3的实施例所示,底部填充坝308通常可以是环形的,使得其连续地包围半导体裸片302。然而,在替代实施例中,底部填充坝不需要是完全连续的(例如,其可包含一或多个开口,或由多个离散和断开元件形成)。尽管在当前示例实施例中,底部填充坝308示出为连接到单个接地垫307,但在其它实施例中,可以提供半导体装置组件,其中一或多个底部填充坝连接到多个接地垫(例如,多个离散元件的底部填充坝各自接到垫,或者一或多个元件的底部填充坝各自连接到多个接地垫)。
图4-9是示出根据本发明技术的实施例的半导体装置组件的一系列制造步骤的简化示意性横截面视图。从图4开始,(例如,呈晶片级、面板级、条级或在一些实施例中,被预单分的)衬底401具有被布置成与半导体裸片的接触件对齐的一或多个的多个接触件403(下文更详细地阐述)、一或多个封装级接触件404(例如,其通过迹线、线、通孔和本领域技术人员容易理解的其它电连接结构连接到接触件403),以及一或多个接地垫407(例如,其通过衬底的电连接结构连接到封装级接触垫404和/或接触件403中的对应接地的一个的接地垫)。
转向图5,可在经配置以容纳半导体装置的多个接触件403中的每一个周围提供接地的底部填充坝508。底部填充坝508可经配置(例如,通过选择将设置在对应多个接触件403上的距半导体裸片的外边缘的高度和横向距离)以限制底部填充材料的圆角,使得所述圆角(例如,基于底部填充材料的倾斜角,所述倾斜角是由于所述底部填充材料与半导体裸片的材料的粘附性、其粘度、其体积等形成的)覆盖半导体裸片的竖直侧壁的至少一部分(例如,至少一半、至少三分之二、基本上所有等)。
接下来转向图6,可在多个接触件403中的每一个上提供例如半导体裸片602之类的一或多个半导体裸片(例如,单个裸片或裸片堆叠),并且(例如,通过对应的多个互连件,例如,焊球、铜柱、铜凸块、直接Cu-Cu冷焊等)将其电耦合到多个接触件中的每一个。现在转向图7,在每个半导体裸片602与衬底401之间分配底部填充材料705。通过配置底部填充坝508的高度和横向间距(例如,从相应半导体裸片602的外竖直表面开始),可以控制在邻近每个半导体裸片602的每侧形成的底部填充材料705的圆角的大小和形状,以提供每个半导体裸片的侧壁的至少一些(例如,至少一半、至少三分之二、基本上所有等)的覆盖,从而提供倾斜(例如,非竖直)表面,在所述表面上可以更均匀的厚度可靠地形成溅镀EMI屏蔽件。
根据本公开的一个实施例,这种溅镀EMI屏蔽件806的形成在图8中示出。如参考图8可以看出,由于底部填充材料705的圆角的配置,溅镀EMI屏蔽件806通常可以没有竖直部分。转向图9,包封材料909(例如,模塑树脂等)可提供在附接到垫404的EMI屏蔽件806、焊球或其它封装互连件上方,并且可(例如,沿切割道(dicing street)910)单分个别组件以完成工艺。
尽管在前述示例实施例中,半导体装置组件已用延伸到半导体裸片的竖直侧壁的顶部的底部填充材料的圆角示出,但在其它实施例中,组件可具有仅向上延伸到半导体裸片的竖直侧壁一部分(例如,向上小于一半、仅向上三分之二、向上90%等)的底部填充材料的圆角。根据本发明技术的实施例,图10中以简化示意性横截面视图示出了一个这样的组件1000。如参考图10可以看出,组件1000包含其上安装有半导体裸片1002的衬底1001(例如,以倒装芯片布置在衬底1001上的接触件1003与半导体裸片1002上的对应垫之间形成多个互连件)。衬底1001可进一步包含封装级接触垫1004,用于通过衬底1001中的迹线、线、通孔和其它电连接结构(图中未示)向半导体裸片1002(例如,电力、接地和I/O信号)(例如,经由焊球)提供外部连接,所述衬底将封装级接触垫1004电连接到接触件1003。在半导体裸片1002与衬底1001之间可以提供底部填充材料1005(例如,毛细管底填充料)以向互连件和接触件1003提供电绝缘。
根据本公开的一个方面,组件1000可进一步包含至少部分地包围半导体裸片1002的一或多个底部填充坝,例如底部填充坝1008。底部填充坝1008可经配置(例如,通过选择距半导体裸片1002的外边缘的高度和横向距离)以限制底部填充材料1005的圆角,使得所述圆角(例如,基于底部填充材料1005的倾斜角,所述倾斜角是由于所述底部填充材料与半导体裸片1002的材料的粘附性、其粘度、其体积等形成的)覆盖半导体裸片1002的竖直侧壁的至少一部分(例如,至少一半、至少三分之二、90%等)。由于如此受限制的圆角提供比半导体裸片1002的侧壁更水平的表面(例如,从竖直方向进一步倾斜),因此在形成圆角之后形成(例如,溅镀)的共形EMI屏蔽件1006将具有更小的竖直区1006a,使得降低此区的厚度不足的风险。组件1000可进一步包含在EMI屏蔽件1006上方和周围提供包封材料1009(例如,模制树脂化合物等),以防止与之进行电接触并向组件提供机械强度和保护。
根据本公开的又一方面,半导体装置组件还可具有在对应裸片的上表面上方延伸的底部填充圆角。取决于所使用的底部填充材料,以及用于形成EMI屏蔽件的技术和材料,此布置可能对所使用的底部填充的量不太敏感,并且可能不会因在半导体裸片的顶部的多余圆角材料上方形成EMI屏蔽件而遭受不良影响。根据本公开的一个其它方面,底部填充坝可经配置以具有足够的高度,以确保底部填充坝不被底部填充材料覆盖(例如,确保溅镀EMI屏蔽件与接地的底部填充坝之间的电连接不受损害)。
尽管在前述示例实施例中,半导体装置组件已被示出并描述为包含单个半导体装置,但在其它实施例中,组件可具有额外半导体装置。例如,图2、7、8、9和/或图10所示的单个半导体装置可以用例如半导体装置的竖直堆叠、多个半导体装置必要时作必要地替换。
根据本公开的一个方面,图2-10的组件中所示的半导体装置可以是存储器裸片,例如动态随机存取存储器(DRAM)裸片、“与非”(NAND)存储器裸片、“或非”(NOR)存储器裸片、磁性随机存取存储器(MRAM)裸片、相变存储器(PCM)裸片、铁电随机存取存储器(FeRAM)裸片、静态随机存取存储器(SRAM)裸片等。在单个组件中提供多个裸片的实施例中,半导体装置可以是同一类型的存储器裸片(例如,两个“与非”、“两个DRAM”等)或不同类型的存储器裸片(例如,一个DRAM和一个“与非”等)。根据本公开的另一方面,上文所示出和描述的组件的半导体裸片可以是逻辑裸片(例如,控制器裸片、处理器裸片等),或逻辑和存储器裸片(例如,由此控制的存储器控制器裸片和存储器裸片)的混合。
上文参考图2-10所描述的半导体装置和半导体装置组件中的任一个可并入到大量更大和/或更复杂的系统中的任一个中,所述系统的代表性实例是图11中示意性示出的系统1100。系统1100可包含半导体装置组件(例如,或离散半导体装置)1102、电源1104、驱动器1106、处理器1108和/或其它子系统或部件1110。半导体装置组件1102可包含大体上与上文参考图2-10所描述的半导体装置的特征类似的特征。所得系统1100可执行广泛多种功能中的任一种,例如存储器存储、数据处理和/或其它合适的功能。因此,代表性系统1100可包含但不限于手持式装置(例如,移动电话、平板电脑、数字阅读器和数字音频播放器)、计算机、车辆、电器和其它产品。系统1100的部件可容纳于单个单元中或分布在多个互连的单元上方(例如,通过通信网络)。系统1100的部件还可包含远程装置和多种计算机可读媒体中的任一种。
图12是示出制造半导体装置组件的方法的流程图。所述方法包含提供衬底,所述衬底包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面(框1210)。所述方法进一步包含在衬底的上表面上方形成导电底部填充坝,并且所述导电底部填充坝与至少一个接地垫进行电接触(框1220)。所述方法进一步包含将半导体裸片安置在多个内部接触垫上方,并且所述半导体裸片与多个内部接触垫进行电接触(框1230)。所述方法进一步包含将底部填充材料至少分配在半导体裸片与衬底之间,底部填充材料包含半导体裸片与底部填充坝之间的圆角(框1240)。所述方法进一步包含在半导体裸片、圆角和导电底部填充坝上方形成导电EMI屏蔽件(框1250)。所述方法进一步包含用包封材料至少部分地包封导电EMI屏蔽件(框1260)。
本文中所论述的包含存储器装置的装置可形成在例如硅、锗、锗化硅合金、砷化镓、氮化镓等半导体衬底或裸片上。在一些情况下,衬底是半导体晶片。在其它情况下,衬底可以是绝缘体上硅(SOI)衬底,例如玻璃上硅(SOG)或蓝宝石上硅(SOP),或另一衬底上的半导体材料的外延层。可以通过使用包含但不限于磷、硼或砷的各种化学物种的掺杂来控制衬底或衬底的子区的导电性。可以在衬底的初始形成或生长期间,通过离子植入或通过任何其它掺杂手段来进行掺杂。
本文中所描述的功能可以硬件、由处理器执行的软件、固件或其任何组合来实施。其它实例及实施方案在本公开及所附权利要求书的范围内。实施功能的特征也可以在物理上位于各个位置处,包含分布以使得功能的各部分在不同物理位置处实施。
如本文(包含在权利要求书中)所使用,如在项列表(例如后加例如“中的至少一个”或“中的一或多个”的短语的项列表)中所使用的“或”指示包含端点的列表,使得例如A、B或C中的至少一个的列表意指A或B或C或AB或AC或BC或ABC(即,A和B和C)。此外,如本文所使用,短语“基于”不应被理解为指代一组封闭条件。例如,在不脱离本公开的范围的情况下,描述为“基于条件A”的示例性步骤可基于条件A和条件B两者。换句话说,如本文所使用,短语“基于”应同样地解释为短语“至少部分地基于”。
如本文中所使用,术语“竖直”、“橫向”、“上部”、“下部”、“上面”以及“下面”可指半导体装置中的特征鉴于图中示出的定向的相对方向或位置。例如,“上部”或“最上部”可指比另一特征更接近页面顶部定位的特征。然而,这些术语应广泛地理解为包含具有其它定向的半导体装置,所述定向例如倒置或倾斜定向,其中顶部/底部、上方/下方、上面/下面、向上/向下,以及左侧/右侧可取决于定向而互换。
应注意,上文描述的方法描述了可能的实施方案,并且操作和步骤可以重新布置或以其它方式加以修改,并且其它实施方案是可能的。此外,可以组合来自所述方法中的两个或更多个的实施例。
从上文中将了解,本文中已出于说明的目的描述本发明的具体实施例,但可在不偏离本发明的范围的情况下进行各种修改。相反,在前述描述中,论述了众多具体细节以提供对本发明技术的实施例的透彻和启发性描述。然而,相关领域的技术人员将认识到,可以在并无具体细节中的一或多个的情况下实践本公开。在其它情况下,未示出或未详细地描述通常与存储器系统和装置相关联的众所周知的结构或操作,以避免混淆技术的其它方面。一般来说,应理解,除了本文中所公开的那些具体实施例之外的各种其它装置、系统及方法可以在本发明技术的范围内。
Claims (20)
1.一种半导体装置组件,其包括:
衬底,其包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面;
半导体裸片,其耦合到所述多个内部接触垫;
导电底部填充坝,其耦合到所述至少一个接地垫;
底部填充材料,其至少安置在所述半导体裸片与所述衬底之间,所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角;以及
导电EMI屏蔽件,其安置在所述半导体裸片、所述圆角和所述导电底部填充坝上方。
2.根据权利要求1所述的半导体装置组件,其中所述圆角至少竖直向上延伸到所述半导体裸片的外表面的一半。
3.根据权利要求1所述的半导体装置组件,其中所述圆角竖直延伸到所述半导体裸片的上表面。
4.根据权利要求1所述的半导体装置组件,其中所述导电EMI屏蔽件通过所述导电底部填充坝和所述至少一个接地垫进行电接地。
5.根据权利要求1所述的半导体装置组件,其中所述导电底部填充坝是大体上环形的并且包围所述半导体裸片的外围。
6.根据权利要求1所述的半导体装置组件,其中所述导电底部填充坝具有经配置以限制所述底部填充材料溢出所述导电底部填充坝的高度。
7.根据权利要求6所述的半导体装置组件,其中所述导电底部填充坝的所述高度进一步经配置以使得所述圆角至少部分地竖直向上延伸到所述半导体裸片的外表面。
8.根据权利要求1所述的半导体装置组件,其中所述导电EMI屏蔽件在所述半导体裸片的上表面上方以及所述圆角上方连续地延伸而没有任何开口。
9.根据权利要求1所述的半导体装置组件,其进一步包括至少部分地包封所述导电EMI屏蔽件的包封材料。
10.一种制造半导体装置组件的方法,其包括:
提供衬底,所述衬底包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面;
在所述衬底的所述上表面上方形成导电底部填充坝,并且所述导电底部填充坝与所述至少一个接地垫进行电接触;
将半导体裸片安置在所述多个内部接触垫上方,并且所述半导体裸片与所述多个内部接触垫进行电接触;
将底部填充材料至少分配在所述半导体裸片与所述衬底之间,所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角;以及
在所述半导体裸片、所述圆角和所述导电底部填充坝上方形成导电EMI屏蔽件。
11.根据权利要求10所述的方法,其中所述圆角至少竖直向上延伸到所述半导体裸片的外表面的一半。
12.根据权利要求10所述的方法,其中所述圆角竖直延伸到所述半导体裸片的上表面。
13.根据权利要求10所述的方法,其中所述导电EMI屏蔽件通过所述导电底部填充坝和所述至少一个接地垫进行电接地。
14.根据权利要求10所述的方法,其中所述导电底部填充坝是大体上环形的并且包围所述半导体裸片的外围。
15.根据权利要求10所述的方法,其中所述导电底部填充坝具有经配置以限制所述底部填充材料溢出所述导电底部填充坝的高度。
16.根据权利要求15所述的方法,其中所述导电底部填充坝的所述高度进一步经配置以使得所述圆角至少部分地竖直向上延伸到所述半导体裸片的外表面。
17.根据权利要求10所述的方法,其中所述导电EMI屏蔽件在所述半导体裸片的上表面上方以及所述圆角上方连续地延伸而没有任何开口。
18.根据权利要求10所述的方法,其进一步包括用包封材料至少部分地包封所述导电EMI屏蔽件。
19.一种半导体装置组件,其包括:
衬底,其包含具有多个内部接触垫和至少一个接地垫的上表面和具有多个外部接触垫的下表面;
至少一个半导体裸片,其耦合到所述多个内部接触垫;
导电底部填充坝,其耦合到所述至少一个接地垫;
底部填充材料,其至少安置在所述至少一个半导体裸片与所述衬底之间,所述底部填充材料包含所述半导体裸片与所述底部填充坝之间的圆角;
导电EMI屏蔽件,其安置在所述至少一个半导体裸片、所述圆角和所述导电底部填充坝上方;以及
包封材料,其至少部分地包封所述导电EMI屏蔽件。
20.根据权利要求19所述的半导体装置组件,其中所述至少一个半导体裸片包括半导体裸片的竖直堆叠。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/897,867 | 2020-06-10 | ||
US16/897,867 US11342277B2 (en) | 2020-06-10 | 2020-06-10 | Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same |
Publications (1)
Publication Number | Publication Date |
---|---|
CN113782518A true CN113782518A (zh) | 2021-12-10 |
Family
ID=78824061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110635277.1A Pending CN113782518A (zh) | 2020-06-10 | 2021-06-08 | 具有使emi屏蔽件接地的导电底部填充坝的半导体装置组件及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US11342277B2 (zh) |
CN (1) | CN113782518A (zh) |
TW (1) | TWI795793B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11342277B2 (en) | 2020-06-10 | 2022-05-24 | Micron Technology, Inc. | Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120112344A1 (en) * | 2009-07-17 | 2012-05-10 | Nec Corporation | Substrate for semiconductor package and method of manufacturing thereof |
US20180226272A1 (en) * | 2017-01-31 | 2018-08-09 | Skyworks Solutions, Inc. | Control of under-fill using under-fill deflash for a dual-sided ball grid array package |
CN108933108A (zh) * | 2017-05-25 | 2018-12-04 | 台湾积体电路制造股份有限公司 | 半导体装置封装及其制造方法 |
US20200126887A1 (en) * | 2018-10-18 | 2020-04-23 | Intel Corporation | Thin line dam on underfill material to contain thermal interface materials |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10002852A1 (de) * | 2000-01-24 | 2001-08-02 | Infineon Technologies Ag | Abschirmeinrichtung und elektrisches Bauteil mit einer Abschirmeinrichtung |
US6762509B2 (en) * | 2001-12-11 | 2004-07-13 | Celerity Research Pte. Ltd. | Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material |
US7781883B2 (en) * | 2008-08-19 | 2010-08-24 | International Business Machines Corporation | Electronic package with a thermal interposer and method of manufacturing the same |
KR20120053332A (ko) * | 2010-11-17 | 2012-05-25 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
JP5799541B2 (ja) * | 2011-03-25 | 2015-10-28 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
US8786060B2 (en) * | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US9287194B2 (en) * | 2013-03-06 | 2016-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging devices and methods for semiconductor devices |
US9564937B2 (en) * | 2013-11-05 | 2017-02-07 | Skyworks Solutions, Inc. | Devices and methods related to packaging of radio-frequency devices on ceramic substrates |
KR101787832B1 (ko) * | 2015-10-22 | 2017-10-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지 |
WO2019066997A1 (en) * | 2017-09-30 | 2019-04-04 | Intel Corporation | SHIELD AGAINST ELECTROMAGNETIC INTERFERENCE CREATED ON HIGH-PERFORMANCE ADDITIVE MANUFACTURING HOUSING |
KR102633190B1 (ko) * | 2019-05-28 | 2024-02-05 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US11342277B2 (en) | 2020-06-10 | 2022-05-24 | Micron Technology, Inc. | Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same |
-
2020
- 2020-06-10 US US16/897,867 patent/US11342277B2/en active Active
-
2021
- 2021-05-28 TW TW110119378A patent/TWI795793B/zh active
- 2021-06-08 CN CN202110635277.1A patent/CN113782518A/zh active Pending
-
2022
- 2022-04-28 US US17/732,276 patent/US11887938B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120112344A1 (en) * | 2009-07-17 | 2012-05-10 | Nec Corporation | Substrate for semiconductor package and method of manufacturing thereof |
US20180226272A1 (en) * | 2017-01-31 | 2018-08-09 | Skyworks Solutions, Inc. | Control of under-fill using under-fill deflash for a dual-sided ball grid array package |
CN108933108A (zh) * | 2017-05-25 | 2018-12-04 | 台湾积体电路制造股份有限公司 | 半导体装置封装及其制造方法 |
US20200126887A1 (en) * | 2018-10-18 | 2020-04-23 | Intel Corporation | Thin line dam on underfill material to contain thermal interface materials |
Also Published As
Publication number | Publication date |
---|---|
TWI795793B (zh) | 2023-03-11 |
US11342277B2 (en) | 2022-05-24 |
TW202213697A (zh) | 2022-04-01 |
US11887938B2 (en) | 2024-01-30 |
US20220254732A1 (en) | 2022-08-11 |
US20210391277A1 (en) | 2021-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20220013421A1 (en) | Shielded fan-out packaged semiconductor device and method of manufacturing | |
CN110690200B (zh) | 半导体封装结构 | |
US11011502B2 (en) | Semiconductor package | |
US10256215B2 (en) | Semiconductor package | |
KR101454884B1 (ko) | 적층된 집적회로 패키지 인 패키지 시스템 | |
US20070158813A1 (en) | Integrated circuit package-in-package system | |
US11908805B2 (en) | Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact | |
US10714431B2 (en) | Semiconductor packages with electromagnetic interference shielding | |
US11894329B2 (en) | Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars | |
US11764161B2 (en) | Ground connection for semiconductor device assembly | |
CN115241165A (zh) | 具有用于裸片堆叠互连的凹陷衬垫的半导体装置 | |
US11887938B2 (en) | Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same | |
CN114093855A (zh) | 用于半导体装置组合件的堆叠半导体裸片 | |
US11942430B2 (en) | Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules | |
US20240136315A1 (en) | Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars | |
US20240145422A1 (en) | Liquid-repelling coating for underfill bleed out control | |
US9281274B1 (en) | Integrated circuit through-substrate via system with a buffer layer and method of manufacture thereof | |
US20240071891A1 (en) | Semiconductor device assemblies having face-to-face subassemblies, and methods for making the same | |
CN117637729A (zh) | 具有共面互连结构的半导体装置组合件及其制造方法 | |
CN116093092A (zh) | 包含不同长度的tsv的半导体装置组合件及其制造方法 | |
CN116504747A (zh) | 信号路由结构及包含其的半导体装置组合件 | |
CN114566489A (zh) | 一种具有电磁屏蔽功能的扇出型封装结构及封装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |