CN113726338A - Analog-to-digital converter and analog-to-digital conversion method - Google Patents

Analog-to-digital converter and analog-to-digital conversion method Download PDF

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CN113726338A
CN113726338A CN202110845211.5A CN202110845211A CN113726338A CN 113726338 A CN113726338 A CN 113726338A CN 202110845211 A CN202110845211 A CN 202110845211A CN 113726338 A CN113726338 A CN 113726338A
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capacitor
sub
pole
reference voltage
analog
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CN113726338B (en
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丁瑞雪
金宏杰
刘术彬
张延博
李琳
朱樟明
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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Abstract

The invention discloses an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter comprises: the device comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end; the lower polar plates of Ca-Cg and C5-C11 can be sampled when the analog-digital converter performs analog-digital conversion, so that the influence of variable parasitic capacitance on the upper polar plate during sampling of the upper polar plate is avoided; and by combining the sampling result of the lower electrode plate of the capacitor in the first module and a high-order data weighted average algorithm, the high-order three-bit noise shaping is achieved, and simultaneously, the mismatch errors of C5-C11 are subjected to first-order shaping, so that the mismatch errors of the whole main DAC array are subjected to first-order shaping, and the circuit complexity is simplified.

Description

Analog-to-digital converter and analog-to-digital conversion method
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to an analog-to-digital converter and an analog-to-digital conversion method.
Background
Analog-to-Digital Converter (ADC) is a bridge connecting the real world and the Digital world, and plays an irreplaceable role in various fields such as detection systems and modern communications. The continuous development of biological signal detection equipment such as electroencephalogram detection, piezoelectric detection and the like promotes the further improvement of detection precision, and simultaneously stimulates the development of ADC towards low power consumption and high precision.
The successive approximation type analog-to-digital converter is simple in structure, mostly adopts digital modules and dynamic logic, can realize low power consumption, and has high requirements in high-resolution application, wherein mismatch of a capacitor array is a key factor influencing circuit precision. A Mismatch Error Shaping (MES) method is used in the successive approximation ADC to reduce the requirement on a capacitor array, however, the traditional MES method needs to sample an upper polar plate, the variable parasitic capacitance of the upper polar plate of the capacitor array can generate a large influence on the capacitance of a low bit, so that the capacitor mismatch is serious, and the MES method in the related technology can not shape the interstage gain error, thereby limiting the whole precision of the ADC from being incapable of being improved and reducing the linearity.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an analog-to-digital converter and an analog-to-digital conversion method. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides an analog-to-digital converter comprising: the device comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end; wherein the content of the first and second substances,
the auxiliary ADC module comprises a first type capacitor, a first sub-capacitor, a second comparator, a second preset logic circuit and a first node, wherein the first type capacitor comprises: C1-C4, a first pole of C1-C4 connected to the first node, a second pole connected to one of the second signal input terminal, the first reference voltage signal terminal, the second reference voltage signal terminal or the third reference voltage signal terminal; the second comparator comprises a first input end and an output end, the first pole of the first sub-capacitor is connected with the first node, the second pole of the first sub-capacitor is connected with the first input end of the second comparator, the output end of the second comparator is connected with the input end of the second preset logic circuit, the output end of the second preset logic circuit is connected with the input end of the DWA module, and the output end of the DWA module is connected with the first preset logic circuit;
the first module comprises a second type of capacitor, a third type of capacitor and a second node, wherein the second type of capacitor comprises: ca to Cg, the third type of capacitance comprises: C5-C11, Ca-Cg and C5-C11 having first poles connected to the second node and second poles connected to one of the second signal input terminal, the first reference voltage signal terminal, the second reference voltage signal terminal or the third reference voltage signal terminal;
the first comparator comprises a first input end and an output end, the first input end of the first comparator is connected with the second node, and the output end of the first comparator is connected with the first preset logic circuit.
In one embodiment of the invention, the device further comprises a first sampling switch and a second sampling switch;
in the auxiliary ADC module, the first poles of C1-C4 are connected with the first reference voltage signal end through the first sampling switch;
in the first module, Ca to Cg and C5 to C11 are connected with the first reference voltage signal end through the second sampling switch.
In one embodiment of the present invention, the device further comprises an operational amplifier, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor and a third sampling switch;
the operational amplifier comprises a first input end and a first output end, the first input end of the operational amplifier is connected to the second node, the first output end of the operational amplifier is connected with the first pole of the fourth sub-capacitor, and the second pole of the fourth sub-capacitor is grounded;
the first pole of the second sub-capacitor is connected with the first input end of the operational amplifier, and the second pole of the second sub-capacitor is connected with the output end of the operational amplifier;
the first pole of the third sub-capacitor is connected to the second node through the third sampling switch, and the second pole of the third sub-capacitor is grounded.
In one embodiment of the present invention, the device further comprises a second module, wherein the second module comprises a fourth type capacitor, a fifth type capacitor and a second node;
the fourth type of capacitor comprises: ch to Cn, the fifth type of capacitor comprises: first poles of C12-C18, Ch-Cn and C12-C18 are connected to the second node, and second poles are connected to one of the first signal input terminal, the first reference voltage signal terminal, the second reference voltage signal terminal or the third reference voltage signal terminal.
In one embodiment of the present invention, the second module further includes a fourth sampling switch, and the first poles of Ch to Cn and C12 to C18 of the second module are connected to the first reference voltage signal terminal through the fourth sampling switch.
In an embodiment of the present invention, the operational amplifier further includes a fifth sub-capacitor, a sixth sub-capacitor, a seventh sub-capacitor, and a fifth sampling switch, and the operational amplifier further includes a second input terminal and a second output terminal;
a second input end of the operational amplifier is connected to the second node, a second output end of the operational amplifier is connected with a first pole of the seventh sub-capacitor, and a second pole of the seventh sub-capacitor is grounded;
the first pole of the fifth sub-capacitor is connected with the second input end of the operational amplifier, and the second pole of the fifth sub-capacitor is connected with the second output end of the operational amplifier;
the first pole of the sixth sub-capacitor is connected to the second node through the fifth sampling switch, and the second pole of the sixth sub-capacitor is grounded.
In an embodiment of the present invention, the auxiliary ADC module further includes a sixth type of capacitor, an eighth sub-capacitor, and a fourth node, where the sixth type of capacitor includes: C19-C22, wherein a first pole of C19-C22 is connected to the fourth node, and a second pole is connected to one of the first signal input terminal, the first reference voltage signal segment, the second reference voltage signal terminal or the third reference voltage signal terminal;
the second comparator further comprises a second input end, the first pole of the eighth sub-capacitor is connected with the fourth node, and the second pole of the eighth sub-capacitor is connected with the second input end of the second comparator.
In one embodiment of the present invention, a sixth sampling switch is further included;
in the auxiliary ADC module, the first poles of C19-C22 are connected with the first reference voltage signal end through the sixth sampling switch.
In a second aspect, the present invention further provides an analog-to-digital conversion method applied to the analog-to-digital converter of the first aspect, including: a sampling stage, a first quantization stage, an integration stage and a second quantization stage; wherein the content of the first and second substances,
in a sampling stage, second poles of Ca-Cg, C1-C4 and C5-C11 are connected with the second signal input end, second poles of Ch-Cn, C19-C22 and C12-C18 are connected with the first signal input end, and a first sampling switch, a second sampling switch, a fourth sampling switch and a sixth sampling switch are all closed, so that Ca-Cg and C5-C11 in the first module sample the second signal input signal, Ch-Cn and C12-C18 in the second module sample the first input signal, and C1-C4 in the auxiliary ADC module sample the second input signal and C19-C21 sample the first input signal; the first input signal and the second input signal are both analog signals, and the voltage of the first input signal is different from that of the second input signal;
in a first quantization stage, after the sampling results of the C1-C4 on the second input signal and the sampling results of the C19-C21 on the first input signal are compared by a second comparator, the comparison results are input into the second preset logic circuit to obtain a three-bit quantization code, the three-bit quantization code is input into the DWA module, and a seven-bit thermometer code obtained by conversion is input into the first preset logic circuit, so that the first preset logic circuit sets Ca-Cg and Ch-Cn according to the seven-bit thermometer code;
in the integration stage, the third sampling switch and the fifth sampling switch are closed to obtain a first integration voltage at the first pole of the third sub-capacitor and a second integration voltage at the first pole of the sixth sub-capacitor;
in a second quantization stage, the first comparator compares the first integrated voltage with the second integrated voltage, and inputs the comparison result to the first preset logic circuit, so that the first preset logic circuit sets C5-C11 and C12-C18 to obtain a seven-bit quantization code, and the three-bit quantization code and the seven-bit quantization code are added to obtain an analog-to-digital conversion result of the input signal.
In an embodiment of the present invention, the sum of the capacitances of Ca to Cg and C5 to C11 is equal to the capacitance values of the third sub-capacitance and the fourth sub-capacitance, and the sum of the capacitances of Ch to Cn and C12 to C17 is equal to the capacitance values of the sixth sub-capacitance and the seventh sub-capacitance.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end, and because the analog-to-digital converter adopts an MASH 1-0 shaping scheme, the analog-to-digital converter can sample the second poles of Ca-Cg and C5-C11, namely the lower pole plates of Ca-Cg and C5-C11 when carrying out analog-to-digital conversion, thereby avoiding the influence of variable parasitic capacitance on the upper pole plate when carrying out upper sampling and effectively relieving the influence of the variable parasitic capacitance on the linearity.
In addition, the analog-to-digital converter also comprises a DWA module, three capacitors corresponding to high three bits in the related technology are converted into Ca-Cg 7 capacitors by combining a capacitor bottom plate sampling result in the first module and a high-bit data weighted average algorithm, so that the noise shaping of the high three bits is achieved, the MASH 1-0 shaping scheme can carry out first-order shaping on mismatch errors of a low-bit DAC (namely C5-C11), and further the mismatch errors of the whole main DAC array are shaped in a first-order manner, so that the circuit complexity is simplified.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an auxiliary ADC module according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another structure of an analog-to-digital converter according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another structure of an auxiliary ADC module according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating operation of an analog-to-digital converter according to an embodiment of the present invention;
FIG. 6 is a signal flow diagram for mismatch error shaping of a capacitor array according to an embodiment of the present invention;
fig. 7 is a simulation result diagram of the analog-to-digital conversion method according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of an auxiliary ADC module according to an embodiment of the present invention. As shown in fig. 1-2, the present invention provides an analog-to-digital converter 100, comprising: first module 10, first comparator 20, auxiliary ADC module 30, DWA module 40, first preset logic circuit 50, first signal input terminal VINA second signal input terminal VIPA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPAnd a third reference voltage signal terminal VREFN(ii) a Wherein the content of the first and second substances,
the auxiliary ADC module 30 includes a first type capacitor, a first sub-capacitor, a second comparator 301, a second preset logic circuit 302, and a first node N1, the first type capacitorComprises the following steps: C1-C4, C1-C4, a first pole connected with the first node N1, a second pole and a second signal input end VIPA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNOne of them is connected; the second comparator 301 comprises a first input end and an output end, the first pole of the first sub-capacitor is connected with the first node N1, the second pole of the first sub-capacitor is connected with the first input end of the second comparator 301, the output end of the second comparator 301 is connected with the input end of the second preset logic circuit 302, the output end of the second preset logic circuit 302 is connected with the input end of the DWA module 40, and the output end of the DWA module 40 is connected with the first preset logic circuit 50;
the first module 10 comprises a second type of capacitance, a third type of capacitance and a second node N2, the second type of capacitance comprising: ca to Cg, and the third type of capacitor includes: C5-C11, Ca-Cg and C5-C11, the first pole is connected with the second node N2, the second pole is connected with the second signal input end VIPA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNOne of them is connected;
the first comparator 20 includes a first input terminal and an output terminal, the first input terminal of the first comparator 20 is connected to the second node N2, and the output terminal is connected to the first preset logic circuit 50.
Specifically, the analog-to-digital converter 100 includes a first module 10, a first comparator 20, an auxiliary ADC module 30, a DWA module 40, a first preset logic circuit 50, and a first signal input terminal VINA second signal input terminal VIPA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPAnd a third reference voltage signal terminal VREFNWherein the second type capacitors Ca-Cg and the third type capacitors C5-C11 in the first module 10 have first poles connected to the second node N2 and second poles connected to the second signal input terminal VIPA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNIs connected, optionally, the analog-to-digital converter 100 further comprises a second sampling switchTurning off S2, Ca-Cg and C5-C11 pass through the second sampling switch S2 and the first reference voltage signal terminal VCMConnected such that Ca to Cg and C5 to C11 can supply the second signal input terminal V when the second sampling switch S2 is closedIPWhen the second sampling switch S2 is turned off, the sampling of the second input signal is finished by Ca to Cg and C5 to C11.
Further, the auxiliary ADC module 30 comprises a first type of capacitance: C1-C4, a first sub-capacitor Ccap1, a second comparator 301, a second preset logic circuit 302 and a first node N1, wherein the first poles of C1-C4 are connected with a first node N1, and the second poles of C1-C4 are connected with a second signal input end VIPA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNIs connected. Referring to fig. 2, in the auxiliary ADC module 30, the first poles of the C1-C4 pass through the first sampling switch S1 and the first reference voltage signal terminal VCMThe connection of the first sampling switch S1 can realize that C1-C4 can be used for the second signal input end VIPIs sampled.
It should be noted that in this embodiment, the first input signal and the second input signal are both analog signals, and the voltages of the two signals are different.
Optionally, with continued reference to fig. 1, the analog-to-digital converter 100 further includes an operational amplifier 60, a second sub-capacitor Ccap3, a third sub-capacitor Cint1, a fourth sub-capacitor Cint', and a third sampling switch S3;
the operational amplifier 60 includes a first input end and a first output end, the first input end of the operational amplifier 60 is connected to the second node N2, the first output end is connected to the first pole of the fourth sub-capacitor Cint ', and the second pole of the fourth sub-capacitor Cint' is grounded;
the first pole of the second sub-capacitor Ccap3 is connected to the first input terminal of the operational amplifier 60, and the second pole is connected to the output terminal of the operational amplifier 60;
the first pole of the third sub-capacitor Cint1 is connected to the second node N2 and the second pole is grounded through the third sampling switch S3.
Optionally, the first input terminal of the operational amplifier 60 is a positive input terminal, the positive input terminal is connected to the second node N2 in the first module 10, the first output terminal is connected to the first pole of the fourth sub-capacitor Cint ', and the second pole of the fourth sub-capacitor Cint' is grounded. In addition, the first pole of the second sub-capacitor Ccap3 is connected to the first input terminal of the operational amplifier 60, the second pole is connected to the output terminal of the operational amplifier 60, the first pole of the third sub-capacitor Cint1 is connected to the second node N2 through the third sampling switch S3, the second pole is grounded, and when the third sampling switch S3 is closed, the first integrated voltage at the first pole of the third sub-capacitor Cint1 can be obtained.
It should be noted that the analog-to-digital converter 100 provided by the present invention actually adopts a fully differential circuit structure, and fig. 1 only illustrates a single end as an example.
Fig. 3 is a schematic diagram of another structure of the analog-to-digital converter according to the embodiment of the present invention. Referring to fig. 3, the analog-to-digital converter 100 further includes a second module 10 ', where the second module 10' includes a fourth type capacitor, a fifth type capacitor, and a third node N3;
the fourth type of capacitor includes: Ch-Cn, the fifth type of capacitance includes: C12-C18, Ch-Cn and C12-C18 have first poles connected to a third node N3, second poles connected to a first signal input terminal VINA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNIs connected.
Optionally, the analog-to-digital converter 100 further includes a fourth sampling switch S4, and in the second module 10', the first poles of Ch-Cn and C12-C18 are connected to the first reference voltage signal terminal V via the fourth sampling switch S4CMAnd (4) connecting.
With continued reference to fig. 3, the analog-to-digital converter 100 further includes a fifth sub-capacitor Ccap4, a sixth sub-capacitor Cint2, a seventh sub-capacitor Cint 2', and a fifth sampling switch S5, and the operational amplifier 60 further includes a second input terminal and a second output terminal;
a second input end of the operational amplifier 60 is connected to the third node N3, a second output end of the operational amplifier is connected to a first pole of the seventh sub-capacitor Cint2 ', and a second pole of the seventh sub-capacitor Cint 2' is grounded;
the first pole of the fifth sub-capacitor Ccap4 is connected to the second input terminal of the operational amplifier 60, and the second pole is connected to the second output terminal of the operational amplifier 60;
the first pole of the sixth sub-capacitor Cint2 is connected to the third node N3 and the second pole is grounded through the fifth sampling switch S5.
Fig. 4 is a schematic structural diagram of an auxiliary ADC module according to an embodiment of the present invention. Optionally, as shown in fig. 4, the analog-to-digital converter 100 further includes a sixth sampling switch S6;
in the auxiliary ADC module 30, the first pole of C19-C22 is connected to the first reference voltage signal terminal V via the sixth sampling switch S6CMAnd (4) connecting.
It should be understood that for the second module 10', Ch Cn and C12C 18 are connected to the first reference voltage signal terminal V through the fourth sampling switch S4CMConnected, Ch-Cn and C12-C18 may initially be coupled to the first signal input terminal V when the fourth sampling switch S4 is closedINCh to Cn and C12 to C18 end sampling the first input signal when the second sampling switch S2 is turned off.
Specifically, the auxiliary ADC module 30 further includes a sixth type of capacitance, an eighth sub-capacitance Ccap2 and a fourth node N4, where the sixth type of capacitance includes: C19-C22, C19-C22, the first pole is connected with the fourth node N4, the second pole is connected with the first signal input end VINA first reference voltage signal terminal VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNOne of them is connected;
the second comparator 301 further comprises a second input terminal, and the first pole of the eighth sub-capacitor Ccap2 is connected to the fourth node N4 and the second pole is connected to the second input terminal of the second comparator 301.
It can be understood that, in the related art, three high bits generally correspond to three capacitors, and the present invention splits the three capacitors corresponding to three high bits into 7 capacitors with equal capacitance values, i.e., Ca to Cg and Ch to Cn, to implement noise shaping for three high bits.
Referring to FIG. 3, C5-C10 of the first module 10 are lowThe binary capacitance, C11, is used as the weight capacitance and does not participate in the conversion. The first poles of Ca-Cg and C5-C11, namely the voltage value of the upper pole plate, are input into the first input end of the first comparator 20, digital output is obtained through the comparison of the first comparator 20, and then the second poles of Ca-Cg and C5-C11, namely the lower pole plate, are controlled by the capacitance switches SW corresponding to Ca-Cg and C5-C11 respectively and connected to the first reference voltage signal end VCMA second reference voltage signal terminal VREFPOr a third reference voltage signal terminal VREFNTo implement a successive approximation of the dichotomy.
It should be noted that, in the present invention, the structures of the first module 10 and the second module 10 'are the same, and C12 to C17 in the second module 10' are low-order binary capacitors, and C18 does not participate in the conversion, which is not described herein again.
Specifically, in the auxiliary ADC module 30, the first poles of C19-C22 are connected to the first reference voltage signal terminal V through the sixth sampling switch S6CMThe connection is realized, and the connection and disconnection of the first sampling switch S1 realize that the C19-C22 pair the second signal input end VIPOf the second input signal. After the C1-C4 and C19-C22 respectively complete sampling, the second comparator 301 compares the sampling result of the C1-C4 on the second input signal with the sampling result of the C19-C22 on the first input signal, and inputs the comparison result to the second preset logic circuit 302, so as to obtain the three-bit quantization code. Referring to fig. 1, since the output terminal of the second preset logic circuit 302 is connected to the input terminal of the DWA module 40, the three-bit quantization code can be output by the DWA module 40 to obtain a seven-bit thermometer code, so that the first preset logic circuit 50 sets Ca to Cg and Ch to Cn according to the seven-bit thermometer code.
Further, the third sampling switch S3 and the fifth sampling switch S5 are closed to obtain a first integral voltage at the upper plate of the third sub-capacitor Cint1 and a second integral voltage at the upper plate of the sixth sub-capacitor Cint2, the first integral voltage and the second integral voltage are compared by the first comparator, and a comparison result is input into the first preset logic circuit 50 to obtain a seven-bit quantization code, so that the C5 to C11 and the C12 to C18 are set according to the seven-bit quantization code; and then, adding the three-dimensional quantization code and the seven-bit quantization code to obtain an analog-to-digital conversion result of the input signal.
Therefore, the analog-to-digital converter 100 provided by the invention adopts an MASH 1-0 shaping scheme, and can sample the second poles of Ca to Cg and C5 to C11 and the lower pole plates of Ch to Cn and C12 to C18, so that the influence of variable parasitic capacitance on the upper pole plate during sampling of the upper pole plate is avoided, and the influence of the variable parasitic capacitance of the upper pole plate on the linearity is effectively relieved. In addition, the analog-to-digital converter 100 comprises a DWA module 40, capacitors corresponding to high three bits in the related technology are divided into 7 capacitor units by combining sampling results of lower plates of Ca-Cg, C5-C11, Ch-Cn and C12-C18 and utilizing a high-bit data weighted average algorithm, so that noise shaping of the high three bits is achieved, mismatch errors of low-bit DACs in a main DAC array (namely Ca-Cg, C5-C11, Ch-Cn and C19-C22) can be subjected to first-order shaping by a MASH 1-0 shaping scheme, the mismatch errors of the whole main DAC array are subjected to first-order shaping, and circuit complexity is simplified.
Fig. 5 is a timing diagram of an operation of the analog-to-digital converter according to the embodiment of the present invention. Referring to fig. 3 to 5, an embodiment of the present invention further provides an analog-to-digital conversion method, including: a sampling stage, a first quantization stage, an integration stage and a second quantization stage; wherein the content of the first and second substances,
in the sampling phase, the second polarity of the C1-C4 and the second signal input end V in the first module 10 and the C5-C11 and the auxiliary ADC module 30 are respectively connected to the first and second signal input ends VIPSecond poles of Ch-Cn, C12-C18 and C19-C22 in the second module 10' are connected with the first signal input end VINThe first sampling switch S1, the second sampling switch S2, the fourth sampling switch S4 and the sixth sampling switch S6 are all closed, so that Ca to Cg and C5 to C11 in the first module 10 sample the second signal input signal, Ch to Cn and C12 to C18 in the second module 10' sample the first input signal, C1 to C4 in the auxiliary ADC module 30 sample the second input signal, and C19 to C21 sample the first input signal; the first input signal and the second input signal are both analog signals, and the voltage of the first input signal and the voltage of the second input signal are different;
in the first quantization stage, after the second comparator 301 compares the sampling results of C1-C4 on the second input signal with the sampling results of C19-C21 on the first input signal, the comparison results are input to the second preset logic circuit 302 to obtain a three-bit quantization code, the three-bit quantization code is input to the DWA module 40, and the converted seven-bit thermometer code is input to the first preset logic circuit 50, so that the first preset logic circuit 50 sets Ca to Cg and Ch to Cn according to the seven-bit thermometer code;
during the integration phase, the third sampling switch S3 and the fifth sampling switch S5 are closed, resulting in a first integrated voltage at the first pole of the third sub-capacitor Cint1 and a second integrated voltage at the first pole of the sixth sub-capacitor Cint 2;
in the second quantization stage, the first comparator 20 compares the first integrated voltage with the second integrated voltage, and inputs the comparison result to the first preset logic circuit 50, so that the first preset logic circuit 50 sets C5-C11 and C12-C18 to obtain a seven-bit quantization code, and adds the three-bit quantization code and the seven-bit quantization code to obtain an analog-to-digital conversion result of the input signal.
In this embodiment, the analog-to-digital conversion performed by the analog-to-digital converter 100 mainly includes four stages: a sampling phase, a first quantization phase, an integration phase and a second quantization phase.
In particular when
Figure BDA0003180250340000131
When the signal is "1", a sampling stage is entered, the first sampling switch S1, the second sampling switch S2, the fourth sampling switch S4 and the sixth sampling switch S6 are all closed, and at this time, Ca to Cg, C5 to C11 in the first module 10 and the second poles of C1 to C4 in the auxiliary ADC module 30 and the second signal input terminal V are all closedIPConnecting the second poles of Ch-Cn, C12-C18 in the second module 10' and C19-C22 in the auxiliary ADC module 30 with the first signal input terminal VINIn connection, Ca to Cg and C5 to C11 sample the second signal input signal, Ch to Cn and C12 to C18 sample the first input signal, C1 to C4 sample the second input signal, and C19 to C21 sample the first input signal.
When in use
Figure BDA0003180250340000132
When the signal is changed to "0", the sampling phase is finished, the upper plates of Ca to Cg, C5 to C11, C1 to C4, Ch to Cn, C12 to C18 and C19 to C22 store the sampled values of the corresponding sampling switches immediately before the closing of the sampling switches, and the values are also the values to be quantized by C1 to C4 and C19 to C22 in the auxiliary ADC module 30.
In FIG. 5, when
Figure BDA0003180250340000133
When the rising edge of the first square wave is entered, the first quantization stage starts, the second comparator 301 compares the sampling results of the C1-C4 on the second input signal with the sampling results of the C19-C21 on the first input signal, then inputs the comparison results into the second preset logic circuit 302, the second preset logic circuit 302 outputs the three-bit quantization code, then inputs the three-bit quantization code into the DWA module 40, the DWA module 40 converts the three-bit quantization code into the seven-bit thermometer code by using the high-bit data weighted average algorithm, and the obtained seven-bit thermometer code is further input into the first preset logic circuit 50, so that the first preset logic circuit 50 sets Ca-Cg and Ch-Cn according to the seven-bit thermometer code to obtain the seven-bit quantization code, and at this time, the first preset logic circuit 50 sets Ca-Cg and Ch-Cn according to the seven-bit thermometer code to obtain the seven-bit quantization code
Figure BDA0003180250340000141
The falling edge of the third square wave is entered and the first quantization phase ends.
Specifically, in this embodiment, the seven-bit thermometer code output by the DWA module 40 is transmitted to the first preset logic circuit, the first preset logic circuit 50 controls the second poles of Ca to Cg to be connected to the second reference voltage signal terminal VREFP or the third reference voltage signal terminal VREFN through the respective corresponding capacitance switches SW to complete setting, meanwhile, the seven-bit thermometer code output by the DWA module 40 is further inverted and then output to the first preset logic circuit 50, and the first preset logic circuit 50 controls the second poles of Ch to Cn to be connected to the second reference voltage signal terminal VREFP or the third reference voltage signal terminal VREFN through the respective corresponding capacitance switches SW to perform setting. It should be appreciated that since the set signals delivered by the first preset logic circuit 50 to Ca Cg and Ch Cn are opposite, the second polarity of Ca Cg and Ch Cn is connected to different VREFP and VREFN, i.e., the set result is different.
In addition, in the embodiment, the three-bit quantization code latched by the quantization is output to the 7-bit thermometer code through the DWA module 40, and the 7-bit thermometer code sequentially selects 7 capacitor units of Ca to Cg/Ch to Cn in a circulating manner, so that the randomization processing of the nonlinear error is realized, and the DWA module can better suppress harmonic distortion caused by the mismatch of the auxiliary DAC.
Please refer to fig. 5, when
Figure BDA0003180250340000142
On entering the rising edge of the square wave, the integration phase begins, the third sampling switch S3 and the fifth sampling switch S5 are closed,
Figure BDA0003180250340000143
the integration phase ends when the falling edge of the square wave is entered, resulting in a first integrated voltage at the first pole of the third sub-capacitor Cint1 and a second integrated voltage at the first pole of the sixth sub-capacitor Cint 2. It is understood that at this stage, the third sub-capacitor Cint1 shares charges with the capacitor arrays Ca to Cg and C5 to C10, and the sixth sub-capacitor Cint2 shares charges with the capacitor arrays Ch to Cn and C12 to C17, thereby completing the integration.
For example, in this embodiment, the sum of the capacitances of Ca to Cg and C5 to C11, the capacitance values of the third sub-capacitor Cint1 and the fourth sub-capacitor Cint ', the sum of the capacitances of Ch to Cn and C12 to C17, and the capacitance values of the sixth sub-capacitor Cint2 and the seventh sub-capacitor Cint2 ' are equal, and obviously, this design makes the first pole voltages of Ca to Cg and C5 to C11 in the first module 10 and the first pole voltages of Ch to Cn and C12 to C18 in the second module 10 ' both attenuate 1/2, which is equivalent to adding a one-bit redundancy bit.
And entering a second quantization stage after integration is completed, inputting voltage values of first poles of Ca-Cg and C5-C11 into a first input end of a first comparator 20, inputting voltage values of first poles of Ch-Cn and C12-C18 into a second input end of the first comparator 20, comparing the first integrated voltage with the second integrated voltage by the first comparator 20, inputting a comparison result into a first preset logic circuit 50 to obtain a seven-bit quantization code, wherein the seven-bit quantization code is the quantization results of C5-C11 and C12-C18, and adding the three-bit quantization code with the seven-bit quantization code to obtain an analog-to-digital conversion result of the input signal.
In the second quantization stage, the first preset logic circuit 50 will transmit the opposite set signal to the capacitor switch SW connected to the second pole of C5 and C12 according to the comparison result, C5 is connected to VREFP or VREFN, C12 is connected to VREFN or VREFP, and C5 and C12 are connected to different voltages, so the set result is different. After the setting of the C5 and the C12 is finished, the voltages of the nodes N2 and N3 are transmitted to the first comparator 301, the first comparator 301 continues to perform comparison, the setting of the C5 to C11 and the setting of the C12 to C18 are completed through the circulation operation, and finally the seven-bit quantization code is obtained.
It will be appreciated that the analog to digital conversion method provided by the present invention also includes an amplification stage. In order to realize noise shaping in the auxiliary ADC block 30, after a seven-bit quantization code is obtained by conversion in the second quantization stage, the first integrated voltage stored in the third sub-capacitor Cint1 is amplified by G times and stored in the second sub-capacitor Ccap3, the second integrated voltage stored in the sixth sub-capacitor Cint2 is amplified by G times and stored in the fifth sub-capacitor Ccap4,
Figure BDA0003180250340000161
after the signal is "1", the first pole of the second sub-capacitor Ccap3 is connected to the node N1, the second pole is connected to the first input end of the second comparator, so that the sum of the voltage stored in the second sub-capacitor Ccap3 and the residual voltage on the first poles of C1-C4 is realized, the first pole of the fifth sub-capacitor Ccap4 is connected to the node N4, the second pole is connected to the second input end of the second comparator, and the sum of the voltage stored in the fifth sub-capacitor Ccap4 and the residual voltage on the first poles of C19-C22 is realized.
In this embodiment, a series method may be adopted to implement summation operation, the first sub-capacitor Ccap1 and the eighth sub-capacitor Ccap2 alternately work in a ping-pong structure, and for the nth cycle, when the first sub-capacitor Ccap1 and the eighth sub-capacitor Ccap2 work in a ping-pong structure, the first sub-capacitor Ccap1 and the eighth sub-capacitor Ccap2 work in a ping-pong manner
Figure BDA0003180250340000162
When the signal is "1", the operational amplifier 60 amplifies the first integration voltage by G times, and after the amplification is completed, the amplified voltage value is stored in the first sub-capacitor Ccap 1. In the (N + 1) th period, the first sub-capacitor Ccap1 and the eighth sub-capacitor Ccap2 are alternated, the upper plate voltages of C1-C4 are (GVINT + Vref), wherein Gvint represents the first integral voltage amplified by G times, Vref represents the upper plate voltages of Ca-Cg and C5-C11,
Figure BDA0003180250340000163
after the signal is "1", the auxiliary ADC module 30 starts quantization, obtains digital output through comparison of the second comparator 301, and generates a three-bit quantization code, and Ccap2 is a feedback capacitor of the operational amplifier and stores an amplified voltage value, so that noise shaping is realized by alternately working at three high bits.
To more clearly show the working principle, fig. 6 is a signal flow diagram for mismatch error shaping of the capacitor array provided by the embodiment of the present invention, and it can be understood that the capacitor array refers to C1-C4 and C19-C22 and Ca-C11 and Ch-C18. Referring to fig. 6, after the quantization of the high-side auxiliary SAR ADC (C1-C4, C19-C22) is completed, the quantized result is transmitted to the first predetermined logic circuit, and the conversion residual is obtained at the top plates of Ca-Cg, C5-C11, Ch-Ca and C12-C18, wherein the conversion residual includes distortion errors from DAC nonlinearity and mismatch, which may deteriorate the linearity of the analog-to-digital converter 100. In order to reduce the influence caused by capacitance mismatch and nonlinearity, the analog-to-digital conversion method provided by the invention adopts an NS SAR ADC with an N-0MASH framework. And the Ca-Cg and the Ch-Cn adopt DWA algorithm to realize mismatching error shaping, and can be obtained according to the Meisen formula:
D(z)＝VIN(z)+(1-z-1)E1(z)+[1-H1(z)]·[Δ·Q1(z)+Q2(z)+E2(z)]
in the formula, delta represents a gain error, E1 is a mismatch error of C1-C4 and C19-C22, and E2 is a mismatch error of C5-C11 and C12-C18, so that the capacitor array mismatch error shaping technology can simultaneously shape a capacitor mismatch error, a gain error and second-stage quantization noise, and the limitation of the mismatch error on high precision is broken through.
The analog-to-digital conversion method is further explained by simulation experiments.
Specifically, a 65nm standard CMOS process is adopted for circuit design, an analog-to-digital converter works under 1.2V power supply voltage, the highest sampling frequency is 2MS/s, the input signal amplitude is 2.16V Vpp, wherein the input signal comprises a first signal input end VIPAnd a first input signal and a second signal input terminal VINOf the first input signal. Fig. 7 is a simulation result diagram of the analog-to-digital conversion method according to the embodiment of the present invention. When the frequency of the input signal is 854.5Hz, the frequency spectrum of the ADC obtained by the test is shown in FIG. 7, the harmonic noise (SNDR) of the SAR ADC signal is 115dB, the dynamic range (SFDR) without stray noise is 78dB, and the effective precision is 18.8 bits. Therefore, after mismatch error integer, the SFDR is improved by 40dB, and the invention realizes great improvement of linearity by reducing mismatch of the capacitor array and reducing quantization noise.
The beneficial effects of the invention are as follows:
the invention provides an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end, and because the analog-to-digital converter adopts an MASH 1-0 shaping scheme, the analog-to-digital converter can sample the second poles of Ca-Cg and C5-C11, namely the lower pole plates of Ca-Cg and C5-C11 when carrying out analog-to-digital conversion, thereby avoiding the influence of variable parasitic capacitance on the upper pole plate when carrying out upper sampling and effectively relieving the influence of the variable parasitic capacitance on the linearity.
In addition, the analog-to-digital converter also comprises a DWA module, three capacitors corresponding to high three bits in the related technology are converted into Ca-Cg 7 capacitors by combining a capacitor bottom plate sampling result in the first module and a high-bit data weighted average algorithm, so that the noise shaping of the high three bits is achieved, the MASH 1-0 shaping scheme can carry out first-order shaping on mismatch errors of a low-bit DAC (namely C5-C11), and further the mismatch errors of the whole main DAC array are shaped in a first-order manner, so that the circuit complexity is simplified.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. An analog-to-digital converter, comprising: the device comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end; wherein the content of the first and second substances,
the auxiliary ADC module comprises a first type capacitor, a first sub-capacitor, a second comparator, a second preset logic circuit and a first node, wherein the first type capacitor comprises: C1-C4, a first pole of C1-C4 connected to the first node, a second pole connected to one of the second signal input terminal, the first reference voltage signal terminal, the second reference voltage signal terminal or the third reference voltage signal terminal; the second comparator comprises a first input end and an output end, the first pole of the first sub-capacitor is connected with the first node, the second pole of the first sub-capacitor is connected with the first input end of the second comparator, the output end of the second comparator is connected with the input end of the second preset logic circuit, the output end of the second preset logic circuit is connected with the input end of the DWA module, and the output end of the DWA module is connected with the first preset logic circuit;
the first module comprises a second type of capacitor, a third type of capacitor and a second node, wherein the second type of capacitor comprises: ca to Cg, the third type of capacitance comprises: C5-C11, Ca-Cg and C5-C11 having first poles connected to the second node and second poles connected to one of the second signal input terminal, the first reference voltage signal terminal, the second reference voltage signal terminal or the third reference voltage signal terminal;
the first comparator comprises a first input end and an output end, the first input end of the first comparator is connected with the second node, and the output end of the first comparator is connected with the first preset logic circuit.
2. The analog-to-digital converter according to claim 1, further comprising a first sampling switch and a second sampling switch;
in the auxiliary ADC module, the first poles of C1-C4 are connected with the first reference voltage signal end through the first sampling switch;
in the first module, Ca to Cg and C5 to C11 are connected with the first reference voltage signal end through the second sampling switch.
3. The analog-to-digital converter according to claim 2, further comprising an operational amplifier, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor and a third sampling switch;
the operational amplifier comprises a first input end and a first output end, the first input end of the operational amplifier is connected to the second node, the first output end of the operational amplifier is connected with the first pole of the fourth sub-capacitor, and the second pole of the fourth sub-capacitor is grounded;
the first pole of the second sub-capacitor is connected with the first input end of the operational amplifier, and the second pole of the second sub-capacitor is connected with the output end of the operational amplifier;
the first pole of the third sub-capacitor is connected to the second node through the third sampling switch, and the second pole of the third sub-capacitor is grounded.
4. The analog-to-digital converter according to claim 2, further comprising a second module comprising a fourth type of capacitance and a fifth type of capacitance and a third node;
the fourth type of capacitor comprises: ch to Cn, the fifth type of capacitor comprises: first poles of C12-C18, Ch-Cn and C12-C18 are connected to the third node, and second poles are connected to one of the first signal input terminal, the first reference voltage signal terminal, the second reference voltage signal terminal or the third reference voltage signal terminal.
5. The analog-to-digital converter according to claim 4, further comprising a fourth sampling switch, wherein in the second block, the first poles of Ch to Cn and C12 to C18 are connected to the first reference voltage signal terminal through the fourth sampling switch.
6. The analog-to-digital converter according to claim 5, further comprising a fifth sub-capacitor, a sixth sub-capacitor, a seventh sub-capacitor and a fifth sampling switch, the operational amplifier further comprising a second input terminal and a second output terminal;
a second input end of the operational amplifier is connected to the third node, a second output end of the operational amplifier is connected with a first pole of the seventh sub-capacitor, and a second pole of the seventh sub-capacitor is grounded;
the first pole of the fifth sub-capacitor is connected with the second input end of the operational amplifier, and the second pole of the fifth sub-capacitor is connected with the second output end of the operational amplifier;
the first pole of the sixth sub-capacitor is connected to the third node through the fifth sampling switch, and the second pole of the sixth sub-capacitor is grounded.
7. The analog-to-digital converter according to claim 1, wherein the auxiliary ADC module further comprises a sixth type of capacitance, an eighth sub-capacitance and a sixth node, the sixth type of capacitance comprising: C19-C22, wherein a first pole of C19-C22 is connected to the sixth node, and a second pole is connected to one of the first signal input terminal, the first reference voltage signal segment, the second reference voltage signal terminal or the third reference voltage signal terminal;
the second comparator further comprises a second input end, the first pole of the eighth sub-capacitor is connected with the sixth node, and the second pole of the eighth sub-capacitor is connected with the second input end of the second comparator.
8. The analog-to-digital converter according to claim 7, further comprising a sixth sampling switch;
in the auxiliary ADC module, the first poles of C19-C22 are connected with the first reference voltage signal end through the sixth sampling switch.
9. An analog-to-digital conversion method applied to the analog-to-digital converter of any one of claims 1 to 8, comprising: a sampling stage, a first quantization stage, an integration stage and a second quantization stage; wherein the content of the first and second substances,
in a sampling stage, second poles of Ca-Cg, C1-C4 and C5-C11 are connected with the second signal input end, second poles of Ch-Cn, C19-C22 and C12-C18 are connected with the first signal input end, and a first sampling switch, a second sampling switch, a fourth sampling switch and a sixth sampling switch are all closed, so that Ca-Cg and C5-C11 in the first module sample the second signal input signal, Ch-Cn and C12-C18 in the second module sample the first input signal, and C1-C4 in the auxiliary ADC module sample the second input signal and C19-C21 sample the first input signal; the first input signal and the second input signal are both analog signals, and the voltage of the first input signal is different from that of the second input signal;
in a first quantization stage, after the sampling results of the C1-C4 on the second input signal and the sampling results of the C19-C21 on the first input signal are compared by a second comparator, the comparison results are input into the second preset logic circuit to obtain a three-bit quantization code, the three-bit quantization code is input into the DWA module, and a seven-bit thermometer code obtained by conversion is input into the first preset logic circuit, so that the first preset logic circuit sets Ca-Cg and Ch-Cn according to the seven-bit thermometer code;
in the integration stage, the third sampling switch and the fifth sampling switch are closed to obtain a first integration voltage at the first pole of the third sub-capacitor and a second integration voltage at the first pole of the sixth sub-capacitor;
in a second quantization stage, the first comparator compares the first integrated voltage with the second integrated voltage, and inputs the comparison result to the first preset logic circuit, so that the first preset logic circuit sets C5-C11 and C12-C18 to obtain a seven-bit quantization code, and the three-bit quantization code and the seven-bit quantization code are added to obtain an analog-to-digital conversion result of the input signal.
10. The method of claim 9, wherein the sum of the capacitances of Ca to Cg and C5 to C11 is equal to the capacitance values of the third and fourth sub-capacitors, and the sum of the capacitances of Ch to Cn and C12 to C17 is equal to the capacitance values of the sixth and seventh sub-capacitors.
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