CN113726338B - Analog-to-digital converter and analog-to-digital conversion method - Google Patents

Analog-to-digital converter and analog-to-digital conversion method Download PDF

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CN113726338B
CN113726338B CN202110845211.5A CN202110845211A CN113726338B CN 113726338 B CN113726338 B CN 113726338B CN 202110845211 A CN202110845211 A CN 202110845211A CN 113726338 B CN113726338 B CN 113726338B
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sub
capacitor
pole
reference voltage
analog
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CN113726338A (en
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丁瑞雪
金宏杰
刘术彬
张延博
李琳
朱樟明
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter comprises: the device comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end; the analog-to-digital converter can sample the lower polar plates of Ca-Cg and C5-C11 when performing analog-to-digital conversion, so that the influence of variable parasitic capacitance on the upper polar plate when the upper polar plate is sampled is avoided; and by combining the capacitance lower polar plate sampling result in the first module and the high bit data weighted average algorithm, the high three-bit noise shaping is achieved, and meanwhile, the C5-C11 mismatch errors are shaped in a first order, so that the mismatch errors of the whole main DAC array are shaped in the first order, and the circuit complexity is simplified.

Description

Analog-to-digital converter and analog-to-digital conversion method
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to an analog-to-digital converter and an analog-to-digital conversion method.
Background
Analog-to-digital converters (Analog to Digital Converter, ADC) are bridges connecting the real world with the digital world, playing an irreplaceable role in various fields such as detection systems and modern communications. The continuous development of biological signal detection equipment such as electroencephalogram detection, piezoelectric detection and the like promotes the further improvement of detection precision, and simultaneously stimulates the development of ADC (analog to digital converter) towards low power consumption and high precision.
The successive approximation type analog-to-digital converter is simple in structure, most of the successive approximation type analog-to-digital converters are digital modules and dynamic logic, low power consumption can be achieved, and high requirements are met in high-resolution application, wherein mismatch of a capacitor array is a key factor affecting circuit accuracy. The successive approximation type ADC uses a Mismatch Error Shaping (MES) method to reduce the requirement on a capacitor array, however, the traditional MES method is required to sample an upper polar plate, the variable parasitic capacitance of the upper polar plate of the capacitor array can have a larger influence on the low-order capacitance, so that the capacitance mismatch is serious, and the MES method in the related technology cannot shape the inter-stage gain error, thereby limiting the integral accuracy of the ADC not to be improved, and simultaneously reducing the linearity.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an analog-to-digital converter and an analog-to-digital conversion method. The technical problems to be solved by the invention are realized by the following technical scheme:
in a first aspect, the present invention provides an analog-to-digital converter comprising: the device comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end; wherein,
The auxiliary ADC module comprises a first capacitor, a first sub-capacitor, a second comparator, a second preset logic circuit and a first node, wherein the first capacitor comprises: the first poles of C1-C4 and C1-C4 are connected with the first node, the second pole is connected with one of the second signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end; the second comparator comprises a first input end and an output end, a first pole of the first sub-capacitor is connected with the first node, a second pole of the first sub-capacitor is connected with the first input end of the second comparator, the output end of the second comparator is connected with the input end of the second preset logic circuit, the output end of the second preset logic circuit is connected with the input end of the DWA module, and the output end of the DWA module is connected with the first preset logic circuit;
the first module comprises a second type capacitor, a third type capacitor and a second node, wherein the second type capacitor comprises: ca to Cg, the third type of capacitance includes: the first poles of C5-C11, ca-Cg and C5-C11 are connected with the second node, and the second pole is connected with one of the second signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end;
The first comparator comprises a first input end and an output end, wherein the first input end of the first comparator is connected with the second node, and the output end of the first comparator is connected with the first preset logic circuit.
In one embodiment of the present invention, the method further comprises a first sampling switch and a second sampling switch;
in the auxiliary ADC module, a first pole of C1-C4 is connected with the first reference voltage signal end through the first sampling switch;
in the first module, ca-Cg and C5-C11 are connected with the first reference voltage signal end through the second sampling switch.
In one embodiment of the present invention, the circuit further comprises an operational amplifier, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor and a third sampling switch;
the operational amplifier comprises a first input end and a first output end, wherein the first input end of the operational amplifier is connected to the second node, the first output end of the operational amplifier is connected with the first pole of the fourth sub-capacitor, and the second pole of the fourth sub-capacitor is grounded;
the first pole of the second sub-capacitor is connected with the first input end of the operational amplifier, and the second pole of the second sub-capacitor is connected with the output end of the operational amplifier;
The first pole of the third sub-capacitor is connected to the second node and the second pole is grounded through the third sampling switch.
In one embodiment of the present invention, a second module is further included, the second module including fourth and fifth types of capacitances and a second node;
the fourth type of capacitance includes: ch to Cn, the fifth type of capacitance includes: the first poles of C12-C18, ch-Cn and C12-C18 are connected with the second node, and the second pole is connected with one of the first signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end.
In one embodiment of the present invention, a fourth sampling switch is further included, and in the second module, ch to Cn and the first poles of C12 to C18 are connected to the first reference voltage signal terminal through the fourth sampling switch.
In one embodiment of the present invention, the operational amplifier further includes a fifth sub-capacitor, a sixth sub-capacitor, a seventh sub-capacitor, and a fifth sampling switch, and further includes a second input terminal and a second output terminal;
the second input end of the operational amplifier is connected to the second node, the second output end of the operational amplifier is connected with the first pole of the seventh sub-capacitor, and the second pole of the seventh sub-capacitor is grounded;
The first pole of the fifth sub-capacitor is connected with the second input end of the operational amplifier, and the second pole of the fifth sub-capacitor is connected with the second output end of the operational amplifier;
the first pole of the sixth sub-capacitor is connected to the second node and the second pole is grounded through the fifth sampling switch.
In one embodiment of the present invention, the auxiliary ADC module further includes a sixth type of capacitance, an eighth sub-capacitance, and a fourth node, the sixth type of capacitance including: the first poles of C19-C22 are connected with the fourth node, and the second poles are connected with one of the first signal input end, the first reference voltage signal section, the second reference voltage signal end or the third reference voltage signal end;
the second comparator further comprises a second input end, a first pole of the eighth sub-capacitor is connected with the fourth node, and a second pole of the eighth sub-capacitor is connected with the second input end of the second comparator.
In one embodiment of the present invention, a sixth sampling switch is further included;
in the auxiliary ADC module, a first pole of C19-C22 is connected with the first reference voltage signal end through the sixth sampling switch.
In a second aspect, the present invention further provides an analog-to-digital conversion method, which is applied to the analog-to-digital converter in the first aspect, and includes: a sampling phase, a first quantization phase, an integration phase and a second quantization phase; wherein,
In the sampling stage, the second poles of Ca-Cg, C1-C4 and C5-C11 are connected with the second signal input end, the second poles of Ch-Cn, C19-C22 and C12-C18 are connected with the first signal input end, and the first sampling switch, the second sampling switch, the fourth sampling switch and the sixth sampling switch are all closed so that Ca-Cg and C5-C11 in the first module sample the second signal input signal, ch-Cn and C12-C18 in the second module sample the first input signal, and C1-C4 in the auxiliary ADC module sample the second input signal and C19-C21 sample the first input signal; the first input signal and the second input signal are analog signals, and the voltage of the first input signal is different from that of the second input signal;
in a first quantization stage, a second comparator compares the sampling result of the second input signal by C1-C4 and the sampling result of the first input signal by C19-C21, then inputs the comparison result into a second preset logic circuit to obtain a three-bit quantization code, inputs the three-bit quantization code into the DWA module, inputs the seven-bit thermometer code obtained by conversion into a first preset logic circuit, and enables the first preset logic circuit to set Ca-Cg and Ch-Cn according to the seven-bit thermometer code;
In the integration stage, the third sampling switch and the fifth sampling switch are closed to obtain a first integrated voltage at the first pole of the third sub-capacitor and a second integrated voltage at the first pole of the sixth sub-capacitor;
in the second quantization stage, the first comparator compares the first integrated voltage with the second integrated voltage, inputs the comparison result to the first preset logic circuit, so that the first preset logic circuit sets C5-C11 and C12-C18 to obtain seven-bit quantization codes, and adds the three-bit quantization codes and the seven-bit quantization codes to obtain an analog-to-digital conversion result of an input signal.
In one embodiment of the present invention, the sum of the capacitances of Ca to Cg and C5 to C11, the capacitance values of the third sub-capacitance and the fourth sub-capacitance are equal, the sum of the capacitances of Ch to Cn and C12 to C17, and the capacitance values of the sixth sub-capacitance and the seventh sub-capacitance are equal.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end, and because the analog-to-digital converter adopts a MASH 1-0 shaping scheme, the second poles of Ca-Cg and C5-C11, namely the lower pole plates of Ca-Cg and C5-C11, can be sampled when the analog-to-digital converter is used for carrying out analog-to-digital conversion, thereby avoiding the influence of variable parasitic capacitance on an upper pole plate when the upper pole plate is sampled and effectively relieving the influence of variable parasitic capacitance of the upper pole plate on linearity.
In addition, the analog-to-digital converter further comprises a DWA module, three capacitors corresponding to the upper three bits in the correlation technology are converted into Ca-Cg 7 capacitors by combining the capacitor lower plate sampling result in the first module and the high bit data weighted average algorithm, so that high three-bit noise shaping is achieved, the MASH 1-0 shaping scheme can carry out first-order shaping on mismatch errors of the low-bit DAC, namely C5-C11, and the mismatch errors of the whole main DAC array are all shaped in the first order, so that the circuit complexity is simplified.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an auxiliary ADC module according to an embodiment of the invention;
fig. 3 is a schematic diagram of another structure of an analog-to-digital converter according to an embodiment of the present invention;
fig. 4 is another schematic structural diagram of an auxiliary ADC module according to an embodiment of the invention;
FIG. 5 is a timing diagram of the operation of the analog-to-digital converter according to the embodiment of the present invention;
FIG. 6 is a graph of a capacitive array mismatch error shaping signal provided by an embodiment of the present invention;
fig. 7 is a diagram of simulation results of an analog-to-digital conversion method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Fig. 1 is a schematic structural diagram of an analog-to-digital converter according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of an auxiliary ADC module according to an embodiment of the present invention. As shown in fig. 1-2, the present invention provides an analog-to-digital converter 100 comprising: first module 10, first comparator 20, auxiliary ADC module 30, DWA module 40, first preset logic circuit 50, first signal input terminal V IN A second signal input terminal V IP A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP And a third reference voltage signal terminal V REFN The method comprises the steps of carrying out a first treatment on the surface of the Wherein,
the auxiliary ADC module 30 includes a first type of capacitance, a first sub-capacitance, a second comparator 301, a second preset logic circuit 302, and a first node N1, the first type of capacitance including: C1-C4, the first pole of C1-C4 is connected with the first node N1, the second pole is connected with the second signal input end V IP A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN One of themConnecting; the second comparator 301 includes a first input terminal and an output terminal, a first pole of the first sub-capacitor is connected to the first node N1, a second pole is connected to the first input terminal of the second comparator 301, the output terminal of the second comparator 301 is connected to the input terminal of the second preset logic circuit 302, the output terminal of the second preset logic circuit 302 is connected to the input terminal of the DWA module 40, and the output terminal of the DWA module 40 is connected to the first preset logic circuit 50;
The first module 10 includes a second type of capacitance, a third type of capacitance, and a second node N2, the second type of capacitance including: ca to Cg, the third type of capacitance includes: C5-C11, ca-Cg, and C5-C11, the first pole being connected to the second node N2, the second pole being connected to the second signal input terminal V IP A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN One of them is connected;
the first comparator 20 includes a first input terminal and an output terminal, the first input terminal of the first comparator 20 is connected to the second node N2, and the output terminal is connected to the first preset logic circuit 50.
Specifically, the analog-to-digital converter 100 includes a first module 10, a first comparator 20, an auxiliary ADC module 30, a DWA module 40, a first preset logic circuit 50, a first signal input V IN A second signal input terminal V IP A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP And a third reference voltage signal terminal V REFN Wherein the first poles of the second type capacitors Ca-Cg and the third type capacitors C5-C11 in the first module 10 are connected with the second node N2, and the second poles are connected with the second signal input terminal V IP A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN Optionally, the analog-to-digital converter 100 further includes a second sampling switch S2, ca-Cg, and C5-C11 connected to the first reference voltage signal terminal V via the second sampling switch S2 CM Is connected with the second sampling switch S2, and Ca-Cg and C5-C11 can be connected with the second signal input terminal V IP Is sampled when the second input signal of (2) is sampledWhen the sampling switch S2 is turned off, ca to Cg and C5 to C11 end sampling the second input signal.
Further, the auxiliary ADC module 30 includes a first type of capacitance: C1-C4, a first sub-capacitor Ccap1, a second comparator 301, a second preset logic circuit 302 and a first node N1, wherein the first poles of C1-C4 are connected with the first node N1, and the second pole is connected with a second signal input end V IP A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN One of which is connected. Referring to fig. 2, in the auxiliary ADC module 30, the first poles of C1-C4 are connected to the first reference voltage signal terminal V through the first sampling switch S1 CM Connection, C1-C4 can be realized by closing and opening the first sampling switch S1 to the second signal input end V IP Is sampled.
It should be noted that, in the embodiment, the first input signal and the second input signal are both analog signals, and the voltages of the two signals are different.
Optionally, referring to fig. 1, the analog-to-digital converter 100 further includes an operational amplifier 60, a second sub-capacitor Ccap3, a third sub-capacitor Cint1, a fourth sub-capacitor Cint' and a third sampling switch S3;
the operational amplifier 60 includes a first input end and a first output end, the first input end of the operational amplifier 60 is connected to the second node N2, the first output end is connected to the first pole of the fourth sub-capacitor Cint ', and the second pole of the fourth sub-capacitor Cint' is grounded;
a first pole of the second sub capacitor Ccap3 is connected with a first input end of the operational amplifier 60, and a second pole is connected with an output end of the operational amplifier 60;
the first pole of the third sub-capacitor Cint1 is connected to the second node N2 via the third sampling switch S3, and the second pole is grounded.
Optionally, the first input terminal of the operational amplifier 60 is a non-inverting input terminal, the non-inverting input terminal is connected to the second node N2 in the first module 10, the first output terminal is connected to the first pole of the fourth sub-capacitor Cint ', and the second pole of the fourth sub-capacitor Cint' is grounded. In addition, the first pole of the second sub-capacitor Ccap3 is connected to the first input terminal of the operational amplifier 60, the second pole is connected to the output terminal of the operational amplifier 60, the first pole of the third sub-capacitor Cint1 is connected to the second node N2 through the third sampling switch S3, and the second pole is grounded, and when the third sampling switch S3 is closed, the first integrated voltage at the first pole of the third sub-capacitor Cint1 is obtained.
It should be noted that, in the analog-to-digital converter 100 provided by the present invention, a fully differential circuit structure is actually adopted, and fig. 1 is only illustrated by taking a single-ended example.
Fig. 3 is a schematic diagram of another structure of an analog-to-digital converter according to an embodiment of the present invention. Referring to fig. 3, the analog-to-digital converter 100 further includes a second module 10', wherein the second module 10' includes a fourth type of capacitor, a fifth type of capacitor and a third node N3;
the fourth type of capacitance includes: ch to Cn, the fifth type of capacitance includes: C12-C18, ch-Cn, and C12-C18, the first pole connected to the third node N3, the second pole connected to the first signal input terminal V IN A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN One of which is connected.
Optionally, the analog-to-digital converter 100 further includes a fourth sampling switch S4, and the first poles of Ch-Cn and C12-C18 in the second module 10' are connected with the first reference voltage signal terminal V via the fourth sampling switch S4 CM And (5) connection.
With continued reference to fig. 3, the analog-to-digital converter 100 further includes a fifth sub-capacitor Ccap4, a sixth sub-capacitor Cint2, a seventh sub-capacitor Cint2', and a fifth sampling switch S5, and the operational amplifier 60 further includes a second input terminal and a second output terminal;
Wherein, the second input end of the operational amplifier 60 is connected to the third node N3, the second output end is connected to the first pole of the seventh sub-capacitor Cint2', and the second pole of the seventh sub-capacitor Cint2' is grounded;
the first pole of the fifth sub-capacitor Ccap4 is connected with the second input end of the operational amplifier 60, and the second pole is connected with the second output end of the operational amplifier 60;
the first pole of the sixth sub-capacitor Cint2 is connected to the third node N3 and the second pole is grounded through the fifth sampling switch S5.
Fig. 4 is another schematic structural diagram of an auxiliary ADC module according to an embodiment of the invention. Optionally, as shown in fig. 4, the analog-to-digital converter 100 further includes a sixth sampling switch S6;
in the auxiliary ADC module 30, the first poles of C19-C22 are connected with the first reference voltage signal terminal V through the sixth sampling switch S6 CM And (5) connection.
It should be appreciated that for the second module 10', ch-Cn and C12-C18 are connected to the first reference voltage signal terminal V via the fourth sampling switch S4 CM When the fourth sampling switch S4 is closed, ch-Cn and C12-C18 start to be connected to the first signal input terminal V IN When the second sampling switch S2 is turned off, ch to Cn and C12 to C18 end the sampling of the first input signal.
Specifically, the auxiliary ADC module 30 further includes a sixth type of capacitor, an eighth sub-capacitor cca 2, and a fourth node N4, where the sixth type of capacitor includes: C19-C22, the first pole of C19-C22 is connected with the fourth node N4, the second pole is connected with the first signal input end V IN A first reference voltage signal terminal V CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN One of them is connected;
the second comparator 301 further includes a second input terminal, and the first pole of the eighth sub-capacitor cca 2 is connected to the fourth node N4, and the second pole is connected to the second input terminal of the second comparator 301.
It can be understood that three capacitors are usually corresponding to the upper three bits in the related art, and the three capacitors corresponding to the upper three bits are split into 7 capacitors with equal capacitance values, namely Ca-Cg and Ch-Cn, so as to realize noise shaping of the upper three bits.
With continued reference to fig. 3, C5-C10 in the first module 10 are low binary capacitors, and C11 is used as a weight capacitor and does not participate in the conversion. The voltage values of the first poles Ca-Cg and C5-C11, i.e. the upper pole plates, are input into the first input end of the first comparator 20, are compared by the first comparator 20 to obtain digital output, and are input according to the first preset logic circuit 50 The second poles of Ca-Cg and C5-C11, namely the lower polar plate, are controlled and connected to the first reference voltage signal end V by the capacitance switches SW corresponding to Ca-Cg and C5-C11 respectively CM Second reference voltage signal terminal V REFP Or a third reference voltage signal terminal V REFN To implement a successive approximation process of the dichotomy.
It should be noted that, in the present invention, the first module 10 and the second module 10 'have the same structure, and the second module 10' has the C12-C17 low-order binary capacitor, and the C18 does not participate in the conversion, which is not repeated here.
Specifically, in the auxiliary ADC module 30, the first poles of C19 to C22 are connected to the first reference voltage signal terminal V through the sixth sampling switch S6 CM Is connected with a second signal input end V of C19-C22 through the closing and opening of a first sampling switch S1 IP Is provided for the second input signal. After C1 to C4 and C19 to C22 finish sampling respectively, the second comparator 301 compares the sampling result of the second input signal from C1 to C4 with the sampling result of the first input signal from C19 to C22, and inputs the comparison result to the second preset logic circuit 302, thereby obtaining the three-bit quantization code. With continued reference to fig. 1, since the output terminal of the second preset logic circuit 302 is connected to the input terminal of the DWA module 40, the three-bit quantization code can be output by the DWA module 40 to obtain a seven-bit thermometer code, so that the first preset logic circuit 50 sets Ca to Cg and Ch to Cn according to the seven-bit thermometer code.
Further, the third sampling switch S3 and the fifth sampling switch S5 are closed to obtain a first integrated voltage at the upper polar plate of the third sub-capacitor Cint1 and a second integrated voltage at the upper polar plate of the sixth sub-capacitor Cint2, the first integrated voltage and the second voltage are compared by a first comparator, and the comparison result is input into a first preset logic circuit 50 to obtain a seven-bit quantization code, so that the C5-C11 and the C12-C18 are set according to the seven-bit quantization code; and then, adding the three-dimensional quantized code and the seven-bit quantized code to obtain an analog-to-digital conversion result of the input signal.
Therefore, the analog-to-digital converter 100 provided by the invention adopts the MASH 1-0 shaping scheme, and can sample the second poles of Ca-Cg and C5-C11 and the lower pole plates of Ch-Cn and C12-C18, so that the influence of the variable parasitic capacitance of the upper pole plate on the upper pole plate during the sampling of the upper pole plate is avoided, and the influence of the variable parasitic capacitance of the upper pole plate on the linearity is effectively relieved. In addition, the analog-to-digital converter 100 includes the DWA module 40, by combining the sampling results of the lower polar plates of Ca to Cg, C5 to C11, ch to Cn, and C12 to C18, and using the weighted average algorithm of high-order bits, the capacitors corresponding to the high three bits in the correlation technique are split into 7 capacitor units, so as to achieve the noise shaping of the high three bits, and the MASH 1-0 shaping scheme can perform the first-order shaping on the mismatch errors of the low-order DACs in the main DAC arrays (i.e., ca to Cg, C5 to C11, ch to Cn, and C19 to C22), so that the mismatch errors of the whole main DAC array are all shaped by the first-order, thereby simplifying the circuit complexity.
Fig. 5 is a timing chart of the operation of the analog-to-digital converter according to the embodiment of the present invention. Referring to fig. 3 to 5, the embodiment of the present invention further provides an analog-to-digital conversion method, which includes: a sampling phase, a first quantization phase, an integration phase and a second quantization phase; wherein,
during the sampling phase, ca-Cg, C5-C11 in the first module 10 and C1-C4 in the auxiliary ADC module 30 are coupled to the second pole and the second signal input terminal V IP Second and first signal input terminals V connected with Ch-Cn, C12-C18 and C19-C22 in the second module 10 IN The first sampling switch S1, the second sampling switch S2, the fourth sampling switch S4 and the sixth sampling switch S6 are all closed so as to enable Ca-Cg and C5-C11 in the first module 10 to sample the second signal input signals, ch-Cn and C12-C18 in the second module 10' to sample the first input signals, C1-C4 in the auxiliary ADC module 30 to sample the second input signals and C19-C21 to sample the first input signals; the first input signal and the second input signal are analog signals, and the voltages of the first input signal and the second input signal are different;
in the first quantization stage, the second comparator 301 compares the sampling result of the second input signal from C1 to C4 with the sampling result of the first input signal from C19 to C21, and then inputs the comparison result to the second preset logic circuit 302 to obtain a three-bit quantization code, and inputs the three-bit quantization code to the DWA module 40, and inputs the converted seven-bit thermometer code to the first preset logic circuit 50, so that the first preset logic circuit 50 sets Ca to Cg and Ch to Cn according to the seven-bit thermometer code;
In the integration stage, the third sampling switch S3 and the fifth sampling switch S5 are closed to obtain a first integrated voltage at the first pole of the third sub-capacitor Cint1 and a second integrated voltage at the first pole of the sixth sub-capacitor Cint 2;
in the second quantization stage, the first comparator 20 compares the first integrated voltage with the second integrated voltage, and inputs the comparison result to the first preset logic circuit 50, so that the first preset logic circuit 50 sets the C5 to C11 and the C12 to C18 to obtain a seven-bit quantization code, and adds the three-bit quantization code and the seven-bit quantization code to obtain an analog-to-digital conversion result of the input signal.
In this embodiment, when the analog-to-digital converter 100 is used for analog-to-digital conversion, the method mainly includes four stages: a sampling phase, a first quantization phase, an integration phase and a second quantization phase.
Specifically, whenWhen the signal is "1", the sampling stage is entered, the first sampling switch S1, the second sampling switch S2, the fourth sampling switch S4 and the sixth sampling switch S6 are all closed, and at this time, the Ca to Cg, C5 to C11 in the first module 10 and the second poles of C1 to C4 in the auxiliary ADC module 30 and the second signal input terminal V IP Second and first signal input terminals V connected with Ch-Cn, C12-C18 in the second module 10' and C19-C22 in the auxiliary ADC module 30 IN And the connection is that Ca-Cg and C5-C11 sample the second signal input signal, ch-Cn and C12-C18 sample the first input signal, C1-C4 sample the second input signal and C19-C21 sample the first input signal.
When (when)When the signal becomes "0", the sampling phase ends, ca to Cg, C5 to C11, C1 to C4, ch to Cn, C12 to C18 and C19 to C22The upper plate of (C) stores the sampled value immediately before the corresponding sampling switch is closed, which is also the value to be quantized for C1-C4 and C19-C22 in the auxiliary ADC module 30.
In FIG. 5, whenWhen the rising edge of the first square wave is entered, the first quantization stage starts, the second comparator 301 compares the sampling results of the second input signals from C1 to C4 and the sampling results of the first input signals from C19 to C21, then inputs the comparison results to the second preset logic circuit 302, the second preset logic circuit 302 outputs a three-bit quantization code, and further inputs the three-bit quantization code to the DWA module 40, the DWA module 40 converts the three-bit quantization code into a seven-bit thermometer code by using a high-bit data weighted average algorithm, and the obtained seven-bit thermometer code is further input to the first preset logic circuit 50, so that the first preset logic circuit 50 sets Ca to Cg and Ch to Cn according to the seven-bit thermometer code to obtain a seven-bit quantization code, at this time, the three-bit quantization code is converted into a seven-bit thermometer code by the DWA high-bit data weighted average algorithm >A falling edge of the third square wave is entered and the first quantization phase ends.
Specifically, in this embodiment, the seven-bit thermometer code output by the DWA module 40 is transmitted to the first preset logic circuit, the first preset logic circuit 50 controls the second poles of Ca to Cg to be connected to the second reference voltage signal terminal VREFP or the third reference voltage signal terminal VREFN through the corresponding capacitance switches SW to complete setting, meanwhile, the seven-bit thermometer code output by the DWA module 40 is further output to the first preset logic circuit 50 after being inverted, and the first preset logic circuit 50 controls the second poles of Ch to Cn to be connected to the second reference voltage signal terminal VREFP or the third reference voltage signal terminal VREFN through the corresponding capacitance switches SW to complete setting. It should be appreciated that because the set signals delivered by the first preset logic 50 to Ca-Cg and Ch-Cn are opposite, the second poles of Ca-Cg and Ch-Cn are connected by different VREFP and VREFN, i.e., the set results are different.
In addition, it should be noted that, in this embodiment, the quantized and latched three-bit quantization code outputs 7-bit thermometer codes through the DWA module 40, where the 7-bit thermometer codes sequentially and circularly select 7 capacitor units Ca to Cg/Ch to Cn, so as to implement randomization processing on nonlinear errors, and the DWA module can better suppress harmonic distortion caused by mismatch of auxiliary DACs.
With continued reference to FIG. 5, whenOn entering the rising edge of the square wave, the integration phase starts, the third sampling switch S3 and the fifth sampling switch S5 are closed, +.>And ending the integration phase when the falling edge of the square wave is entered, and obtaining a first integration voltage at the first pole of the third sub-capacitor Cint1 and a second integration voltage at the first pole of the sixth sub-capacitor Cint 2. It can be understood that at this stage, the third sub-capacitor Cint1 performs charge sharing with the capacitor arrays Ca to Cg and C5 to C10, and the sixth sub-capacitor Cint2 performs charge sharing with the capacitor arrays Ch to Cn and C12 to C17, thereby completing integration.
Illustratively, in the present embodiment, the capacitance values of the sum of the capacitances Ca to Cg and C5 to C11, the capacitance values of the third sub-capacitance Cint1 and the fourth sub-capacitance Cint ' are equal, the capacitance values of the sum of the capacitances Ch to Cn and C12 to C17, the capacitance values of the sixth sub-capacitance Cint2 and the seventh sub-capacitance Cint2' are equal, and it is obvious that this design manner attenuates the first pole voltages of Ca to Cg and C5 to C11 in the first module 10 and the first pole voltages of Ch to Cn and C12 to C18 in the second module 10' by 1/2, which is equivalent to adding one redundancy bit.
After integration, the first input end of the first comparator 20 is input with voltage values of first poles Ca-Cg and C5-C11, the second input end of the first comparator 20 is input with voltage values of first poles Ch-Cn and C12-C18, the first comparator 20 compares the first integrated voltage with the second integrated voltage, the comparison result is input into the first preset logic circuit 50, seven-bit quantized codes are obtained, the seven-bit quantized codes are quantized results of C5-C11 and C12-C18, and the three-bit quantized codes are added with the seven-bit quantized codes, so that an analog-digital conversion result of an input signal is obtained.
In the second quantization stage, the first preset logic 50 transmits the opposite set signal to the capacitor switch SW connected to the second poles of C5 and C12 according to the comparison result, where C5 is connected to VREFP or VREFN, C12 is connected to VREFN or VREFP, and C5 and C12 are connected to different voltages, so that the set result is different. After setting of C5 and C12 is finished, the voltages of the nodes N2 and N3 are transmitted to the first comparator 301, the first comparator 301 continues to compare, and thus the cyclic operation finishes setting of C5 to C11 and C12 to C18, and finally seven-bit quantization codes are obtained.
It should be appreciated that the analog-to-digital conversion method provided by the present invention further comprises an amplification stage. In order to implement noise shaping in the auxiliary ADC module 30, after the seven-bit quantization code is converted in the second quantization stage, the first integrated voltage stored in the third sub-capacitor Cint1 is amplified by G times and then stored in the second sub-capacitor Ccap3, the second integrated voltage stored in the sixth sub-capacitor Cint2 is amplified by G times and then stored in the fifth sub-capacitor Ccap4,after the signal is '1', the first pole of the second sub-capacitor Ccap3 is connected with the node N1, the second pole is connected with the first input end of the second comparator, the summation of the voltage stored on the second sub-capacitor Ccap3 and the residual voltages on the first poles of C1-C4 is realized, the first pole of the fifth sub-capacitor Ccap4 is connected with the node N4, and the second pole is connected with the second input end of the second comparator, so that the summation of the voltage stored on the fifth sub-capacitor Ccap4 and the residual voltages on the first poles of C19-C22 is realized.
The summing operation can be realized by adopting a serial connection method in the embodiment, the first sub-capacitor Ccap1 and the eighth sub-capacitor Ccap2 alternately work in a ping-pong structure, and for the N-th period, whenWhen the signal is "1", the operational amplifier 60 amplifies the first integrated voltage by G times, and after the amplification is completed, the amplified voltage value is stored in the first sub-capacitor cca 1. In the n+1th period, the first sub-capacitor Ccap1 and the eighth sub-capacitorCcap2 alternates, and the voltages of the upper polar plates of C1-C4 are (Gcint+Vref), wherein Gvint represents the first integrated voltage amplified by G times, vref represents the voltages of the upper polar plates of Ca-Cg and C5-C11,after the signal is "1", the auxiliary ADC module 30 starts quantization, obtains a digital output through comparison of the second comparator 301, and generates a three-bit quantization code, and Ccap2 is a feedback capacitor of the op amp, stores the amplified voltage value, and thus alternately works in the upper three bits to realize noise shaping.
To more clearly illustrate the working principle, fig. 6 is a diagram of a capacitor array mismatch error shaping signal provided by an embodiment of the present invention, and it can be understood that the capacitor arrays refer to C1 to C4 and C19 to C22 and Ca to C11 and Ch to C18. Referring to fig. 6, after the quantization of the high-order auxiliary SAR ADC (C1-C4, C19-C22) is completed, the quantized result is transferred to the first preset logic circuit, and the conversion margin is obtained at the upper plates of Ca-Cg, C5-C11, ch-Ca, and C12-C18, which includes distortion errors from DAC nonlinearity and mismatch, which deteriorates the linearity of the analog-to-digital converter 100. In order to reduce the influence of capacitance mismatch and nonlinearity, the analog-to-digital conversion method provided by the invention adopts an NS SAR ADC with an N-0MASH architecture. Wherein, ca-Cg and Ch-Cn adopt DWA algorithm to realize mismatch error shaping, and can be obtained according to the Meissen formula:
D(z)＝V IN (z)+(1-z -1 )E 1 (z)+[1-H 1 (z)]·[Δ·Q 1 (z)+Q 2 (z)+E 2 (z)]
In the formula, delta represents gain error, E1 is mismatch error of C1-C4 and C19-C22, and mismatch error of E2 bits C5-C11 and C12-C18, and it can be seen that the capacitor array mismatch error shaping technology can simultaneously shape capacitor mismatch error, gain error and second-stage quantization noise, and the limit of mismatch error on high precision is broken through.
The analog-to-digital conversion method is further described below through simulation experiments.
Specifically, a 65nm standard CMOS process is adopted for circuit design, and an analog-to-digital converter works at 1.2V electricityUnder the source voltage, the highest sampling frequency is 2MS/s, the amplitude of the input signal is 2.16V Vpp, wherein the input signal comprises a first signal input end V IP First and second signal input terminals V of (a) IN Is provided for the second input signal of (a). Fig. 7 is a diagram of simulation results of an analog-to-digital conversion method according to an embodiment of the present invention. When the input signal frequency is 854.5Hz, the ADC frequency spectrum obtained by testing is shown in FIG. 7, the SAR ADC signal harmonic noise (SNDR) is 115dB, the spurious noise free dynamic range (SFDR) is 78dB, and the effective precision is 18.8 bits. It can be seen that after mismatch error shaping, SFDR is improved by 40dB, and the invention achieves a great improvement in linearity by reducing mismatch of the capacitor array and reducing quantization noise.
According to the embodiment, the beneficial effects of the invention are as follows:
the invention provides an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end, and because the analog-to-digital converter adopts a MASH 1-0 shaping scheme, the second poles of Ca-Cg and C5-C11, namely the lower pole plates of Ca-Cg and C5-C11, can be sampled when the analog-to-digital converter is used for carrying out analog-to-digital conversion, thereby avoiding the influence of variable parasitic capacitance on an upper pole plate when the upper pole plate is sampled and effectively relieving the influence of variable parasitic capacitance of the upper pole plate on linearity.
In addition, the analog-to-digital converter further comprises a DWA module, three capacitors corresponding to the upper three bits in the correlation technology are converted into Ca-Cg 7 capacitors by combining the capacitor lower plate sampling result in the first module and the high bit data weighted average algorithm, so that high three-bit noise shaping is achieved, the MASH 1-0 shaping scheme can carry out first-order shaping on mismatch errors of the low-bit DAC, namely C5-C11, and the mismatch errors of the whole main DAC array are all shaped in the first order, so that the circuit complexity is simplified.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (8)

1. An analog-to-digital converter, comprising: the device comprises a first module, a first comparator, an auxiliary ADC module, a DWA module, a first preset logic circuit, a first signal input end, a second signal input end, a first reference voltage signal end, a second reference voltage signal end and a third reference voltage signal end; wherein,
the auxiliary ADC module comprises a first capacitor, a first sub-capacitor, a second comparator, a second preset logic circuit and a first node, wherein the first capacitor comprises: the first poles of C1-C4 and C1-C4 are connected with the first node, the second pole is connected with one of the second signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end; the second comparator comprises a first input end and an output end, a first pole of the first sub-capacitor is connected with the first node, a second pole of the first sub-capacitor is connected with the first input end of the second comparator, the output end of the second comparator is connected with the input end of the second preset logic circuit, the output end of the second preset logic circuit is connected with the input end of the DWA module, and the output end of the DWA module is connected with the first preset logic circuit;
The first module comprises a second type capacitor, a third type capacitor and a second node, wherein the second type capacitor comprises: ca to Cg, the third type of capacitance includes: the first poles of C5-C11, ca-Cg and C5-C11 are connected with the second node, and the second pole is connected with one of the second signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end;
the first comparator comprises a first input end and an output end, wherein the first input end of the first comparator is connected with the second node, and the output end of the first comparator is connected with the first preset logic circuit;
the device also comprises a first sampling switch and a second sampling switch;
in the auxiliary ADC module, a first pole of C1-C4 is connected with the first reference voltage signal end through the first sampling switch;
in the first module, ca-Cg and C5-C11 are connected with the first reference voltage signal end through the second sampling switch;
the circuit also comprises an operational amplifier, a second sub-capacitor, a third sub-capacitor, a fourth sub-capacitor and a third sampling switch;
the operational amplifier comprises a first input end and a first output end, wherein the first input end of the operational amplifier is connected to the second node, the first output end of the operational amplifier is connected with the first pole of the fourth sub-capacitor, and the second pole of the fourth sub-capacitor is grounded;
The first pole of the second sub-capacitor is connected with the first input end of the operational amplifier, and the second pole of the second sub-capacitor is connected with the output end of the operational amplifier;
the first pole of the third sub-capacitor is connected to the second node and the second pole is grounded through the third sampling switch.
2. The analog-to-digital converter of claim 1, further comprising a second module comprising fourth and fifth types of capacitances and a third node;
the fourth type of capacitance includes: ch to Cn, the fifth type of capacitance includes: the first poles of C12-C18, ch-Cn and C12-C18 are connected with the third node, and the second pole is connected with one of the first signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end.
3. The analog-to-digital converter of claim 2, further comprising a fourth sampling switch, wherein in the second module, the first poles of Ch-Cn and C12-C18 are connected to the first reference voltage signal terminal via the fourth sampling switch.
4. The analog-to-digital converter of claim 3, further comprising a fifth sub-capacitance, a sixth sub-capacitance, a seventh sub-capacitance, and a fifth sampling switch, the operational amplifier further comprising a second input and a second output;
The second input end of the operational amplifier is connected to the third node, the second output end of the operational amplifier is connected with the first pole of the seventh sub-capacitor, and the second pole of the seventh sub-capacitor is grounded;
the first pole of the fifth sub-capacitor is connected with the second input end of the operational amplifier, and the second pole of the fifth sub-capacitor is connected with the second output end of the operational amplifier;
the first pole of the sixth sub-capacitor is connected to the third node and the second pole is grounded through the fifth sampling switch.
5. The analog-to-digital converter of claim 1, wherein the auxiliary ADC module further comprises a sixth type of capacitance, an eighth sub-capacitance, and a sixth node, the sixth type of capacitance comprising: the first poles of C19-C22 are connected with the sixth node, and the second poles are connected with one of the first signal input end, the first reference voltage signal end, the second reference voltage signal end or the third reference voltage signal end;
the second comparator further comprises a second input end, a first pole of the eighth sub-capacitor is connected with the sixth node, and a second pole of the eighth sub-capacitor is connected with the second input end of the second comparator.
6. The analog-to-digital converter of claim 5, further comprising a sixth sampling switch;
In the auxiliary ADC module, a first pole of C19-C22 is connected with the first reference voltage signal end through the sixth sampling switch.
7. An analog-to-digital conversion method applied to the analog-to-digital converter of any one of claims 1 to 6, comprising: a sampling phase, a first quantization phase, an integration phase and a second quantization phase; wherein,
in the sampling stage, the second poles of Ca-Cg, C1-C4 and C5-C11 are connected with the second signal input end, the second poles of Ch-Cn, C19-C22 and C12-C18 are connected with the first signal input end, and the first sampling switch, the second sampling switch, the fourth sampling switch and the sixth sampling switch are all closed so that Ca-Cg and C5-C11 in the first module sample the second input signal, ch-Cn and C12-C18 in the second module sample the first input signal, and C1-C4 in the auxiliary ADC module sample the second input signal and C19-C21 sample the first input signal; the first input signal and the second input signal are analog signals, and the voltage of the first input signal is different from that of the second input signal;
in a first quantization stage, a second comparator compares the sampling result of the second input signal by C1-C4 and the sampling result of the first input signal by C19-C21, then inputs the comparison result into a second preset logic circuit to obtain a three-bit quantization code, inputs the three-bit quantization code into the DWA module, inputs the seven-bit thermometer code obtained by conversion into a first preset logic circuit, and enables the first preset logic circuit to set Ca-Cg and Ch-Cn according to the seven-bit thermometer code;
In the integration stage, the third sampling switch and the fifth sampling switch are closed to obtain a first integrated voltage at the first pole of the third sub-capacitor and a second integrated voltage at the first pole of the sixth sub-capacitor;
in the second quantization stage, the first comparator compares the first integrated voltage with the second integrated voltage, inputs the comparison result to the first preset logic circuit, so that the first preset logic circuit sets C5-C11 and C12-C18 to obtain seven-bit quantization codes, and adds the three-bit quantization codes and the seven-bit quantization codes to obtain an analog-to-digital conversion result of an input signal.
8. The analog-to-digital conversion method of claim 7, wherein the sum of the capacitances of Ca to Cg and C5 to C11, the third sub-capacitance and the fourth sub-capacitance are equal, the sum of the capacitances of Ch to Cn and C12 to C17, and the sixth sub-capacitance and the seventh sub-capacitance are equal.
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