CN113722262A

CN113722262A - Inter-chip serial bridging method for on-chip high-bandwidth bus

Info

Publication number: CN113722262A
Application number: CN202111180073.XA
Authority: CN
Inventors: 刘根贤; 廖孟安; 瞿波
Original assignee: Hunan Aerospace Economic Development Co ltd
Current assignee: Hunan Aerospace Economic Development Co ltd
Priority date: 2021-10-11
Filing date: 2021-10-11
Publication date: 2021-11-30

Abstract

An inter-chip serial bridging method for an on-chip high bandwidth bus, comprising the steps of: (1) utilizing a phase-locked loop technology to carry out frequency multiplication on a bus synchronous clock; (2) serializing various signals of the internal bus by using a frequency multiplication clock; (3) transmitting serial addresses and control signals at high speed outside the chip, and starting a handshake protocol for reading or writing; (4) the read or write handshake is successful, a continuous data transmission stage is entered, and the data is continuously transmitted at high speed outside the chip; (5) if the transmission in the step (4) of the continuous data transmission stage is normally finished, restoring the self functional attributes of the state, control and address signals, and preparing to establish the next round of reading or writing operation transmission; (6) and (5) if the continuous data transmission stage (4) is abnormal, returning to the step (3). The invention can reduce the quantity of the connection between the sheets to the range of easy realization; the on-chip bus can be serialized and sent at high speed, the serial data is received at the expansion end, and the bus is deserialized and restored, so that the design risk is reduced, and the cost of a single-chip device is reduced.

Description

Inter-chip serial bridging method for on-chip high-bandwidth bus

Technical Field

The invention relates to an inter-chip serial bridging method, in particular to an inter-chip serial bridging method of an on-chip high-bandwidth bus.

Background

The on-chip bus is the most common technical means for realizing the connection of the IP cores in the SoC, and realizes data communication between the IP cores in a bus mode. An on-chip bus specification generally needs to define the relationships of driving, timing, strategy and the like in the processes of initialization, arbitration, request transmission, response, sending, receiving and the like among various modules. On-chip buses and standardization, the industry has also developed a number of mature IP cores based on standard on-chip buses.

The prior art has the following disadvantages: when a plurality of devices are designed to work in a matched mode, the number of connecting lines of high-performance buses in the chip is large, the buses in the chip cannot be directly expanded out of the chip, and due to the fact that the number of pins for interconnection between the chips is limited, expansion of the buses in the chip towards the outside of the chip is difficult to achieve.

Disclosure of Invention

The technical problem to be solved by the present invention is to overcome the above-mentioned defects in the prior art, and to provide an inter-chip serial bridging method for an on-chip high bandwidth bus, which can reduce the number of inter-chip connections and realize on-chip bus expansion.

The technical scheme adopted by the invention for solving the technical problems is as follows: an inter-chip serial bridging method for an on-chip high bandwidth bus, comprising the steps of:

(1) utilizing a phase-locked loop technology to carry out frequency multiplication on a bus synchronous clock; the phase-locked loop controls the frequency and the phase of an internal oscillation signal of the loop by using an externally input reference signal, and a stable and high-frequency clock signal can be realized by using the phase-locked loop; frequency multiplication means that the frequency of a clock signal is multiplied by 8 times, for example, an input clock is 10MHz, and a frequency multiplication output clock is 80 MHz; the bus operates uniformly according to the pace of the clock signal and is called a synchronous bus. The bus synchronous clock, the on-chip bus is synchronous in clock, when the on-chip bus works, all signals on the bus are coordinated and acted in unison under the drive of the clock signal, and the signal is called synchronous clock;

(2) serializing various signals of the internal bus by using a frequency multiplication clock; the serial transmission signals can be output as signals of address, control, state, data and the like after being paralleled, only address, control and state signals are needed to be transmitted in a protocol handshaking stage according to the change of a bus protocol, and only data needs to be transmitted in a data transmission stage after handshaking;

(3) transmitting serial addresses and control signals at high speed outside the chip, and starting a handshake protocol for reading or writing;

(4) the read or write handshake is successful, a continuous data transmission stage is entered, and the data is continuously transmitted at high speed outside the chip;

(5) if the transmission in the step (4) of the continuous data transmission stage is normally finished, restoring the self functional attributes of the state, control and address signals, and preparing to establish the next round of reading or writing operation transmission;

(6) and (5) if the continuous data transmission stage (4) is abnormal, returning to the step (3).

The invention has the advantages that the quantity of inter-chip connections can be reduced to the range easy to realize, and the expansion of the on-chip bus can be realized by only 6 signals at least; the on-chip bus can be serialized and sent at high speed, the serial data received by the expansion end is deserialized and restored to the bus, so that a complex device can be split into a plurality of device combinations, the design risk is reduced, and the cost of a single-chip device is reduced; the internal bus contains signals of various states, control, addresses, data and the like, and not only needs to solve the serialized transmission of the signals, but also needs to solve a bus timing protocol to complete the reading process and the writing process of specific address data.

Drawings

FIG. l is a schematic diagram of on-chip bus serialization of the present invention;

FIG. 2 is a diagram of on-chip bus serial data transfer according to the present invention;

FIG. 3 is a schematic diagram of the serial transmission and recovery of control, status, address and data of the present invention;

FIG. 4 is an exemplary diagram of internal bus signals of the present invention;

fig. 5 is a bus extension internal block diagram of the present invention.

Detailed Description

The following examples are given to further illustrate the embodiments of the present invention:

referring to fig. 1-5, embodiments of the present invention include the following steps:

(2) serializing various signals of the internal bus by using a frequency multiplication clock; the serial transmission signals can be output as signals of address, control, state, data and the like after being paralleled, only address, control and state signals are needed to be transmitted in a protocol handshaking stage according to the change of a bus protocol, and only data needs to be transmitted in a data transmission stage after handshaking; as shown in fig. 4 and 5, the internal interface of the bus serializing module includes clock frequency multiplication, signal serialization and time control logic unit;

(5) if the transmission in the step (4) of the continuous data transmission stage is normally finished, restoring the self functional attributes of the state, control and address signals, and preparing to establish the next round of reading or writing operation transmission; as shown in fig. 2 and 3, after the reading and writing are established, a continuous data transmission stage is entered, and all signals are used for data signal transmission; if the transmission is normally finished in the continuous data transmission stage step, the state, control and address data signals restore the self functional attributes and prepare to establish the next round of transmission.

Those not described in detail in the specification are well within the skill of the art.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the technical principle of the present invention, and these modifications and decorations should also be regarded as being within the protection scope of the present invention.

Claims

1. An inter-chip serial bridging method for an on-chip high bandwidth bus, comprising the steps of:

utilizing a phase-locked loop technology to carry out frequency multiplication on a bus synchronous clock;

serializing various signals of the internal bus by using a frequency multiplication clock;

transmitting serial addresses and control signals at high speed outside the chip, and starting a handshake protocol for reading or writing;

the read or write handshake is successful, a continuous data transmission stage is entered, and the data is continuously transmitted at high speed outside the chip;

if the transmission in the step (4) of the continuous data transmission stage is normally finished, restoring the self functional attributes of the state, control and address signals, and preparing to establish the next round of reading or writing operation transmission;

and (5) if the continuous data transmission stage (4) is abnormal, returning to the step (3).