CN101296229A - Device for implementing dynamic time-slot TDMA distribution - Google Patents
Device for implementing dynamic time-slot TDMA distribution Download PDFInfo
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Abstract
The invention relates to a realization device of time slot allocation TDMA, in particular to a realization device of the dynamic time slot allocation TDMA, aiming at solving the problem of low efficiency of the existing coding system. A dynamic time slot scheduling method is adopted in a TDMA communication system. The way of sending from primary ends to secondary ends is that the primary ends dispatch and broadcast the data to each secondary end according to the priority level and the length of data required by the secondary end equipment. The time slot scheduling of upstream data is that: the time of uploading time slot of the frame of the secondary ends is arranged by the primary ends in a unified way according to the priority level uploaded on the previous frame of the secondary ends and the length of the data to be uploaded. The secondary ends arrange proper data to be uploaded according to the size of time slot that the primary ends send to the secondary ends. The device of the invention can be widely applied to an EoC system, a wireless communication system and an optical fiber analog communication system.
Description
One, technical field
Patent of the present invention relates to a kind of time-slot TDMA distribution implement device, particularly a kind of dynamic time-slot TDMA distribution implement device.
Two, background technology
Several below high-speed wideband communication prior art has on coaxial cable:
Cable Modem technology: based on the CMTS system of DOCSIS1.1, DOCSIS2.0, DOCSIS 3.0 standards in the North America, Europe is extensive use of, but China " not acclimatized ".Reason is that the electric equipment great majority of China are not proved through electromagnetic compatibility, even the product through the Electro Magnetic Compatibility authentication also exceeds standard greatly for " saving cost " its product electromagnetic radiation when producing, the cable tv coax net is a tree network, meeting influx noise (funneling effect), make noise flood normal signal of communication, effective bandwidth is reduced greatly, perhaps can't communicate by letter at all.
The Moca technology: multimedia over Coax Alliance (Multimedia over Coax Alliance), by Panasonic, Conexant; Entropic Communications provides the Moca chipset now, and domestic have some users to use the MOCA technology, inserts but this technology only is applicable to family multi-media, is not suitable for multi-user's Access Network.But in bench-scale testing, find a large amount of problem of Moca: (1) can not transmit (frequency 900-1500MHz) at a distance, and the loss on cable and splitter of this frequency is big; (2) because the frequency that they use is identical with mobile phone frequency, the proper communication of interference handset; (3) discomfort is fit to do the extensive Access Network of point-to-multipoint.
The WLAN technology: the WLAN wireless network adopts agreements such as 802.11a/b/g/n, adopt the wireless work of carrying out in the former 2.4-2.483GHz of the being used for frequency range, because the signal of 2.4GHz, frequency is too high, be not suitable in transmission over coaxial cable, usually adopt the method for frequency reducing to realize, now domestic Liuhe-Wantong and French Thomson company use the frequency that its tranmitting frequency mixes down to more than the 860MHz on coaxial cable.Because WLAN adopts the CSMA/CA agreement, be suitable for the few family of user side and use, and be not suitable for the Access Network of multi-user concurrent, speed sharply descends when multi-user concurrent is communicated by letter, and can't use in the system that large-scale user inserts.
Solve the existing low problem of one-to-many communication efficiency rate.
Three, summary of the invention
The problem that solves:
Disturbing the problem that normally to use on the big network in order to solve existing C MTS technology; Solve technology such as Moca, WLAN and can not be applied to the medium problem of system that large-scale consumer inserts.Solve the problem that prior art can not realize the integration of three networks.Solve the existing inefficient problem of coded system.
Technical scheme:
" dynamic time-slot TDMA distribution implement device " is made up of local side apparatus, ustomer premises access equipment and network management system, adopt TDMA (timesharing multiple access) mode to realize that the multi-user inserts at MAC, can realize that HFC (coaxial cable fiber mix net) network the whole network under the light station covers, finish last 1000 meters users' broadband access, safety certification, safety management, link to each other with the core broadband networks by EPON, GPON or fiber optical transceiver, cable TV subscriber's broadband access is finished in collaborative work, and two-way television, IPTV etc. realize the integration of three networks.
In the two-way communication that realizes network data on the channel of coaxial cable (CATV) broadband analog signal 2-30MHz or on the frequency of 862MHz-2.5GHz, the program request signaling of leaving language phone (VoIP) and two-way interaction TV for that QoS priority is the highest in the network data is used, and remaining uses for the computer broadband networks.Realize broadband access network, IPTV.Keep to cable television network on the frequency range of 47MHz-862MHz and use, modulation anolog TV signals, digital television signal and IPQAM TV signal.Realize by the high-pass and low-pass filter frequency division, thereby realize that broadband networks, telephone network, the television network integration of three networks are in the coaxial cable net.
By local side apparatus ethernet signal is modulated to the analog signal of OFDM, again the signal of modulation is amplified the back and transmit by coaxial cable.Ustomer premises access equipment is finished demodulation, and the analog signal that local side is sended over is reduced to ethernet signal.
Be specially: upward signal is from the signal of the Ethernet PHY input of user side, be converted to the OFDM digital modulation signals through the SOC chip signal, be converted to the OFDM analog signal through AD9865 D/A, after OP2674 amplifies, online by sending to cable TV behind the filter filtering, send on the local side apparatus through cable television network, local side apparatus is with the signal that receives, being sent to AD9865 behind filter filtering carries out the A/D conversion and is converted to data-signal, be tuned as ethernet signal through separating of local side apparatus, thereby realize data upload.Downstream signal identical with upward signal, only direction is opposite.
The local side modulation:
Ethernet data is input to the MII interface of the MAC of SOC chip through PHY chip (IP101), through the AMBA bus, directly be sent to dynamic reconfigurable accelerating engine → by dma mode through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal data are abandoned, if data are legal → the MAC layer: according to the priority of data, arrange time slot and bandwidth by the TDMA agreement, if the time slot that now is not this user side sends the back then buffer memory wait time slot arrives, if the time slot of this user side transmission → PHY layer immediately then: realize range finding, burst transfer, forward error correction, channel estimating, power control → coding layer: realize OFDM, QAM, the QPSK modulation reaches and the AD9865 interface, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize that FEEDBACK CONTROL → data to the AD9865 chip are sent to AD9865 and form analogue data output → process OPA2674 through D/A and amplify, the modulated analog signal that forms 2-30MHz transmits on coaxial cable, delivers to each ustomer premises access equipment.
The local side demodulation:
The analog signal that sends from user side → be sent to AD9865 to be converted to data output → coding layer through A/D: with the Data Format Transform of AD9865 is 32bit data lattice → PHY layer: realize range finding, burst transfer, forward error correction, channel estimating, power control, the control AD9865 reception data of appropriate state, make the error rate minimum → the MAC layer: with the reduction of data that receives is original data → through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal that data are abandoned, if data legal → data send to Ethernet data through PHY chip (IP101) by AMBA bus dma mode.
The ARM926EJ processor, the ARM926EJ processor in the SOC chip is responsible for handling the management data in the native system, is responsible for dynamic-configuration dynamically programmable circuit.
The data that the data medium priority is the highest are used for the signaling-information of voice signal and video on demand.
The modulation of ustomer premises access equipment:
Ethernet data is input to the MII interface of the MAC of SOC chip through PHY chip (IP101), through the AMBA bus, directly be sent to dynamic reconfigurable accelerating engine → by dma mode through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal data are abandoned, if data are legal → and the MAC layer: wait for that local side apparatus arranges time slot and bandwidth, if uploading the time slot that is not this user side now sends the back then buffer memory wait time slot arrives, if the time slot of this user side transmission → PHY layer immediately then: realize range finding, burst transfer, forward error correction, channel estimating, power control, control AD9865 with suitable parameter with data transmissions → coding layer: realization OFDM, QAM, the QPSK modulation reaches and the AD9865 interface, the data format of AD98 65 and 32 bit data forms of SOC inside are changed in realization, and realize that FEEDBACK CONTROL → data to the AD9865 chip are sent to AD9865 and form analogue data output → process OPA2674 through D/A and amplify, the modulation signal that forms 2-30MHz send transmission at coaxial cable, delivers to local side apparatus.
The user side demodulation:
The analog signal that sends from local side → be sent to AD9865 to form data output → coding layer: realize that OFDM, QAM, QPSK demodulation reach and AD986 5 interfaces through A/D, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize FEEDBACK CONTROL → PHY layer: realize range finding, burst transfer, forward error correction, channel estimating, power control to the AD9865 chip, thereby the control AD9865 reception data → MAC layer of appropriate state: if the data of this user side then are reduced to original data; Data if not this user side, then it is abandoned → through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal that data are abandoned, if data legal → data send to Ethernet data through PHY chip (IP101) by AMBA bus dma mode.
Downlink data comprises: downlink signaling and downlink data two parts.Downlink signaling comprises synchronous head (being used for the synchronous of master-slave equipment), issue the data user and hold address (MAC Address number and the serial number that distributes), forward error correction, time slot demand, the priority that local side proposes according to all ustomer premises access equipments will be sought unification to dispatch to arbitrate to issue and be allowed this user side to upload the length of time slot; Ustomer premises access equipment sends data according to the time slot that local side issues to local side.
Upstream data comprises: up signaling, upstream data.Up signaling comprises: user side address (serial number that this user side is distributed with MAC Address and local side), next frame need be uploaded the length of payload user data, the priority of next frame data (annotate: the demand of this frame, local side next frame issue the Shi Caihui response), there are the length of this frame numeric data code that order is brought according to local side, payload user data etc. in the back again.
The login of ustomer premises access equipment utilizes the CSMA/CA agreement to realize.In each time slot of uploading and descending to pass, there is one section very little time slot to adopt the CSMA/CA mode.The manner only is used for local side apparatus and ustomer premises access equipment is consulted, and ustomer premises access equipment is registered on the local side apparatus, finishes the registration of new equipment.
Local side is distributed to the time slot that user side uploads two kinds of method for expressing: (1) time slot is the integral multiple of certain unit time slot; (2) time slot is an arbitrary value.
Beneficial effect:
Should be mainly used in realizing in the HFC cable TV network with the scheme target product: broadband access network, interactive TV program request, IPTV, private network access etc.Dwindle the gap with international technology, by " made in China " to " China creates "; Utilization is modulated, demodulation accelerating engine system power dissipation is low, saves resource, saves the energy, realization " green internet "; Utilization is modulated, demodulation accelerating engine system speed is fast, the system availability height, the communication efficiency of raising system, realize the higher ratio of performance to price, reduce cost, make the poor also can go up to such an extent that play the Internet, afford to use video on demand, promote the harmonious development of society, dwindle " digital divide ", development promotes social harmony.
Four, description of drawings
Fig. 1 group network system block diagram
Fig. 2 local side apparatus, ustomer premises access equipment theory diagram
Fig. 3 SOC chip internal theory diagram
Fig. 4 modulation, demodulation hierarchy schematic diagram
Fig. 5 need distribute the TDMA processed frame structure of time slot
Fig. 6 CSMA/CA handshake
Five, embodiment
Below in conjunction with accompanying drawing embodiments of the present invention are described in detail:
Constitute coder/decoder based on dynamically programmable circuit accelerating engine; Constitute PHY, MAC layer accelerator based on dynamically programmable circuit accelerating engine; Constitute network intrusions early warning and control based on dynamically programmable circuit accelerating engine.Thereby low-power consumption, low cost, the high efficiency of the system of realization.
Large scale network invasion early warning, control: utilize the dynamically programmable circuit to form credibleization accelerating engine, realize coaxial cable wideband data network invasion early warning, control.
The integration of three networks: the accelerating engine that utilizes the dynamic reconfigurable circuit to constitute, realize voice communication, network data transmission, utilize frequency division to realize voice communication, network data and Digital Television, simulated television coexistence, thereby realize three-network integration system based on the CABLE cable.
Operation principle: in the two-way communication that realizes network data on the channel of coaxial cable (CATV) broadband analog signal 2-30MHz or on the frequency of 862MHz-2.5GHz, the program request signaling of leaving language phone (VoIP) and two-way interaction TV for that QoS priority is the highest in the network data is used, and remaining uses for the computer broadband networks.Realize broadband access network, IPTV.Keep to cable television network on the frequency range of 47MHz-862MHz and use, modulation anolog TV signals, digital television signal and IPQAM TV signal.Realize by the high-pass and low-pass filter frequency division, thereby realize that broadband networks, telephone network, the television network integration of three networks are in the coaxial cable net.
System is made up of local side apparatus and subscriber equipment, in coaxial cable, utilize the OFDM OFDM, utilize QAM and QPSK mode modulating data on the subcarrier of OFDM, thereby realize high efficiency digital speech, network broadband data high-speed transfer on coaxial cable.
Be modulated to QAM1024, the QAM256 on the OFDM subcarrier, the encoding and decoding software of QAM16, QPSK, utilize the accelerating engine of dynamically programmable circuit to realize; Utilize the accelerating engine of dynamically programmable circuit to realize the network data enciphering/deciphering, realize network intrusions early warning and control; Utilize the accelerating engine of dynamically programmable circuit to realize MAC layer, PHY layer protocol etc.
Local side apparatus is installed at light station at cable TV coaxial fiber mix net (HFC), and ustomer premises access equipment is installed in user family, and a local side apparatus can connect 64 ustomer premises access equipments.
This project system is made of local side apparatus, ustomer premises access equipment, bridger, webmastering software realizes that last 1000 meters bilateral network inserts, and realizes cable television network, telephone network, the computer communication network integration of three networks.VoIP mode (do not relate to VoIP in this project, only stayed the highest network channel of priority) is adopted in voice communication.
1, preferred embodiment 1:
This project system is made up of local side apparatus, subscriber equipment and jumper.Local side apparatus (Master), ustomer premises access equipment (Slave) are formed by connecting by wired TV amplifier, distributor, splitter, coaxial cable.
1) local side apparatus:
A local side apparatus can connect 64 subscriber equipmenies.Local side apparatus is modulated to the OFDM analog signal with the Ethernet supplied with digital signal, use TDMA (time division multiple access) agreement, pass through coaxial cable, realize the one-to-many data communication, data are sent to subscriber equipment, and subscriber equipment will be demodulated into digital signal from the ofdm signal that coaxial cable sends, if data are to this user, this subscriber equipment is reduced into original data with demodulated data signal, and the Ethernet that outputs to the user uses for the user.
The Ethernet data of same user's input is modulated to the OFDM analog signal through subscriber equipment when taking turns to the time slot of this user side, will be sent to local side by coaxial cable, and local side is demodulated into legacy data with the OFDM analog signal, by the Ethernet output of local side.Thereby realized two-way communication.
2) ustomer premises access equipment:
The chip of user side and local side apparatus chip are identical, just the different pattern of work.Block diagram as shown in the figure.The modulating/demodulating of ustomer premises access equipment and the modulating/demodulating of local side apparatus are similar, and the local side apparatus mode of operation is an active mode, and the mode of operation of ustomer premises access equipment is from mode.
3) jumper:
Effect: it is straight-through that modulation, the demodulated analog signal of the local side apparatus of 2-30MHz and ustomer premises access equipment are skipped TV signal amplifiers, and the signal of 47-860MHz still amplifies through TV signal amplifiers.
The signal jumper is fairly simple, it is exactly a two high-pass and low-pass filter, first high-pass and low-pass filter is 2-30MHz and 47MHz-862MHz two-way with the Signal Separation of 2-860MHz earlier, the TV signal of 47-862MHz is exported to wired TV amplifier and is amplified, and the signal of 2-30MHz is directly connected to the input port of the 2-30MHz of second high-pass and low-pass filter; 47MHz-860MHz cable TV signal after the amplification is connected to the input port of the 47-862MHz of second high-pass and low-pass filter, exports 2-862MHz by one tunnel full rate signal that is mixed into again of second high-pass and low-pass filter.
Be illustrated in figure 1 as the system architecture schematic diagram, 101 is the local side modulator-demodulator, and 102 is that bridger, 103 is that user side modulator-demodulator, 104 is that another one user side modulator-demodulator, 105 is that TV signal amplifiers, 106 is that catv distributor, 107 is that catv distributor, 108 CATV set-top-box, 109 are that television set, 110 is the PC computer.
2, preferred embodiment 2:
The network management software adopts snmp protocol, supports SNMP V1.0/V2.0/V3.0 agreement.Finish the design of the integration of three networks network management software, realize network intrusions early warning and control.For unification of three nets provides perfect network management function.Its embedded SNMP adopts the NET SNMP source code of open source code to revise and realizes.
Webmastering software has following surface function:
1) traffic statistics function: the flow to the uplink and downlink of each user side is added up;
2) the IGMP agreement realizes that video multicast is used for time-moving television, video request program;
3) the limited subscriber end connects the platform number of computer: be limited in the platform number that connects PC under each user side, the protection benefits of operators;
4) broadcast packet, unknown bag inhibit feature: broadcast packet or other attack packets are suppressed, avoid of the influence of these useless data to normal data communication;
5) preferential, the preferentially setting of time-delay of speed: it is preferential to be set to speed in the demanding place of data rate; It is preferential to be set to time-delay to the little place of data delay requirement;
6) QOS realizes: the professional prioritised transmission that is provided with and guarantees data such as phone, program request order of isolating, thus realize the integration of three networks; IEEE 802.1p is the traffic priority control criterion, is operated in media interviews control (MAC) sublayer.It makes Layer 2 switch that traffic prioritization and dynamic multicast filtering services can be provided.IEEE 802.1p standard also provides the flux of multicast filtering function, does not exceed second layer switching network scope to guarantee this flow.IEEE 802.1p protocol header comprises 3 precedence fields, and this field support is grouped into various flow kinds with packet.
7) VLAN realizes: IEEE 802.1p is the extension protocol of IEEE 802.1q (VLAN label protocol) standard, their collaborative works.IEEE 802.1q standard definition the label that adds for the ethernet mac frame.The VLAN label has two parts: VLAN ID (12 bit) and priority (3 bit).Do not define in the IEEE 802.1q VLAN standard and the use precedence field, then defined this field among the IEEE 802.1p.
8) authentication service (802.1x): the 802.1x Verification System provides a kind of means of access authentication of user, and it only pays close attention to opening and closing of port.When inserting for validated user (according to number of the account and password), this port is opened, and inserts or when not having the user to insert, then make port be in closed condition for the disabled user.
9) STP (Spanning-Tree Protocol) prevents broadcast storm, by blocking one or more redundancy ports, safeguards a loop-free network (IEEE802.1d);
10) Webserver: utilize webpage that system is managed, transmission is provided with.
3, preferred embodiment 3 (local side apparatus, ustomer premises access equipment principle constitute block diagram)
Be illustrated in figure 2 as 201 and be ethernet signal; 202 are RJ45 connection ethernet signal; 203 is PHY chip such as chips such as IP101, RTL8201; 204 finish major function for the SOC chip; 205 programs for the operation of SDRAM chip-stored; 206 is FLASH chip-stored condensing routine; 207 is AD9865 or other high-speed AD/DA conversion chip, as AD9868, AD9865 etc.; 208 is OPA26 74 chips, amplifies the analog signal of output; 209 are the communication of high-pass and low-pass filter realization frequency division.
The course of work of modulation: the ethernet signal of 201 inputs is through 203 PHY chip conversion, ethernet signal on the twisted-pair feeder is transformed to the MII interface signal, the MII interface of the SOC chip by 204 is a network data with the network interface conversion of signals, and network data is directly given the accelerating engine of SOC by the dma mode of SOC; Carry out encryption, the decryption processing of data through accelerating engine, the encoding and decoding of MAC data are handled, the encoding and decoding of PHY layer are handled, the encoding and decoding of modulation system are handled, the data of modulation are delivered to ad/da converter at a high speed such as AD9865 or AD9868, data-signal is converted to analogue data, after OPA2 674 amplifies, delivers to 209 high-pass and low-pass filters, modulation signal and TV signal mixing back are exported by coaxial cable.
The course of work of demodulation: the mixed signal of 211 inputs, isolating the 2-30MHz modulation signal through 209 high-pass and low-pass filters carries out A/D and is converted to parallel data through 207 high-speed a/ds, D/A conversion chip AD9865, AD9868, give SOC chip 2 04, through the SOC decoding circuit formation data flow of decoding, send the data to the 203PHY chip by SOC by DMA, form network data.
4, preferred embodiment 4, high-speed wideband SOC chip (theory diagram such as Fig. 3):
Employing has the IP of ARM926EJ, ARM946EJ, ARM966EJ or the MIPS of DSP instruction set and Java accelerator, expansion MI I interface, synchronous communication interface, the crypto engine of dynamic reconfigurable, the modulating/demodulating accelerating engine of dynamic reconfigurable, Asynchronous Serial Interface, USB mouth on the AMBA of ARM926EJ bus.Outside chip, add ad/da converter at a high speed.
External interface adopts the AMBA bus to link to each other with interface module, and this SOC chip mainly comprises with lower interface:
● sdram interface: be used to connect SDRAM (synchronous DRAM), operating system, firmware program, application program are moved in SDRAM.
● the FLASH interface: be used to connect FlashROM (quick electric erasable read only memory), FlashROM is used to deposit bootloader (using Uboot), firmware program, built-in application program.
● the MAC interface: the MAC interface is inner to be connected with ARM926EJ by the AMBA bus, and the interface of the outside MII of employing, RMII compatibility connects PHY chip or exchange chip;
● USB interface: adopt interface (backward compatible USB1.1) standard of USB2.0 standard, comprise one USB Host interface, one USB Device interface.
● UART (Asynchronous Serial Interface): 2,1 is RXD, TXD (3 line) serial ports, is used for the debugging of linux program; 1 is Full Featured serial ports (9 line), is used for communication, and wherein DTR, DSR, RTS, CTS, DCD, RI promptly can be used as the special function control line that general GPIO also can be used as UART.
● GPIO (general I/O control mouth): 8, be used to light LED, the various states of indication chip, GPIO0 is used to indicate modulation encoding and decoding state, GPIO1 is used to indicate the connection status of coaxial cable, and GPIO2-GPIO5 is used to indicate the LINK/ACTIVE state of exchange chip.
● dynamic reconfigurable accelerating engine: be connected employing AMBA interface with ARM926, utilize the dynamic reconfigurable circuit to realize encoding and decoding accelerating algorithm at a high speed, thereby reduce the burden of CPU, thereby significantly reduce, the power consumption of CPU, because the power consumption of special circuit realizes that than universal circuit same function power consumption is much smaller.
● the dynamic reconfigurable crypto engine: inside is connected with the AMBA bus of ARM926, the outside is connected with the AD9865 chip by sync cap, with input, the dateout of AD9865 chip be two-way signaling, the sampled feedback signal of its AD9865 is one way signal 5 parallel-by-bit data, flows to the dynamic reconfigurable crypto engine.
● the PLL module: lock is the dominant frequency (can by program control its frequency be set) of 266MHz for CPU to ring clock control circuit/frequency multiplication control circuit with the frequency frequency multiplication CLK_CPU of 66MHz; The CLK_SDRAM frequency provides synchronised clock for 166MHz for SDRAM; CLK_MAC provides the frequency of 25MHz for the MAC module; CLK_USB provides the frequency of 48MHz for USB; CLK_UART provides the frequency of 33MHz for serial ports; CLK_AD9865 provides the synchronizing frequency of 66MHz for AD9865; CLK_1 is for providing clock to the dynamic reconfigurable accelerating engine; CLK_2 provides clock etc. for the dynamic reconfigurable crypto engine.
● the design of the Firmware firmware of SOC chip: physical layer adopts the modulating/demodulating mode of ofdm signal, and its subcarrier adopts QAM16, QAM64, QAM256, QAM1024, QPSK, according to the adaptive selection modulation/demodulation methods of the result of channel estimating; The descending employing broadcast mode of data link layer (downlink data adopts the dynamic reconfigurable encryption/decryption engine, carries out distributing data according to the MAC Address of each slave unit), up employing dynamic sharing pattern.Operation linux2.6.x operating system cooperates its PHY layer protocol of realization, MAC agreement with the program of processor on ARM926EJ.
● physical layer: the zero intermediate frequency signals that adopts 2-30MHz, can modulate by the frequency conversion chip and to take office on what frequency, can be in low frequency 0-85MHz frequency range operate as normal, can be in 87MHz-86 0MHz frequency range operate as normal, also can be in the 860MHz-2500MHz scope operate as normal.Be divided into 7 independently sub-channels in the frequency range of 28MHz, adopt the OFDM modulation system in each sub-band, each subcarrier self adaptation adopts QAM1024, QAM256, QAM64, QAM16, QPSK carrier system.
Be illustrated in figure 3 as SOC chip internal block diagram, 301 is the SDRAM chip interface circuit, is used for the SOC chip and connects the SDRAM chip; 302 is the processor of ARM926EJ, ARM946EJ, ARM966EJ or MIPS, function: be used for procotol and handle; 303 is the Flash interface, is used to connect the Flash chip, the executive program of the main storage chip of flash chip; 304 is the AMBA bus, is used for SDRAM, CPU, Flash interface, MAC interface, UART interface, GPIO interface, dynamic reconfigurable accelerating engine etc. are coupled together; 306 is MAC, is used to handle 802.3 Ethernet protocols; 308 is USB interface, is main USB interface and from USB interface, is used to connect the USB mouth of computer, or connects the product of the band USB interface of miscellaneous equipment, as printer, and game machine etc.; The UART serial line interface is used to connect computer by serial, the equipment of other band serial ports, and as serial printer, 485 serial ports etc.; The GPIO interface is used for connecting control LED lamp, the control miscellaneous equipment, or be used for Simulation with I
2The C bus is used to connect equipment that EEPROM device, simulation spi bus be used to control spi bus, simulation MDC/MDIO Ethernet control interface etc.; 311 dynamic reconfigurable accelerating engines are realized encryption, the deciphering of network data, the processing of procotol, the processing of MAC layer data, the processing of PHY layer data, code decode algorithm etc.;
312 is the pll clock circuit, the clock of input is exported to corresponding circuit through the pll clock translation circuit with the clock that input clock is transformed to various needs, input to processor 302 after the clock frequency conversion of CLK_CPU with input, use for CPU, the CLK_SDRAM clock signal flows to external SDRAM chip use and offers the use of sdram interface circuit simultaneously after frequency conversion, guarantee that external SDRAM device and sdram interface circuit are synchronous; The MAC module that CLK_MAC clock, clock are provided as in the SOC chip is used the clock that offers external PHY chip simultaneously, keeps the synchronous of PHY chip and MAC module; CLK_USB provides clock for outside USB physical chip; CLK_UART provides clock for the UART module, in order to produce the clock signal of UART, is the different baud rate of UART product; CLK_AD98 65 provides clock for the accelerating engine of AD9865 and SOC inside, the sampling and the conversion of the AD/DA conversion of control AD9865; The another one clock that CLK_1 provides for the dynamic reconfigurable engine is for the processing of dynamic reconfigurable engine.
5, preferred embodiment 5 (local side apparatus is seen Fig. 4 in conjunction with the modulating/demodulating process of the data-signal of chip) local side modulation:
Ethernet data is input to the MII interface of the MAC of SOC chip through PHY chip (IP101), through the AMBA bus, directly be sent to dynamic reconfigurable accelerating engine → by dma mode through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal data are abandoned, if data are legal → the MAC layer: according to the priority of data, arrange time slot and bandwidth by the TDMA agreement, if the time slot that now is not this user side sends the back then buffer memory wait time slot arrives, if the time slot of this user side transmission → PHY layer immediately then: realize range finding, burst transfer, forward error correction, channel estimating, power control → coding layer: realize OFDM, QAM, the QPSK modulation reaches and AD98 65 interfaces, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize that FEEDBACK CONTROL → data to the AD9865 chip are sent to AD9865 and form analogue data output → process 0PA2674 through D/A and amplify, the modulated analog signal that forms 2-30MHz transmits on coaxial cable, delivers to each ustomer premises access equipment.
The local side demodulation:
The analog signal that sends from user side → be sent to AD9865 to be converted to data output → coding layer through A/D: with the Data Format Transform of AD9865 is 32bit data lattice → PHY layer: realize range finding, burst transfer, forward error correction, channel estimating, power control, the control AD9865 reception data of appropriate state, make the error rate minimum → the MAC layer: with the reduction of data that receives is original data → through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal that data are abandoned, if data legal → data send to Ethernet data through PHY chip (IP101) by AMBA bus dma mode.
The ARM926EJ processor, the ARM926EJ processor in the SOC chip is responsible for handling the management data in the native system, is responsible for dynamic-configuration dynamically programmable circuit.
The data that the data medium priority is the highest are used for the signaling-information of voice signal and video on demand.6, preferred embodiment 6 (the modulating/demodulating process of ustomer premises access equipment, chip internal dynamic reconfigurable accelerating engine theory diagram combines realization with coding, decoding accelerating engine block diagram, sees Fig. 4)
The modulation of ustomer premises access equipment:
Ethernet data is input to the MII interface of the MAC of SOC chip through PHY chip (IP101), through the AMBA bus, directly be sent to dynamic reconfigurable accelerating engine → by dma mode through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal data are abandoned, if data are legal → and the MAC layer: wait for that local side apparatus arranges time slot and bandwidth, if uploading the time slot that is not this user side now sends the back then buffer memory wait time slot arrives, if the time slot of this user side transmission → PHY layer immediately then: realize range finding, burst transfer, forward error correction, channel estimating, power control, control AD9865 with suitable parameter with data transmissions → coding layer: realization OFDM, QAM, the QPSK modulation reaches and the AD9865 interface, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize that FEEDBACK CONTROL → data to the AD9865 chip are sent to AD9865 and form analogue data output → process OPA2674 through D/A and amplify, the modulation signal that forms 2-30MHz send transmission at coaxial cable, delivers to local side apparatus.
The user side demodulation:
The analog signal that sends from local side → be sent to AD9865 to form data output → coding layer: realize that OFDM, QAM, QPSK demodulation reach and the AD9865 interface through A/D, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize FEEDBACK CONTROL → PHY layer: realize range finding, burst transfer, forward error correction, channel estimating, power control to the AD9865 chip, thereby the control AD9865 reception data → MAC layer of appropriate state: if the data of this user side then are reduced to original data; Data if not this user side, then it is abandoned → through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal that data are abandoned, if data legal → data send to Ethernet data through PHY chip (IP101) by AMBA bus dma mode.
7. the preferred embodiment 7 TDMA processing procedure of time slot (distribution according to need)
The uplink and downlink data can be the full-duplex communication modes, also can be the half-duplex operation modes.
Downlink data comprises: downlink signaling and downlink data two parts.Downlink signaling comprises synchronous head (being used for the synchronous of master-slave equipment), issue the data user and hold address (MAC Address number and the serial number that distributes, serial number is when logining local side by user side, the number that order produces), forward error correction, time slot demand, the priority that local side proposes according to all ustomer premises access equipments will be sought unification to dispatch to arbitrate to issue and be allowed this user side to upload the length of time slot; Ustomer premises access equipment sends data according to the time slot that local side issues to local side.
Upstream data comprises: up signaling, upstream data.Up signaling comprises: user side address (serial number that this user side is distributed with MAC Address and local side), next frame need be uploaded the length of payload user data, the priority of next frame data (annotate: the demand of this frame, local side next frame issue the Shi Caihui response), there are the length of this frame numeric data code that order is brought according to local side, payload user data etc. in the back again.
Be illustrated in figure 5 as the left side and send to a certain user side data format for local side, right-hand member is that a certain user side is uploaded data format.
501 for local side sends to the n framed user end number of a certain user side data, MAC Address, and wherein local side lands the number of local side according to user side during user side, on for example first user side is logined behind the local side, user side number is that the number of 0, the 10 local side in the login is 9, by that analogy.Frame number represents that the data that transmit are the n frame, represents exactly to send to this user side from beginning to send to present the n time; MAC Address represents that this is the MAC Address of that user side.
The priority of 502 requests of uploading according to this user side previous frame for local side and the length of request msg produce through arbitration, keep for the size of the time slot of this user side, upload data according to this standard when uploading data for the user side next frame.
503 is the length code that is handed down to the n frame data, gives MAC Address equipment in 501, the data length of following after the expression length code.Length code has two kinds of method for expressing: (1) is directly represented with the byte number of following data.The advantage of this representation is that the data of being followed all are valid data, do not have unwanted filler.Shortcoming is: the figure place that the expression word length needs is many, and the transmission time is more scrappy, the dispatching algorithm more complicated; (2) represent with a timeslice.A timeslice can be transmitted a plurality of bytes, as representing with 1 that with 1024 bytes 2048 bytes are represented etc. with 2.The advantage of this mode: the data of expression word length are short, and the time is convenient to handle by the expression of a slice, a slice.Shortcoming: the end of last frame always is 1024 complete bytes usually, and discontented the needs fills, so efficient is relatively low.
Local side is distributed to the time slot that user side uploads two kinds of method for expressing: (1) time slot is the integral multiple of certain unit time slot; (2) time slot is an arbitrary value.
504 is the data that the n frame issues, and just payload user data is the data that really will transmit.
509-513 is that a certain user side n frame is uploaded data format.
509 comprise the MAC Address of user side number and this user side of this bag and this frame number for the address of user side.User side number is the serial number that local side is distributed to this user side, for example: 1 local side, the system of 64 user sides, the serial number 0-63 of user side; MAC Address is the MAC Address of ustomer premises access equipment; This frame is the n frame, so this frame number is n.
510 upload the priority of next frame tendency to develop data for this user side, promptly below a frame need upload the priority of data, we reserve 8, the standard of existing IPv4 is 3.
511 upload the length of next frame tendency to develop data for this user side.
510,511 all is the priority of data of the transmission that needs of request next frame and the length of tendency to develop transmission of data, after to be this user side according to this equipment needs transmitted the priority of data setting and data cached size that this equipment needs are uploaded data and send local side to, local side was unified scheduling according to the request of all user sides in the native system.
If the resource that other user sides need is few, can satisfy the demand of this user side.Then local side is arbitrated, and transmits the data of this user side for the sufficiently long time slot of this user side at next frame by the needs of this user side.
If other user sides also need resource, then local side is according to the unified scheduling of size that each user side priority and needs transmit data, and the suitable time slot of distributing to this user side is used for this user side and uploads data.
512 is the length that the n frame is uploaded data, and promptly this user side is uploaded data length, just the back length of data and then.
513 is that the n frame is uploaded the data data, i.e. payload user data.
Downlink data: it is that local side transmits the priority of data according to each ustomer premises access equipment needs and the length of data is dispatched that the local side data send user side to, is broadcast to each user side.User side is according to the MAC Address that sends to the different user end, if the data of this user side then receive and decode; Data if not this user side are then given up this frame.
Upstream data: the length that the timeslot scheduling of upstream data priority that to be local side upload according to the user side previous frame and needs are uploaded data is unified to arrange to give this frame of this user side to upload time slots.This user side arranges suitable data to upload for the size of the time slot of local terminal according to local side.
For the data of no initializtion, first frame data that send of local side for example, local side does not receive the request msg that the user brings in as yet.Then local side is according to the time slot of each user side of user side number mean allocation of login.
8. preferred embodiment 8 (negotiations of user side data)
The login of ustomer premises access equipment utilizes the CSMA/CA agreement to realize.In each time slot of uploading and descending to pass, there is one section very little time slot to adopt the CSMA/CA mode.The manner only is used for local side apparatus and ustomer premises access equipment is consulted, and ustomer premises access equipment is registered on the local side apparatus, finishes the registration of new equipment.
Be illustrated in figure 6 as the theory diagram that utilizes CSMA/CA registration, 601 be the MAC Address of local side, 6 02 broadcasting commands for sending, and 603 be the MAC Address according to this user side of 602 broadcasting commands answer of a certain user side, 604 is the flag bit of replying.
Login has dual mode.Mode one, the roll-call mode.When local side sends one when calling the roll order, the MAC Address+0x01 of local side (supposing that here 0x01 is the roll-call log on command), listed each user side is according to the order of its login recall signal successively.Mode two, addition manner.When local side sends an addition manner, the MAC Address+0x02 of local side (supposing that here 0x02 adds order), the ustomer premises access equipment of having logined is not replied.Behind random time of ustomer premises access equipment time-delay of not logining, answer the MAC of this user side and reply interpolation command keyword 0x02, local side adds ustomer premises access equipment in the login formation of local side according to the answer of user side, generates a new ustomer premises access equipment.If reply data bumps, then resend the interpolation command mode.Till all ustomer premises access equipments are all logined.
So just all ustomer premises access equipments are all signed in in the local side apparatus.
Though in conjunction with the accompanying drawings embodiments of the present invention are described, those of ordinary skills can make various distortion or modification within the scope of the appended claims.
Claims (10)
1. the dynamic time-slot TDMA distribution implement device comprises local side apparatus, ustomer premises access equipment; Local side apparatus, ustomer premises access equipment are by formations such as SOC chip, high-speed AD/DA conversion chip, PHY chip, SDRAM chip, FlashROM chips; Wherein,
SOC chip: by sdram interface, FLASH interface, MAC interface, USB interface, UART, GPIO, PLL module, dynamic reconfigurable accelerating engine; Wherein,
The dynamic reconfigurable accelerating engine is characterized in that: comprise encryption, deciphering layer: encryption, deciphering, network intrusions control accelerating engine; The MAC layer: the channel arrangement, comprise priority and bandwidth, time slot is arranged accelerating engines such as TDMA; PHY layer: range finding, burst transfer, forward error correction, channel estimating, power control accelerating engine; Coding and decoding layer: OFDM, QAM, QPSK modulation reach and AD9865 interface accelerating engine;
The TDMA mode that principal and subordinate's dynamic slot distributes is adopted in communication between local side apparatus, the ustomer premises access equipment; It is characterized in that: downlink data comprises downlink signaling and downlink data two parts; Upstream data comprises: up signaling, upstream data; Master-slave equipment is consulted to adopt roll-call and is added the two kinds of patterns of consulting.
2. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: the local side coding, Ethernet data is input to the MII interface of the MAC of SOC chip through the PHY chip, through the AMBA bus, directly be sent to dynamic reconfigurable accelerating engine → by dma mode through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal data are abandoned, if data are legal → the MAC layer: according to the priority of data, arrange time slot and bandwidth by the TDMA agreement, if the time slot that now is not this user side sends the back then buffer memory wait time slot arrives, if the time slot of this user side transmission → PHY layer immediately then: realize range finding, burst transfer, forward error correction, channel estimating, power control → coding layer: realize OFDM, QAM, the QPSK modulation reaches and the AD9865 interface, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize that FEEDBACK CONTROL → data to the AD9865 chip are sent to AD9865 and form analogue data output → process OPA2674 through D/A and amplify, form modulated analog signal and on coaxial cable, transmit, deliver to each ustomer premises access equipment.
3. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: the local side decoding, the analog signal that sends from user side → be sent to AD9865 to be converted to data output → coding layer through A/D: with the Data Format Transform of AD9865 is 32bit data lattice → PHY layer: realize range finding, burst transfer, forward error correction, channel estimating, power control, the control AD9865 reception data of appropriate state, make the error rate minimum → the MAC layer: with the reduction of data that receives is original data → through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal that data are abandoned, if data legal → data send to Ethernet data through the PHY chip by AMBA bus dma mode.
4. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: the user side coding, Ethernet data is input to the MII interface of the MAC of SOC chip through the PHY chip, through the AMBA bus, directly be sent to dynamic reconfigurable accelerating engine → by dma mode through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal data are abandoned, if data are legal → and the MAC layer: wait for that local side apparatus arranges time slot and bandwidth, if uploading the time slot that is not this user side now sends the back then buffer memory wait time slot arrives, if the time slot of this user side transmission → PHY layer immediately then: realize range finding, burst transfer, forward error correction, channel estimating, power control, control AD9865 with suitable parameter with data transmissions → coding layer: realization OFDM, QAM, the QPSK modulation reaches and the AD9865 interface, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize that FEEDBACK CONTROL → data to the AD9865 chip are sent to AD9865 and form analogue data output → process OPA2674 through D/A and amplify, form modulation signal and send transmission, deliver to local side apparatus at coaxial cable.
5. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: the user side decoding, the analog signal that sends from local side → be sent to AD9865 forms data output → coding layer through A/D: realization OFDM, QAM, the QPSK demodulation reaches and the AD9865 interface, the data format of AD9865 and 32 bit data forms of SOC inside are changed in realization, and realize FEEDBACK CONTROL → PHY layer: realize range finding to the AD9865 chip, burst transfer, forward error correction, channel estimating, power control, thereby the control AD9865 reception data → MAC layer of appropriate state: if the data of this user side then are reduced to original data; Data if not this user side, then it is abandoned → through the legitimacy of network intrusions early warning with control accelerating engine and encrypt/decrypt accelerating engine judgment data, if data are illegal that data are abandoned, if data legal → data send to Ethernet data through the PHY chip by AMBA bus dma mode.
6. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: downlink data comprises downlink signaling and downlink data two parts; Downlink signaling comprises synchronous head, issue serial number, forward error correction that the data user holds address MAC Address number and distributes; Time slot demand, the priority that local side proposes according to all ustomer premises access equipments will be sought unification to dispatch to arbitrate to issue and be allowed a certain user side to upload the length of time slot; Ustomer premises access equipment sends data according to the time slot that local side issues to local side.
7. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: upstream data comprises up signaling, upstream data; Up signaling comprises the serial number that with MAC Address and local side this user side is distributed the user side address, the length that next frame need be uploaded payload user data, the priority of next frame data, again the back have this frame according to local side order bring and allow to upload numeric data code length, payload user data etc.
8. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: local side is distributed to the time slot that user side uploads two kinds of method for expressing: time slot is the integral multiple of certain unit time slot; Time slot is an arbitrary value.
9. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: between each time slot of uploading and passing down, have one section very little time slot to adopt the CSMA/CA mode to carry out handshake between local side apparatus and the ustomer premises access equipment; The manner is used for local side apparatus and ustomer premises access equipment is consulted, and is used for ustomer premises access equipment and initiatively tells local side apparatus, the existence of slave unit and the new MAC Address that adds slave unit; This negotiation has dual mode roll-call mode, addition manner.
10. dynamic time-slot TDMA distribution implement device according to claim 1, its feature comprises: when local side sent an addition manner, the ustomer premises access equipment of having logined was not replied; The ustomer premises access equipment of not logining was delayed time after the time with the captain, answer the MAC of this user side and reply the interpolation command keyword, local side adds ustomer premises access equipment in the login formation of local side according to the answer of user side, generates a new ustomer premises access equipment; If reply data bumps, then resend the interpolation command mode; Till all ustomer premises access equipments are all logined.
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