CN111290889B - FPGA-based universal processor-oriented test method and system - Google Patents

Abstract

The invention provides a test method and a test system for a general processor based on an FPGA (field programmable gate array). The method comprises the following steps: dividing a processor into at least two parts, wherein each part is placed on an FPGA; setting a data conversion triggering condition of a parallel data-to-serial data module on each FPGA; performing function configuration on the data capture module; relocating processor execution code using a debug tool; if the triggering condition for converting the parallel data into the serial data is met, downloading the required data into a data grabbing module; stopping data capture work after the data capture module captures the required data, and exporting the data stored in the data capture module; converting the exported data into a VCD format file; and carrying out hardware debugging based on the VCD file. The invention can effectively solve the contradiction between larger area of the general processor and limited capacity of the FPGA, and provides a more flexible test means according to the test requirement.

Description

FPGA-based universal processor-oriented test method and system

Technical Field

The invention relates to the technical field of digital circuit design, in particular to a test method and a test system for a general processor based on an FPGA (field programmable gate array).

Background

As chip processes continue to improve and upgrade, the size and complexity of general purpose processors has grown geometrically. In the case of a short project period, testing based solely on EDA (Electronic Design Automation) software cannot completely ensure that all hardware problems can be solved. In the early days of the project, if more system software can be tested by using an FPGA (Field Programmable Gate Array), great confidence is brought to the tape-out and mass production of the final chip. Although FPGAs are also continuously improving and upgrading in recent years, a single FPGA cannot fully accommodate the processor and peripheral circuits in capacity. Although it is not a new topic to distribute the design on different FPGAs, for a general purpose processor, due to the characteristics of high association degree between the fully synchronous circuit design and the front and back stages of the internal logic of the general purpose processor, there is a certain technical challenge to distribute the design on different FPGAs. In addition, when system level software is tested, if the hardware has errors, the final display of the error position and the actual error position may have been different by tens of millions of instructions, and it is almost impossible to analyze the problem according to the error information. Testing system software on FPGAs also faces such problems.

At present, due to the design complexity and high integration of the general-purpose processor, methods for distributing designs on different FPGAs have respective characteristics and limitations, and no general principle and method for the general-purpose processor are provided. In addition, for signal capture on FPGAs, FPGA companies provide on-chip debugging means, such as the Chipscope tool of Xilinx. However, the method is not suitable for debugging a general-purpose processor due to the inflexible triggering mode, the limited debugging signals provided and insufficient debugging information.

At present, there are some related technologies for testing a general-purpose processor based on an FPGA, but there is no principle and effective method for how to divide a general-purpose processor design, and there is no effective method for how to obtain enough debugging information on the FPGA.

Disclosure of Invention

The FPGA-based general processor-oriented testing method and system provided by the invention can effectively solve the contradiction between larger area of the general processor and limited capacity of the FPGA, and provide a more flexible testing means according to the testing requirement.

In a first aspect, the present invention provides a test method for a general-purpose processor based on an FPGA, including:

the processor is divided into at least two parts, each part is placed on an FPGA, and the processor is divided according to the following principle: when the processor is divided, finding out a signal which does not need to be fed back by the signal of the next-stage module in the current period, and dividing the processor at a position which is connected between the next-stage module and the first-stage module through the signal; if the processor can not be found, the processor is divided in the bus function area or the area close to the bus function area;

setting a data conversion triggering condition of a parallel data-to-serial data module on each FPGA;

performing function configuration on the data capture module;

relocating processor execution code using a debug tool;

if the triggering condition for converting the parallel data into the serial data is met, downloading the required data into the data capturing module;

stopping data capture work after the data capture module captures the required data, and exporting the data stored in the data capture module;

converting the exported data into a VCD format file;

and carrying out hardware debugging based on the VCD file.

Optionally, the performing function configuration on the data capture module includes: data filtering, triggering conditions, whether to grab the transfer data and whether to read the DDR data for configuration.

Optionally, the working process of the data capture module includes the following steps:

reading data in the DDR through the PC;

on the PC, converting the binary file into a VCD file;

and visually opening the VCD file by using an EDA tool, and then debugging hardware.

In a second aspect, the present invention provides an FPGA-based general-purpose processor-oriented test system, wherein the processor is divided into two parts, and each part is placed on one FPGA, the system comprising: the system comprises a first FPGA, a first data capture module and a debugging tool module which are connected with the first FPGA, a second FPGA and a second data capture module which is connected with the second FPGA, wherein the first FPGA is connected with the second FPGA through high-speed Serdes serial IO;

the first FPGA comprises a first processor part design module, a debugging interface module, a first parallel data-to-serial data module and a first mmcm clock module, wherein the first parallel data-to-serial data module is connected with the first processor part design module and the first data capture module, the first processor part design module is connected with the debugging interface module, and the debugging interface module is connected with the debugging tool module;

the second FPGA comprises a second processor part design module, a second parallel data-to-serial data module and a second mmcm clock module, the second parallel data-to-serial data module is connected with the second processor part design module and the second data capture module, and the second processor part design module is connected with the debugging interface module.

Optionally, the first parallel data to serial data conversion module and the second parallel data to serial data conversion module are configured to set a data conversion trigger condition, convert the required parallel data in the processor into serial data in real time, and transmit the serial data to the LVDS interface.

Optionally, the first processor design module and the second processor design module are configured to perform asynchronous transmission on the part of the design divided by the processor and the other part of the design.

Optionally, the debug interface module is configured to convert an external JTAG interface into an APB.

Optionally, the first mmcm clock module is configured to generate a required clock for each functional module on the first FPGA;

and the second mmcm clock module is used for generating required clocks for each functional module on the second FPGA.

Optionally, the first data capture module is configured to receive serial data from the first FPGA and store the data in a storage medium in real time;

and the second data grabbing module is used for receiving serial data from the second FPGA and storing the data to a storage medium in real time.

The FPGA-based universal processor-oriented testing method and system provided by the embodiment of the invention can effectively solve the contradiction between larger area of the universal processor and limited capacity of the FPGA, can provide a more flexible debugging means according to the debugging requirement, and can collect, store and restore sufficient debugging information to find the internal problems of the processor. Based on the internal functional characteristics of the general processor, the processors are distributed on a plurality of FPGAs, so that the success rate and the efficiency of FPGA development can be improved; sufficient debugging information can be obtained, hardware problems can be positioned in a short time, and the development cycle of a project is accelerated.

Drawings

Fig. 1 is a schematic structural diagram of a general-purpose processor-oriented test system based on an FPGA according to an embodiment of the present invention;

FIG. 2 is a flowchart of a general purpose processor-oriented FPGA-based test method according to an embodiment of the present invention;

FIG. 3 is a block diagram of a processor according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a data capture module according to an embodiment of the present invention;

fig. 5 is a flowchart of a data capture module according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides a test system facing a general processor based on FPGA (field programmable gate array). As shown in figure 1, a processor is divided into two parts which are respectively placed in two FPGA;

101 is a first FPGA, which comprises a processor part Design module Design1, a Debug interface module DAP (Debug Access Port), and a Parallel To Serial data conversion module of parallell To Serial 1;

102 is a second FPGA, which comprises a processor part Design module Design2 and a Parallel To Serial data conversion module of Parallel To Serial 2;

the first FPGA and the second FPGA are connected through a high-speed Serdes (Serializer/Deserializer) serial IO;

the Parallel To Serial1 data To Serial data conversion module 103 can set a data conversion trigger condition, convert the required Parallel data in the processor into Serial data in real time, and transmit the Serial data To an LVDS (Low-Voltage Differential Signaling) interface;

a processor part Design1 module 104, which is used for asynchronously transmitting the part Design divided by the processor and the other part Design;

a Debug interface module 105, which is a standard DAP (Debug Access Ports) protocol and can convert an external JTAG (Joint Test Action Group) interface into an APB (Advanced Peripheral Bus) interface;

a first mmcm (mode clock manager) clock module 106, which generates the required clocks for the functional modules on the FPGA 1. The module is generated by directly utilizing an FPGA embedded function;

a Parallel To Serial2 data To Serial data conversion module 107 capable of setting a data conversion trigger condition, converting the required Parallel data inside the processor into Serial data in real time, and transmitting the Serial data To the LVDS interface;

a processor part Design2 module 108, which is used for asynchronously transmitting the part Design divided by the processor and the other part Design;

and the second mmcm clock module 109 is used for generating required clocks for all functional modules on the FPGA 2. The module is generated by directly utilizing an FPGA embedded function;

the data capture module 110 needs to be configured by an upper computer on one hand, and can receive serial data from the FPGA1 on the other hand and store the data in a storage medium in real time. The upper computer can read out the data in the storage medium and convert the data into debugging information;

the data capture module 111 needs to be configured by an upper computer on one hand, and can receive serial data from the FPGA2 on the other hand and store the data in a storage medium in real time. The upper computer can read out the data in the storage medium and convert the data into debugging information;

the debugging tool module 112 is a general-purpose debugging tool, such as a Trace-32 tool.

The embodiment of the invention also provides a test method facing a general processor based on FPGA, as shown in FIG. 2, the method comprises the following steps:

in step S201, the processor is first divided. The specific segmentation method will be described in detail later.

Step S202, setting data conversion triggering conditions of the parallel data to serial data modules 103 and 107. The triggering conditions mainly include condition triggering, delay triggering and the like. Conditional triggering refers to a certain preset condition being satisfied to trigger parallel-to-serial conversion. The time delay triggering refers to triggering parallel-serial conversion after time delay meets preset time.

Step S203, configuring the functions of the data capture modules 110 and 111. The configuration comprises data capture triggering conditions, data capture size, data capture time and the like. As will be described in detail later.

Step S204, relocating the processor execution code using the debug tool 112. The debug tool may change the PC (Program Counter) value within the processor after the processor is connected.

In step S205, if the trigger condition for converting parallel data into serial data is satisfied, the required data will be downloaded into the data capture modules 110 and 111.

In step S206, after the data capture modules 110 and 111 capture the required data, the PC upper computer may be used to stop the data capture work of the modules 110 and 111. The data that exists inside it is then exported.

And step S207, converting the exported data into a VCD format file. The VCD format file is a standard waveform file format. The EDA tool may visually display the signal information therein.

And step S208, performing hardware debugging based on the VCD file.

The processor is divided into two parts, and the method is specifically carried out according to the following principle:

the processor is designed synchronously, each module is closely related to the front and back stages, and the output of the signal may need the same period feedback of the signal of the next stage module.

In splitting the processor, signals that do not require the same cycle feedback of the next stage module signal, which is usually concentrated on signals having a bus function or a similar bus function, are found as much as possible.

If the above mentioned signals are not found, it is necessary to be as close to or in the bus function area as possible when the processor is split.

The above mentioned positions were chosen for the following reasons: the part of functions are usually positioned at the tail end of the processor, so that the internal design of the processor can be evenly divided into two parts as far as possible, and resources in the FPGA are utilized to the maximum extent; at the same time, the operating clock frequencies of the two-part design will not be exactly the same, and then the input and output throughputs will not be the same for each part of the design. The functional characteristic of the bus functional region or the proximity of the bus functional region is that the input and output throughputs are maintained consistent by itself.

In addition, the above-mentioned location design is changed into a credit mechanism, which means that the number of the next-level module that can accept the read/write requests is limited and known. Then, when the previous-stage module sends a request, it knows the number of requests that it has sent, and also knows how many requests have been processed, so that the previous-stage module does not need the feedback of the next-stage module.

Taking the example of a processor having two cores and an L2C, the split structure is shown in fig. 3.

Each Core has a function similar to an AXI (Advanced extensible Interface) bus with an Interface portion of the L2C, and Core1 and L2C (Level 2 Cache) interfaces are selected as division points in fig. 3.

301 are the design parts of Core0 and L2C, placed on FPGA 1.

302 is Core1 design, which is separated from L2C and its interface is connected to a parallel to serial module.

The Parallel To Serial1 data To Serial data module 303 converts all output signals in Core1 into Serial output signals, and here, a high-speed Serdes IO is embedded in an FPGA. Here each transition may set the enabling condition to be when there is a valid request.

A Serial To Parallel1 Serial data To Parallel data module 304, which converts the received Serial data To Parallel data and transmits the Parallel data To the L2C.

The Parallel To Serial2 data To Serial data conversion module 305 converts all output signals in the L2C into Serial output signals, and here, the FPGA is used To embed the high-speed Serdes IO. Here each transition may set the enabling condition to be when there is a valid request.

A Serial To Parallel2 Serial data To Parallel data module 306, which converts the received Serial data To Parallel data and transmits the Parallel data To Core1.

The data capture module can be developed based on an FPGA, and a schematic structural diagram of the data capture module is shown in fig. 4.

The Cmd _ receiver command receiving module 401 is connected to the upper PC through a USB, and can receive commands from the PC, including configuration, start, and data transfer from a DDR (Double data Rate SDRAM) to the PC. And meanwhile, commands of the upper computer can be transmitted to other functional modules to complete related functions.

The config _ stats configuration state 402 module embeds function and status registers to hold configuration commands and current operating state.

The Lvds _ receiver differential receiving module 403 receives the internal signal from the processor through Lvds differential transmission, and then expands the received data in parallel.

The Data Filer Data filtering module 404 can filter out unnecessary Data according to the configured specific Data pattern of the upper computer.

The Capture Trigger module 405 can start to Capture required data according to the configured Trigger condition of the upper computer. The trigger conditions include special data pattern, delay trigger, specific address data, and the like.

The Burst Capture continuous Capture module 406 can, on the one hand, transfer the received data to a DDR Controller (DDR Controller) in real time, that is, store the data. On the other hand, a data reading request can be sent to the DDRC, and the data in the DDR is transmitted to the upper computer PC, so that the upper computer can obtain debugging information. The PC of the upper computer can configure the data capturing size and the data capturing time of the module.

The DDRC memory controller module 407, which can read and write DDR, can be implemented by using an FPGA embedded DDRC.

The working process of the data capture module is shown in fig. 5.

And S501, configuring by an upper computer PC, wherein the configuration comprises data filtering, triggering conditions, whether to capture transmitted data and whether to read DDR data. And can set whether data within the DDR can be Wrap.

And step S502, starting a data capture module to obtain captured data.

And S503, reading the data in the DDR through the upper computer PC. The format of the data is a binary file.

Step S504, on the upper PC, the binary file is converted into a VCD (Value Change Dump) file.

And step S505, visually opening the VCD file by utilizing an EDA tool, and then debugging hardware.

The storage medium of the data capture module is not limited to DDR, and can be externally connected with a storage medium with higher speed and larger capacity. Meanwhile, the data transmission can also be carried out by utilizing the high-speed Ethernet.

The FPGA-based universal processor-oriented testing method and system provided by the embodiment of the invention can effectively solve the contradiction between larger area of the universal processor and limited capacity of the FPGA, can provide a more flexible debugging means according to the debugging requirement, and can collect, store and restore sufficient debugging information to find the internal problems of the processor. Based on the internal functional characteristics of the general processor, the processors are distributed on a plurality of FPGAs, so that the success rate and the efficiency of FPGA development can be improved; sufficient debugging information can be obtained, hardware problems can be positioned in a short time, and the development cycle of a project is accelerated.

It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A FPGA-based general processor-oriented test method is characterized by comprising the following steps:

the processor is divided into at least two parts, each part is placed on an FPGA, and the processor is divided according to the following principle: when the processor is divided, if a signal which does not need to be fed back by the signal of the next-stage module in the current period is found, the processor is divided at a position where the signal is connected between the first-stage module and the next-stage module; if the processor can not be found, the processor is divided in the bus function area or the area close to the bus function area;

setting a data conversion triggering condition of a parallel data-to-serial data module on each FPGA;

performing function configuration on the data capture module;

relocating processor execution code using a debug tool;

if the triggering condition for converting the parallel data into the serial data is met, downloading the required data into the data capturing module;

stopping data capture work after the data capture module captures the required data, and exporting the data stored in the data capture module;

converting the exported data into a VCD format file;

and carrying out hardware debugging based on the VCD file.

2. The method of claim 1, wherein functionally configuring the data crawling module comprises: data filtering, triggering conditions, whether to grab the transfer data and whether to read the DDR data for configuration.

3. The method according to claim 1 or 2, wherein the working process of the data grabbing module comprises the following steps:

reading data in the DDR through the PC;

on the PC, converting the binary file into a VCD file;

and visually opening the VCD file by using the EDA tool, and then debugging hardware.

4. The FPGA-based general processor-oriented test system is characterized in that a processor is divided into two parts, each part is placed on one FPGA, and the division of the processor is carried out according to the following principle: when the processor is divided, if a signal which does not need to be fed back by the signal of the next-stage module in the current period is found, the processor is divided at a position where the signal is connected between the first-stage module and the next-stage module; if the processor can not be found, the processor is divided in the bus function area or the area close to the bus function area; the system comprises: the system comprises a first FPGA, a first data capture module and a debugging tool module which are connected with the first FPGA, a second FPGA and a second data capture module which is connected with the second FPGA, wherein the first FPGA is connected with the second FPGA through high-speed Serdes serial IO;

the first FPGA comprises a first processor part design module, a debugging interface module, a first parallel data-to-serial data module and a first mmcm clock module, wherein the first parallel data-to-serial data module is connected with the first processor part design module and the first data capture module, the first processor part design module is connected with the debugging interface module, and the debugging interface module is connected with the debugging tool module;

the second FPGA comprises a second processor part design module, a second parallel data-to-serial data module and a second mmcm clock module, the second parallel data-to-serial data module is connected with the second processor part design module and the second data capture module, and the second processor part design module is connected with the debugging interface module.

5. The system of claim 4, wherein the first parallel data to serial data module and the second parallel data to serial data module are configured to set a data conversion trigger condition, convert the required parallel data in the processor into serial data in real time, and transmit the serial data to the LVDS interface.

6. The system of claim 4, wherein the first processor portion design module and the second processor portion design module are configured to transmit the processor-partitioned portion design asynchronously with respect to the other portion design.

7. The system of claim 4, wherein the debug interface module is configured to convert an external JTAG interface to APB.

8. The system of claim 4, wherein the first mmcm clock module is configured to generate required clocks for the functional modules on the first FPGA;

and the second mmcm clock module is used for generating required clocks for all functional modules on the second FPGA.

9. The system according to claim 4, wherein the first data capture module is configured to receive serial data from the first FPGA and store the data in real time to a storage medium;

and the second data grabbing module is used for receiving serial data from the second FPGA and storing the data to a storage medium in real time.

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