CN113721698B - High-voltage stabilizing circuit of relative power supply - Google Patents
High-voltage stabilizing circuit of relative power supply Download PDFInfo
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- CN113721698B CN113721698B CN202111106498.6A CN202111106498A CN113721698B CN 113721698 B CN113721698 B CN 113721698B CN 202111106498 A CN202111106498 A CN 202111106498A CN 113721698 B CN113721698 B CN 113721698B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention provides a high-voltage stabilizing circuit relative to a power supply, wherein the positive input end of an operational amplifier in the circuit is a reference voltage VREF relative to GND _ Floating, the negative input end of the operational amplifier is an output voltage VOUT sampling voltage in proportion, and the output end of the operational amplifier is connected with the grid electrode of an adjusting tube HVMOS. When the load is suddenly increased, the output voltage VOUT is reduced, the sampling voltage is reduced, the operation output voltage is increased, the HVMOS pull-down capability is enhanced, the GND _ lying voltage is reduced, therefore VOUT is increased, meanwhile, along with the increase of the VDD power supply voltage, the GND _ Floating voltage is increased, the HVMOS drain bears high voltage, and a corresponding HVMOS tube can be selected according to the voltage withstanding requirement. The circuit only needs one HVNMOS and two HVPMOSes to generate a power supply voltage in a wide range of VDD, and the voltage generating circuit of the invention relative to the power supply is different from the traditional voltage to the ground, can be applied to the condition that the ground wire is unstable, and can be realized by using few high-voltage devices.
Description
Technical Field
The invention relates to the technical field of power supply circuits, in particular to a high-voltage stabilizing circuit relative to a power supply.
Background
The power supply voltage generating circuit is widely applied to integrated circuit design and application, and different internal power supply voltages are designed according to load requirements. The conventional technology is to design a low dropout linear regulator (LDO) that generates a relatively low internal supply voltage. By comparing the sampled output voltage with the reference voltage, the operational amplifier adjusts the gate voltage of the output drive tube, and changes the current capability of the drive tube in response to changes in the load, thereby making the output voltage constant. The technical idea is widely applied to circuits, and the principle is shown in figure 1.
Disclosure of Invention
In order to solve the problems, the invention provides a high-voltage stabilizing circuit relative to a power supply, which can work at high voltage. The circuit comprises a MOS tube P1, wherein the drain end of the MOS tube P1 is connected with a bias current, the gate end of the MOS tube P1 is connected with the gate end of the MOS tube P2, the MOS tube P2 and the MOS tube P3 are connected with the gate end of the MOS tube P4, and the MOS tube P5 and the MOS tube P6 are connected with the gate end of the MOS tube P7.
As an improvement of the invention, the drain terminal of the MOS tube P is connected with the source terminal of the HVPMOS tube P, the gate terminal of the HVPMOS tube P is connected with the gate terminal of the HVPMOS tube P, P and P are high-voltage tubes, the high voltage of the power supply can be blocked from being applied to the lower low-voltage tubes N and N, the drain terminal of the MOS tube P is connected with a resistor R and a resistor R, the resistor R is connected with the source terminal of the MOS tube N, the drain terminal of the MOS tube N is connected with the drain terminal of the MOS tube P, the drain terminal of the MOS tube P is connected with the drain terminal of the MOS tube N, the gate terminal of the MOS tube N is connected with the gate terminal of the MOS tube N, the drain terminal of the MOS tube N is connected with the drain terminal of the MOS tube P, the drain terminal of the source terminal of the MOS tube P is connected with the resistor R and the resistor R, the drain terminal of the MOS tube P is connected with the drain terminal of the MOS tube P, and the source ends of the MOS transistor N2 and the MOS transistor N3 are connected and connected with the drain end of the HVNMOS transistor N7.
As an improvement of the present invention, a drain terminal of the HVPMOS transistor P8 is connected to a drain terminal of the MOS transistor N5, a drain terminal of the HVPMOS transistor P9 is connected to a drain terminal of the MOS transistor N6, a gate terminal of the MOS transistor N5 is connected to a gate terminal of the MOS transistor N6, a gate terminal of the HVNMOS transistor N7 is connected to a drain terminal of the MOS transistor N6, and source terminals of the MOS transistor N5, the MOS transistor N6, and the HVNMOS transistor N7 are connected.
As an improvement of the present invention, a source end of the MOS transistor P11 is connected to the resistor R3 and the resistor R4, and the resistor R4 is connected to a source end of the MOS transistor N4.
As an improvement of the invention, the gate terminals of the MOS transistor P1, the MOS transistor N2, the MOS transistor N3 and the MOS transistor N5 are connected with the drain terminal.
As an improvement of the invention, the positive input end of the operational amplifier is a reference voltage VREF relative to GND _ Floating, the negative input end is an output voltage VOUT proportionally sampled voltage, and the output end of the operational amplifier is connected with the grid electrode of the adjusting tube HVMOS. When the load suddenly increases, the output voltage VOUT decreases, the sampling voltage decreases, the operation output voltage becomes larger, the HVMOS pull-down capability is enhanced, the GND _ fouling voltage decreases, and therefore VOUT increases. Thus producing a constant voltage relative to the power supply. Meanwhile, as the VDD supply voltage rises, the GND _ Floating voltage rises, the HVMOS drain bears high voltage, and a corresponding HVMOS tube can be selected according to the requirement of withstand voltage. The circuit requires only one HVNMOS and two HVPMOS to generate one supply voltage in a wide range of VDD.
As an improvement of the present invention, as the VDD supply voltage increases, the GND _ Floating voltage increases and the HVMOS drain assumes high voltage.
The invention has the beneficial effects that: the invention provides a high-voltage stabilizing circuit relative to a power supply, wherein the positive input end of an operational amplifier is a reference voltage VREF relative to GND _ Floating, the negative input end of the operational amplifier is an output voltage VOUT sampling voltage in proportion, and the output end of the operational amplifier is connected with the grid electrode of an adjusting tube HVMOS. When the load suddenly increases, the output voltage VOUT decreases, the sampling voltage decreases, the operation output voltage becomes larger, the HVMOS pull-down capability is enhanced, the GND _ fouling voltage decreases, and therefore VOUT increases. Thus producing a constant voltage relative to the power supply. Meanwhile, as the VDD supply voltage rises, the GND _ Floating voltage rises, the HVMOS drain bears high voltage, and a corresponding HVMOS tube can be selected according to the requirement of withstand voltage. The circuit only needs one HVNMOS and two HVPMOSes to generate a power supply voltage in a wide range of VDD, and the voltage generating circuit of the invention relative to the power supply is different from the traditional voltage to the ground, can be applied to the condition that the ground wire is unstable, and can be realized by using few high-voltage devices.
Drawings
FIG. 1 shows a prior art voltage regulator circuit.
FIG. 2 is a voltage regulator circuit according to embodiment 1 of the present invention.
FIG. 3 is a voltage regulator circuit according to embodiment 2 of the present invention.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific embodiments, which are to be understood as merely illustrative of the invention and not as limiting the scope of the invention.
Example 1: as shown in fig. 2, the positive input terminal of the operational amplifier is a reference voltage VREF corresponding to GND _ Floating, the negative input terminal is a proportional sampling voltage of the output voltage VOUT, and the output terminal of the operational amplifier is connected to the gate of the HVMOS transistor. When the load suddenly increases, the output voltage VOUT decreases, the sampling voltage decreases, the operation output voltage becomes larger, the HVMOS pull-down capability is enhanced, the GND _ fouling voltage decreases, and therefore VOUT increases. Thus producing a constant voltage relative to the power supply. Meanwhile, as the VDD supply voltage rises, the GND _ Floating voltage rises, the HVMOS drain bears high voltage, and a corresponding HVMOS tube can be selected according to the requirement of withstand voltage. The circuit requires only one HVNMOS and two HVPMOS to generate one supply voltage in a wide range of VDD. As the VDD supply voltage rises, the GND _ Floating voltage rises and the HVMOS drain assumes a high voltage.
Example 2: as shown in fig. 3, the circuit includes a MOS transistor P1, a drain terminal of the MOS transistor P1 is connected to a bias current, a gate terminal of the MOS transistor P1 is connected to a gate terminal of the MOS transistor P2, the MOS transistors P2 and P3 are connected to a gate terminal of the MOS transistor P4, and the MOS transistors P5 and P6 are connected to a gate terminal of the MOS transistor P7. The drain terminal of the MOS tube P is connected with the source terminal of the HVPMOS tube P, the gate terminal of the HVPMOS tube P is connected with the gate terminal of the HVPMOS tube P, the drain terminal of the MOS tube P is connected with the resistor R and the resistor R, the resistor R is connected with the source terminal of the MOS tube N, the drain terminal of the MOS tube N is connected with the drain terminal of the MOS tube P, the drain terminal of the MOS tube P is connected with the drain terminal of the MOS tube N, the gate terminal of the MOS tube N is connected with the gate terminal of the MOS tube N, the drain terminal of the MOS tube N is connected with the drain terminal of the MOS tube P, the source terminal of the MOS tube P is connected with the resistor R and the resistor R, the source terminal of the MOS tube P is connected with the source terminal of the MOS tube P, the drain terminal of the MOS tube P is connected with the drain terminal of the source terminal of the MOS tube N, the drain terminal of the MOS tube P is connected with the drain terminal of the MOS tube P, and the drain terminal of the MOS tube P, the drain terminal of the MOS tube P is connected with the NMOS tube N. The drain end of the HVPMOS tube P8 is connected with the drain end of the MOS tube N5, the drain end of the HVPMOS tube P9 is connected with the drain end of the MOS tube N6, the gate end of the MOS tube N5 is connected with the gate end of the MOS tube N6, the gate end of the HVNMOS tube N7 is connected with the drain end of the MOS tube N6, and the source ends of the MOS tube N5, the MOS tube N6 and the HVNMOS tube N7 are connected. The source end of the MOS transistor P11 is connected with the resistor R3 and the resistor R4, and the resistor R4 is connected with the source end of the MOS transistor N4. And the gate ends of the MOS transistor P1, the MOS transistor N2, the MOS transistor N3 and the MOS transistor N5 are connected with the drain end.
In the invention, reference current flows through R1 and R2 to generate reference voltage as a positive input end of an operational amplifier, output voltage is sampled through R3 and R4 and fed back to a negative input end of the operational amplifier, and the output of the operational amplifier adjusts the grid voltage of an N7 tube, thereby adjusting VOUT.
The VOUT voltage is as follows:
VOUT=IBIAS*R2*（R3+R4）/R4；
the relative power output voltage can be flexibly adjusted by adjusting R3 and R4, IBIAS R2 can be easily designed to be zero temperature coefficient, so that VOUT is also the temperature coefficient of flexibility.
In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that various modifications can be made to the embodiments described in the foregoing embodiments, or some or all of the technical features of the embodiments can be equivalently replaced, and the modifications or the replacements do not make the essence of the corresponding technical solutions depart from the scope of the embodiments of the present invention.
Claims (4)
1. A high voltage stabilizing circuit of a relative power supply is characterized in that the circuit comprises a MOS tube P1, the drain end of the MOS tube P1 is connected with a bias current, the gate end of the MOS tube P1 is connected with the gate end of the MOS tube P1, the MOS tube P1 and the MOS tube P1 are connected with the gate end of the MOS tube P1, the drain end of the MOS tube P1 is connected with the source end of the HVPMOS tube P1, the drain end of the MOS tube P1 is connected with the gate end of the MOS tube P1, the drain end of the MOS tube P1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of the HVPMOS tube P1, the drain end of the resistor R1 and the resistor R1 are connected with the gate end of the MOS tube P1, the drain end of the MOS tube P1 is connected with the drain end of the resistor 1, the drain end of the MOS tube P1 is connected with the drain end of the MOS tube P1, the drain end of the MOS tube P1 is connected with the drain end of the MOS tube 1, the drain end of the MOS tube P1 is connected with the MOS tube 1, the drain end of the resistor 1 is connected with the drain end of the MOS tube P1, the MOS tube P1 is connected with the drain end of the MOS tube P1, the resistor 1, the drain end of the MOS tube P1 is connected with the MOS tube P1, the drain end of the MOS tube 1 is connected with the drain end of the resistor 1 is connected with the drain end of the MOS tube P1, the MOS tube P1 is connected with the drain end of the MOS tube 1, the MOS tube N1, the drain end of the MOS tube P1, the drain end of the MOS tube P1 is connected with the drain end of the MOS tube P1 and the drain end of the MOS tube P1, the MOS tube P1 is connected with the MOS tube 1, the MOS tube P1, the drain end of the MOS tube P1, the drain end of the MOS tube P1 is connected with the drain end of the MOS tube P1 and the drain end of the MOS tube P1 is connected with the MOS tube P1, the drain end of the MOS tube P1, the MOS tube P1 is connected with the MOS tube P1, the drain end of, the source end of MOS transistor N is connected with the source end of MOS transistor N, the source end of MOS transistor N is connected with the drain end of HVNMOS transistor N, the gate end of MOS transistor N is connected with the gate end of MOS transistor N, the drain end of MOS transistor N is connected with the drain end of MOS transistor P, the gate end of MOS transistor P is connected with resistor R and resistor R, the source end of MOS transistor P is connected with the source end of MOS transistor P, the drain end of MOS transistor P is connected with the drain end of MOS transistor N, the drain end of MOS transistor P is connected with the drain ends of MOS transistor P and MOS transistor P, the source ends of MOS transistor N and MOS transistor N are connected and the drain end of NMOS transistor N, the drain end of PMOS transistor P is connected with the drain end of MOS transistor N, the drain end of NMOS transistor N is connected with the drain end of MOS transistor N, the drain end of MOS transistor N is connected with MOS transistor N, the drain end of MOS transistor N, the drain end of MOS transistor N is connected with MOS transistor N, the drain end of MOS transistor N, the drain end of MOS transistor N is connected with MOS transistor N, the drain end of MOS transistor N, the MOS transistor N is connected with the drain end of MOS transistor N, the drain end of MOS transistor N, the drain end of the MOS transistor N, the drain end of the MOS transistor N, the drain end of the MOS transistor N, the drain end of the MOS transistor N, the drain end of the MOS transistor N, the, The source end of an HVNMOS transistor N7 is connected with the ground, one end of a resistor R3 is connected with VOUT +, the other end of the resistor R3 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the source ends of VOUT-and a MOS transistor N4, the gate end of the MOS transistor P11 is connected with the connection point of the resistor R3 and the resistor R4, the resistor R4 is connected with the source end of the MOS transistor N4, the gate end and the drain end of the MOS transistor P1 are connected, the gate end and the drain end of the MOS transistor N2 are connected, the gate end and the drain end of the MOS transistor N3 are connected, the gate end and the drain end of the MOS transistor N5 are connected, and the source ends of the MOS transistors P1, P2, P3, P4, P5, P6 and P7 are connected with the power supply.
2. The high voltage regulator circuit of claim 1, wherein the reference current flows through the resistor R1 and the resistor R2 to generate the reference voltage as the positive input terminal of the operational amplifier, and the output voltage is sampled by the resistor R3 and the resistor R4 and fed back to the negative input terminal of the operational amplifier.
3. The high voltage regulator circuit of claim 2, wherein when the load suddenly increases, the output voltage VOUT decreases, the sampling voltage decreases, the output voltage of the operational amplifier increases, the pull-down capability of the HVNMOS transistor N7 increases, and the GND _ fouling voltage decreases, thereby increasing VOUT.
4. The high voltage regulator circuit of claim 3, wherein as the VDD supply voltage increases, the GND _ FLOATING voltage increases, and the drain of the HVNMOS transistor N7 assumes the high voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111106498.6A CN113721698B (en) | 2021-09-22 | 2021-09-22 | High-voltage stabilizing circuit of relative power supply |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111106498.6A CN113721698B (en) | 2021-09-22 | 2021-09-22 | High-voltage stabilizing circuit of relative power supply |
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| CN113721698A CN113721698A (en) | 2021-11-30 |
| CN113721698B true CN113721698B (en) | 2022-05-31 |
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| CN116185118B (en) * | 2023-04-21 | 2023-07-07 | 苏州锴威特半导体股份有限公司 | Voltage generating circuit of relative power supply |
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| TW201019065A (en) * | 2008-11-11 | 2010-05-16 | Himax Analogic Inc | Shunt regulator |
| CN201562185U (en) * | 2009-11-13 | 2010-08-25 | 安徽华东光电技术研究所 | Circuit for regulating high-level voltage at low level |
| CN201926944U (en) * | 2010-12-17 | 2011-08-10 | 天津市盛丹电子技术发展有限公司 | Microampere precise constant flow source circuit |
| CN105814507A (en) * | 2013-10-04 | 2016-07-27 | 欧姆龙美国管理中心股份有限公司 | Method and apparatus for floating current source |
| CN207008452U (en) * | 2017-07-17 | 2018-02-13 | 无锡科技职业学院 | One kind suspends and follows voltage-stabilized power supply circuit device |
| CN110750128A (en) * | 2019-11-19 | 2020-02-04 | 电子科技大学 | Avalanche photodiode bias voltage regulating circuit based on negative pressure regulation |
-
2021
- 2021-09-22 CN CN202111106498.6A patent/CN113721698B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201019065A (en) * | 2008-11-11 | 2010-05-16 | Himax Analogic Inc | Shunt regulator |
| CN201562185U (en) * | 2009-11-13 | 2010-08-25 | 安徽华东光电技术研究所 | Circuit for regulating high-level voltage at low level |
| CN201926944U (en) * | 2010-12-17 | 2011-08-10 | 天津市盛丹电子技术发展有限公司 | Microampere precise constant flow source circuit |
| CN105814507A (en) * | 2013-10-04 | 2016-07-27 | 欧姆龙美国管理中心股份有限公司 | Method and apparatus for floating current source |
| CN207008452U (en) * | 2017-07-17 | 2018-02-13 | 无锡科技职业学院 | One kind suspends and follows voltage-stabilized power supply circuit device |
| CN110750128A (en) * | 2019-11-19 | 2020-02-04 | 电子科技大学 | Avalanche photodiode bias voltage regulating circuit based on negative pressure regulation |
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