CN113687705A - Method for supplying power in standby phase - Google Patents
Method for supplying power in standby phase Download PDFInfo
- Publication number
- CN113687705A CN113687705A CN202010425085.3A CN202010425085A CN113687705A CN 113687705 A CN113687705 A CN 113687705A CN 202010425085 A CN202010425085 A CN 202010425085A CN 113687705 A CN113687705 A CN 113687705A
- Authority
- CN
- China
- Prior art keywords
- power supply
- programmable logic
- power
- computer system
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000004044 response Effects 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 4
- 238000007726 management method Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
A method for providing power during standby phase is implemented by a computer system supporting the specification of open computing plan, and comprises the following steps: (A) a programmable logic unit setting a card signal related to an open operation card to a high level to enter a first mode; (B) when the computer system is in a first mode, a baseboard management control unit judges whether the standby power supply is insufficient; (C) when the standby power supply is judged to be insufficient, the substrate management control unit transmits a trigger signal to the programmable logic unit; (D) when the programmable logic unit receives the trigger signal, the programmable logic unit transmits a notification signal to a power supply unit to enter a second mode; and (E) when the computer system is in the second mode, the power supply unit provides a main power supply to the open computing card.
Description
Technical Field
The present invention relates to a method for providing power, and more particularly, to a method for providing power required by a computer system during a standby period.
Background
The voltage of standby power (standby power) provided by the power supply of the existing server is 12V, and the current is between 1.5A and 2A, so that the power supply capability of the standby power is enough for the server in standby state for the application of the past server products. However, under the circumstance that new interfaces (interfaces) and devices are continuously developed, the specifications of the power supply are gradually unable to meet the requirements of some system designs, and for the specification of Open Computer Project (OCP) V3.0, a current of 1.5A is required in the standby state, and in addition, about 0.5A is required for a fan and about 1A is required for a standby power supply required by the original system design (platform path control, substrate management controller, gigabit ethernet transceiver (PHY), etc.), and the total 12V standby power supply requirement is about 3A, so that the power supply of the existing server is unable to meet the requirements of the system design of OCP V3.0 in the standby state, and therefore, a solution is necessary.
Disclosure of Invention
The present invention provides a method for supplying power in the standby stage, which can satisfy the standby power requirement of the computer system supporting the open operation plan specification.
In order to solve the above technical problems, the method for providing power in the standby stage of the present invention is implemented by a computer system supporting the specification of an open operation plan, the computer system is in a first mode when entering a standby stage, and then enters a second mode with a higher power demand than the first mode, the computer system comprises a baseboard management control unit, an open operation card, a programmable logic unit electrically connecting the baseboard management control unit and the open operation card, and a power supply unit for supplying power to the baseboard management control unit, the open operation card and the programmable logic unit, the method for providing power in the standby stage comprises the following steps:
(A) setting a card signal related to the activation of the open operation card to a high level by the programmable logic unit to enter the first mode;
(B) when the computer system is in the first mode, card data related to the open operation card is obtained through the baseboard management control unit, and whether a standby power supply provided by the power supply unit is insufficient or not is judged according to the card data;
(C) when the baseboard management control unit judges that the standby power supply is insufficient, the baseboard management control unit transmits a trigger signal to the programmable logic unit;
(D) when the programmable logic unit receives the trigger signal, the programmable logic unit transmits a notification signal indicating that a main power supply is started to the power supply unit in response to the trigger signal so as to enter the second mode; and
(E) when the computer system is in the second mode, the power supply unit responds to the notification signal to provide the main power supply with power larger than the standby power supply so as to supply enough power to the open operation card.
Compared with the prior art, the invention informs the programmable logic unit to transmit the notification signal indicating to start the main power supply to the power supply unit when the baseboard management control unit determines that the standby power supply is insufficient, so that the power supply unit can provide the main power supply with electric power larger than the standby power supply to the open operation card in advance when the computer system is in the second mode, thereby meeting the requirement of the standby power supply required by the computer system supporting open operation planning specifications.
[ description of the drawings ]
Other features and effects of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings, in which:
FIG. 1 is a block diagram illustrating a computer system for implementing an embodiment of the method of the present invention for providing power during a standby phase;
FIG. 2 is a timing diagram illustrating the states of multiple signals and voltages in different modes;
FIG. 3 is a block diagram illustrating the state of signals when the computer system is in a first mode;
FIG. 4 is a flowchart illustrating a first mode entry procedure in an embodiment of the method of the present invention for providing power during a standby phase;
FIG. 5 is a block diagram illustrating the state of signals when the computer system is in a second mode;
FIG. 6 is a flowchart illustrating a standby power procedure in an embodiment of the method for providing power during a standby phase according to the present invention;
FIG. 7 is a block diagram illustrating the state of signals when the computer system is in a third mode; and
FIG. 8 is a flowchart illustrating a main power supply procedure in an embodiment of the method for providing power during the standby phase according to the present invention.
[ detailed description ] embodiments
Referring to FIG. 1, the embodiment of the method for providing power during the standby phase of the present invention is implemented by a computer system supporting the specification of an open computing plan. The computer system comprises a substrate management control unit 1, a platform path control unit 2, a central processing unit 3, a memory unit 4 electrically connected with the central processing unit 3, an open operation card 5 electrically connected with the substrate management control unit 1, a hot plug control unit 6 electrically connected with the open operation card 5, a programmable logic unit 7 electrically connected with the substrate management control unit 1, the platform path control unit 2, the open operation card 5 and the hot plug control unit 6, a fan 8, and a power supply unit 9 for supplying power to the substrate management control unit 1, the platform path control unit 2, the central processing unit 3, the memory unit 4, the open operation card 5, the hot plug control unit 6, the programmable logic unit 7 and the fan 8.
In this embodiment, the computer system is, for example, a server, the BMC unit 1 is, for example, a BMC (baseboard management controller), the platform path control unit 2 is, for example, a platform Path Controller (PCH), the CPU 3 is, for example, a CPU (central processing unit), the memory unit 4 is, for example, a dual in-line memory module (DIMM), the open computing card 5 is, for example, an OCP card supporting OCP v3.0, the Hot-plug control unit 6 is, for example, a Hot-plug controller (Hot Swap), the programmable logic unit 7 is, for example, a Complex Programmable Logic Device (CPLD), the power supply unit 9 includes an AND gate 91(AND gate) electrically connected to the programmable logic unit 7, a first switching unit 92 electrically connecting the Hot-plug control unit 6 AND the gate 91, a second switching unit 93, electrically connecting the fan 8 AND the programmable logic unit 7, A first transformer 94 electrically connected to the first switching unit 92, the hot plug control unit 6, the programmable logic unit 7, the platform path control unit 2 and the baseboard management control unit 1, a second transformer 95 electrically connected to the CPU 3, the memory unit 4 and the programmable logic unit 7, and a power supply 96 electrically connected to the AND gate 91, the first switching unit 92, the second switching unit 93, the first transformer 94 and the second transformer 95.
It should be noted that the computer system supporting the specification of the open computing plan is in a first mode when entering a standby phase, and then enters a second mode with a higher power demand than the first mode, and the computer system enters a third mode when entering a boot phase. In this embodiment, the first mode is an ID mode, and +3.3V _ EDGE can be provided to the opencard 5 when the computer system is in the ID mode, in which mode only a Field Replaceable Unit (FRU) (not shown) and a Scan Chain (Scan Chain) (not shown) of the opencard 5 are allowed to be accessed. The second mode is AUX power mode, and when the computer system is in AUX power mode, +3.3V _ EDGE and +12V _ EDGE can be provided to the open computing card 5. The third mode is a Main power mode, and the open computing card 5 can run with full capacity.
The following describes an embodiment of a method for supplying power in a standby phase according to the present invention implemented by the computer system with reference to the accompanying drawings, where the embodiment sequentially includes a first mode entering program running in a first mode of the standby phase, a standby power supply program running in a second mode of the standby phase, and a main power supply program running in a third mode of the power-on phase.
Referring to fig. 2, an operation timing chart of the embodiment is shown, which illustrates the states of the voltage supplied by the power supply 96, the signal output by the programmable logic unit 7, the signal output by the platform path control unit 2, and the signal output by the open computing card 5 when the computer system is in different modes.
Referring to fig. 3 and 4, the computer system implements a first mode entering procedure of the method for providing power in the standby phase according to the present invention. The first mode entering procedure describes how to enter the first mode and the states of the signal outputted by the programmable logic unit 7, the signal outputted by the platform path control unit 2, and the signal outputted by the open computing card 5 in the first mode, and includes the following steps.
In step 401, when the bmc 1 detects that the computer system includes the open computing card 5, the bmc 1 transmits a detection notification signal to the programmable logic unit 7.
In step 402, when the detection notification signal is received by the programmable logic unit 7, the card signal (i.e., an OCP _ V3_ EN signal) related to the activation of the open operation card 5 is set to high level by the programmable logic unit 7 and sent to the hot-plug control unit 6 to enter the first mode.
In step 403, the platform path control unit 2 sets a status signal (i.e., a signal S3_ N) indicating whether the computer system enters the boot stage to a low level and sends the status signal to the programmable logic unit 7 to indicate that the computer system does not enter the boot stage.
In step 404, after the programmable logic unit 7 receives the status signal, the programmable logic unit 7 maintains a master enable signal (i.e., a MAIN _ PWR _ EN signal) associated with the enabling of a master power source at a low level and transmits the master enable signal to the open operation card 5 in response to the status signal being at a low level.
In step 405, the programmable logic unit 7 also maintains a supply signal (i.e., a MAIN _ PWR _ ON signal) indicating whether to supply the MAIN power at a low level in response to the status signal and transmits the supply signal to the second transformer 95, so that the second transformer 95 does not output voltage to the cpu 3 and the memory unit 4, and thus does not supply the MAIN power to the cpu 3 and the memory unit 4.
In step 406, while the computer system is in the first mode, the programmable logic unit 7 also maintains an enable main power signal (i.e., an AUX _ PSU _ EN signal) associated with enabling the main power source at a low level and sends the low level to the and gate 91.
In step 407, the AND gate 91 AND the enabled main power signal with low level AND a switching signal (i.e., an interrupt signal) indicating whether the cover of the server is opened or not are anded to obtain AND transmit a notification signal (i.e., a PS _ ON signal, at which the PS _ ON signal after the AND operation is low) indicating that the main power is not enabled to the power supply 96 AND the first switching unit 92, thereby disabling the main power (i.e., a main voltage Vpsu =0V provided by the power supply 96, see the dotted line part of fig. 3), AND enabling the first switching unit 92 to select a standby voltage Vsb =12V provided by the power supply 96 to be transmitted to the first transformer 94 AND the hot-plug control unit 6 to output voltages to the substrate management control unit 1, the platform path control unit 2, the programmable logic unit 7, the hot-plug control unit 6, AND the first switching unit 92, The hot-plug control unit 6 and the open computing card 5, and further supply the standby power to the bmc unit 1, the platform path control unit 2, the programmable logic unit 7, the hot-plug control unit 6 and the open computing card 5. It is worth to be particularly noted that, when the cover plate of the server is opened, the opening/closing signal is at a low level; when the cover plate of the server is closed, the opening/closing signal is at a high level.
In step 408, when the computer system is in the first mode, the programmable logic unit 7 further maintains an auxiliary power-on signal (i.e., an AUX _ PWR _ EN signal) associated with the power-on of the standby power at a low level and transmits the auxiliary power-on signal to the open computing card 5 and the second switching unit 93, so that the second switching unit 93 selectively disables the power supply 96 and the fan 8, thereby not providing power to the fan 8.
In step 409, after the open operation card 5 receives the auxiliary power-up signal, the open operation card 5 maintains an operation signal (i.e., a NIC _ PWR _ GOOD signal) indicating whether the power supplied to the open operation card 5 is stable at a low level and transmits the operation signal to the programmable logic unit 7 to indicate that the power supplied to the open operation card 5 is unstable.
It should be noted that the execution sequence of the steps 404 to 409 disclosed in this embodiment is only an example, and in practice, the execution sequence of the steps 404 to 409 can be adjusted or performed simultaneously according to the requirement.
Referring to fig. 5 and 6, the computer system implements a standby power supply procedure of the method for providing power in the standby phase according to the present invention. The standby power procedure describes how the power supply 96 provides sufficient power to the open computing card 5, and includes the following steps.
In step 501, when the computer system is in the first mode, the bmc unit 1 obtains card data associated with the open computing card 5, and determines whether the standby power provided by the power supply unit 9 is insufficient according to the card data. When the bmc 1 determines that the standby power is insufficient, the process proceeds to step 502; when the board management control unit 1 determines that the standby power is sufficient, the flow ends. In the present embodiment, the card data is stored in the field replaceable unit of the open computing card 5 and includes a power value indicating the power required by the open computing card 5. The bmc unit 1 obtains the card data by reading the card data stored in the field replaceable unit, and determines whether the standby power is insufficient by determining whether the power value in the card data is greater than a predetermined power threshold. When the bmc 1 determines that the power value is greater than the power threshold, it means that the standby power provided by the power supply unit 9 is insufficient; when the bmc 1 determines that the power value is not greater than the power threshold, it means that the standby power provided by the power supply unit 9 is sufficient.
It should be noted that if the bmc 1 determines that the standby power is sufficient, the computer system performs a normal standby process, which is not known to those skilled in the art, and thus the details are omitted herein for brevity.
In step 502, the bmc 1 sends a trigger signal to the programmable logic unit 7.
In step 503, when the programmable logic unit 7 receives the trigger signal, the programmable logic unit 7 transmits a notification signal (i.e., the PS _ ON signal) indicating that the main power supply is enabled to the power supply 96 and the first switching unit 92 in response to the trigger signal, thereby enabling the main power supply, and making the first switching unit 92 select to pass the main voltage Vpsu =12V provided by the power supply 96 to the first transformer 94. In the present embodiment, the programmable logic unit 7 enters the second mode by setting the enable main power signal (i.e., the AUX _ PSU _ EN signal) associated with enabling the main power to high and sending it to the and gate 91.
In step 504, the AND gate 91 AND-operates the enabled main power signal at a high level with the ON/off signal to obtain AND transmit the notification signal indicating that the main power is enabled (at this time, the PS _ ON signal after AND operation is at a high level) to the power supply 96 AND the first switching unit 92.
In step 505, the power supply 96 provides power greater than the main power of the standby power in response to the notification signal to output the main voltage Vpsu =12V and transmits the main voltage Vpsu =12V to the hot-plug control unit 6 and the first transformer 94 via the selection of the first switching unit 92 to output voltages to the bmc unit 1, the stage path control unit 2, the programmable logic unit 7, the hot-plug control unit 6 and the open computing card 5, thereby supplying sufficient power to the open computing card 5.
In step 506, the programmable logic unit 7 sets the auxiliary enable signal (i.e., the AUX _ PWR _ EN signal) related to the enabling of the standby power to high level and transmits the auxiliary enable signal to the open computing card 5 and the second switching unit 93, so that the second switching unit 93 selects the main voltage Vsb =12V provided by the power supply 96 to be transmitted to the fan 8, thereby providing the power to the fan 8.
In step 507, after the open operation card 5 receives the auxiliary power-up signal, the open operation card 5 sets the operation signal (i.e., the NIC _ PWR _ GOOD signal) indicating whether the power supplied to the open operation card 5 is stable to a high level and transmits the operation signal to the programmable logic unit 7 to indicate that the power supplied to the open operation card 5 is stable.
In step 508, the programmable logic unit 7 also maintains the card signal (i.e., the OCP _ V3_ EN signal) associated with the activation of the open computing card 5 high and sends it to the hot-plug control unit 6 while the computer system is in the second mode.
In step 509, the platform path control unit 2 asserts the status signal (i.e., the S3_ N signal) indicating whether the computer system is entering the boot stage to the programmable logic unit 7 to indicate that the computer system is not entering the boot stage.
In step 510, after the programmable logic unit 7 receives the status signal, the programmable logic unit 7 maintains the MAIN enable signal (i.e., the MAIN _ PWR _ EN signal) related to the enabling of the MAIN power source at a low level and transmits the MAIN enable signal to the open operation card 5 in response to the status signal being at a low level.
In step 511, the programmable logic unit 7 also maintains the supply signal (i.e., the MAIN _ PWR _ ON signal) indicating whether to supply the MAIN power source at a low level in response to the status signal and transmits the supply signal to the second transformer 95, so that the second transformer 95 does not output voltage to the cpu 3 and the memory unit 4 (see the dotted line portion of fig. 5), thereby not supplying the MAIN power source to the cpu 3 and the memory unit 4.
It should be noted that the execution sequence of steps 506 to 511 disclosed in this embodiment is only an example, and in practice, the execution sequence of steps 506 to 511 may be adjusted or performed simultaneously according to the requirement.
Referring to fig. 7 and 8, the computer system implements the main power supply procedure of the method for providing power during the standby phase according to the present invention. The main power supply process illustrates how the power supply 96 provides the main power to the computer system for booting, and includes the following steps.
In step 801, when the platform path control unit 2 receives a power-on signal, the platform path control unit 2 sets the status signal (i.e., the S3_ N signal) indicating whether the computer system enters the power-on phase to high, and sends the status signal to the programmable logic unit 7 to indicate that the computer system enters the power-on phase. In this embodiment, the power-on signal can be generated by the user pressing a power switch of the computer system or obtained by remotely transmitting a power-on command. When the platform path control unit 2 receives the power-on signal, the computer system will leave the standby phase and enter the power-on phase, otherwise the computer system will stay in the standby phase.
In step 802, after the programmable logic unit 7 receives the status signal, the programmable logic unit 7 sets the MAIN enable signal (i.e., the MAIN _ PWR _ EN signal) related to the enabling of the MAIN power source to a high level in response to the status signal being at a high level and transmits the MAIN enable signal to the open computing card 5 to enter the third mode.
In step 803, the programmable logic unit 7 sets the supply signal (i.e., the MAIN _ PWR _ ON signal) indicating whether to supply the MAIN power to the second transformer 95 in response to the status signal, so that the second transformer 95 outputs a regulated output voltage to the cpu 3 and the memory unit 4 after the MAIN voltage Vpsu =12V provided by the power supply 96 is adjusted by the second transformer 95, thereby supplying the MAIN power to the cpu 3 and the memory unit 4.
In step 804, when the computer system is in the third mode, the programmable logic unit 7 maintains the active main power signal (i.e., the AUX _ PSU _ EN signal) associated with the active main power at a high level and transmits the signal to the and gate 91.
In step 805, the AND gate 91 AND-operates the enabled main power signal at a high level with the ON/off signal to obtain AND transmit the notification signal indicating the enabling of the main power (at this time, the PS _ ON signal after AND operation is at a high level) to the power supply 96 AND the first switching unit 92, thereby maintaining the enabling of the main power.
In step 806, the power supply 96 provides the main power to output the main voltage Vpsu =12V in response to the notification signal and transmits the main voltage Vpsu =12V to the hot-plug control unit 6 and the first transformer 94 via the selection of the first switching unit 92 to output voltages to the bmc unit 1, the stage path control unit 2, the programmable logic unit 7, the hot-plug control unit 6, and the open computing card 5.
In step 807, the programmable logic unit 7 also maintains the card signal (i.e., the OCP _ V3_ EN signal) associated with the activation of the open computing card 5 at a high level and transmits it to the hot-plug control unit 6 while the computer system is in the third mode.
In step 808, when the computer system is in the third mode, the programmable logic unit 7 further maintains the auxiliary power-on signal (i.e., the AUX _ PWR _ EN signal) related to the power-on of the standby power at a high level and transmits the auxiliary power-on signal to the open computing card 5 and the second switching unit 93, so that the second switching unit 93 selects the main voltage Vsb =12V provided by the power supply 96 to be transmitted to the fan 8, thereby maintaining the power supply to the fan 8.
In step 809, when the computer system is in the third mode, the open computing card 5 maintains the operation signal (i.e., the NIC _ PWR _ GOOD signal) indicating whether the power supplied to the open computing card 5 is stable at a high level and transmits the operation signal to the programmable logic unit 7 to indicate that the power supplied to the open computing card 5 is stable.
It should be noted that the execution sequence of the steps 803 to 809 disclosed in this embodiment is only an example, and in practice, the execution sequence of the steps 803 to 809 can be adjusted or performed simultaneously according to the requirement.
In summary, in the method for providing power during standby phase of the present invention, the bmc 1 notifies the programmable logic unit 7 to send the notification signal indicating to activate the main power to the power supply unit 9 when determining that the standby power is insufficient, so that the power supply unit 9 can provide the main power greater than the standby power to the open computing card 5 in advance when the computer system is in the second mode, although the main power of the power supply 96 can be enabled in advance when the computer system is in the second mode, however, the AUX _ PWR _ EN signal, the MAIN _ PWR _ ON signal, the NIC _ PWR _ GOOD signal, and the power-up sequence are all compliant with open-plan computing standards, can be applied to the specification of open operation plan and meet the requirement of standby power supply required by the computer system supporting the specification of open operation plan. In addition, the power supply 96 used in the present invention can be a power supply 96 commonly used in the industry, and there is no need to customize the power supply 96 using high standby power, so as to greatly reduce the cost of designing and applying safety regulations for the new power supply 96, and accelerate the design schedule of the system product, thereby achieving the purpose of the present invention.
However, the above description is only an example of the present invention, and the scope of the present invention should not be limited thereby, and all simple equivalent changes and modifications made according to the contents of the claims and the patent specification are still included in the scope covered by the present invention.
Claims (11)
1. A method for providing power supply in standby stage is implemented by a computer system supporting the specification of open operation plan, when the computer system enters a standby stage, the computer system is in a first mode firstly, then enters a second mode with higher power demand than the first mode, the computer system comprises a substrate management control unit, an open operation card, a programmable logic unit electrically connected with the substrate management control unit and the open operation card, and a power supply unit for supplying power to the substrate management control unit, the open operation card and the programmable logic unit, and is characterized in that the method for providing power supply in standby stage comprises the following steps:
(A) setting a card signal related to the activation of the open operation card to a high level by the programmable logic unit to enter the first mode;
(B) when the computer system is in the first mode, card data related to the open operation card is obtained through the baseboard management control unit, and whether a standby power supply provided by the power supply unit is insufficient or not is judged according to the card data;
(C) when the baseboard management control unit judges that the standby power supply is insufficient, the baseboard management control unit transmits a trigger signal to the programmable logic unit;
(D) when the programmable logic unit receives the trigger signal, the programmable logic unit transmits a notification signal indicating that a main power supply is started to the power supply unit in response to the trigger signal so as to enter the second mode; and
(E) when the computer system is in the second mode, the power supply unit responds to the notification signal to provide the main power supply with power larger than the standby power supply so as to supply enough power to the open operation card.
2. The method of claim 1, wherein in step (A), the card data includes a power value indicating power required by the open computing card, and the BMC determines whether the standby power is insufficient by determining whether the power value is greater than a predetermined power threshold.
3. The method of claim 1, wherein in step (A), the first mode is an ID mode, and in step (D), the second mode is an AUX power mode.
4. The method of claim 1, wherein in step (D), the programmable logic unit sends the notification signal indicating that the main power source is enabled to the power supply unit by setting an enable main power signal associated with enabling the main power source to a high level.
5. The method of claim 1, wherein the computer system further comprises a fan, and the power supply unit is further configured to supply power to the fan, and further comprising the following steps after the step (D):
(F) when the computer system is in the second mode, the programmable logic unit sets an auxiliary starting signal related to the starting of the standby power supply to a high level so as to supply power to the fan.
6. The method of claim 1, further comprising, before step (a), the steps of:
(G) when the baseboard management control unit detects that the computer system comprises the open operation card, the baseboard management control unit transmits a detection notification signal to the programmable logic unit;
wherein, in the step (a), when the programmable logic unit receives the detection notification signal, the card signal related to the activation of the open computing card is set to a high level by the programmable logic unit to enter the first mode.
7. The method of claim 1, further comprising, after step (D), the steps of:
(H) when the computer system is in the second mode, the open operation card sets an operation signal indicating whether the power supply supplied to the open operation card is stable to a high level to indicate that the power supply supplied to the open operation card is stable.
8. The method of claim 1, wherein the computer system further comprises a platform path control unit electrically connected to the programmable logic unit, the power supply unit further configured to supply power to the platform path control unit, and the method further comprises, after step (E), the steps of:
(I) when the computer system enters a boot stage, the platform path control unit sets a state signal indicating whether the computer system enters the boot stage to a high level and transmits the state signal to the programmable logic unit.
9. The method of claim 8, further comprising, after step (I), the steps of:
(J) after the programmable logic unit receives the status signal, the programmable logic unit responds to the status signal and sets a main starting signal related to the starting of the main power supply to be at a high level so as to enter the starting stage.
10. The method of claim 9 wherein in step (J), the programmable logic unit further asserts a supply signal indicating whether to supply the main power source high in response to the status signal to supply the main power source required for a boot process.
11. The method according to claim 1, wherein the computer system further comprises a CPU and a memory unit electrically connected to the CPU, wherein in step (E), the power supply unit does not supply the main power to the CPU and the memory unit when the computer system is in the second mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010425085.3A CN113687705B (en) | 2020-05-19 | 2020-05-19 | Method for providing power supply in standby stage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010425085.3A CN113687705B (en) | 2020-05-19 | 2020-05-19 | Method for providing power supply in standby stage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113687705A true CN113687705A (en) | 2021-11-23 |
| CN113687705B CN113687705B (en) | 2024-04-19 |
Family
ID=78575843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010425085.3A Active CN113687705B (en) | 2020-05-19 | 2020-05-19 | Method for providing power supply in standby stage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113687705B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097481A (en) * | 2006-06-30 | 2008-01-02 | 佛山市顺德区顺达电脑厂有限公司 | Electronic device having electric power management mechanism |
| CN102213991A (en) * | 2010-04-07 | 2011-10-12 | 英业达股份有限公司 | Standby voltage supply system of server |
| CN104731293A (en) * | 2013-12-23 | 2015-06-24 | 全汉企业股份有限公司 | Power supply device and power supply method thereof |
| CN106227318A (en) * | 2016-08-23 | 2016-12-14 | 浪潮电子信息产业股份有限公司 | A kind of Apparatus and system of control circuit conversion |
| CN106502362A (en) * | 2016-10-21 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of electric supply installation of four component server and its method for designing |
| US20180210524A1 (en) * | 2015-07-21 | 2018-07-26 | Hewlett Packard Enterprise Development Lp | Providing power to a server |
| US20180375421A1 (en) * | 2017-06-26 | 2018-12-27 | Bel Fuse (Macao Commercial Offshore) Limited | Power supply with auxiliary converter for extended input voltage range |
| US20190069437A1 (en) * | 2017-08-28 | 2019-02-28 | Facebook, Inc. | Apparatus, system, and method for enabling multiple storage-system configurations |
| WO2019156614A1 (en) * | 2018-02-06 | 2019-08-15 | Embedderment Ab | Alternative power sources for a modular power supply for starvation prevention in high-current computer power delivery systems |
| TWI675293B (en) * | 2018-11-02 | 2019-10-21 | 神雲科技股份有限公司 | A host boot detection method and its system |
| CN110389643A (en) * | 2018-04-16 | 2019-10-29 | 环达电脑(上海)有限公司 | Server and its far-end control method |
-
2020
- 2020-05-19 CN CN202010425085.3A patent/CN113687705B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097481A (en) * | 2006-06-30 | 2008-01-02 | 佛山市顺德区顺达电脑厂有限公司 | Electronic device having electric power management mechanism |
| CN102213991A (en) * | 2010-04-07 | 2011-10-12 | 英业达股份有限公司 | Standby voltage supply system of server |
| CN104731293A (en) * | 2013-12-23 | 2015-06-24 | 全汉企业股份有限公司 | Power supply device and power supply method thereof |
| US20180210524A1 (en) * | 2015-07-21 | 2018-07-26 | Hewlett Packard Enterprise Development Lp | Providing power to a server |
| CN106227318A (en) * | 2016-08-23 | 2016-12-14 | 浪潮电子信息产业股份有限公司 | A kind of Apparatus and system of control circuit conversion |
| CN106502362A (en) * | 2016-10-21 | 2017-03-15 | 郑州云海信息技术有限公司 | A kind of electric supply installation of four component server and its method for designing |
| US20180375421A1 (en) * | 2017-06-26 | 2018-12-27 | Bel Fuse (Macao Commercial Offshore) Limited | Power supply with auxiliary converter for extended input voltage range |
| US20190069437A1 (en) * | 2017-08-28 | 2019-02-28 | Facebook, Inc. | Apparatus, system, and method for enabling multiple storage-system configurations |
| WO2019156614A1 (en) * | 2018-02-06 | 2019-08-15 | Embedderment Ab | Alternative power sources for a modular power supply for starvation prevention in high-current computer power delivery systems |
| CN110389643A (en) * | 2018-04-16 | 2019-10-29 | 环达电脑(上海)有限公司 | Server and its far-end control method |
| TWI675293B (en) * | 2018-11-02 | 2019-10-21 | 神雲科技股份有限公司 | A host boot detection method and its system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113687705B (en) | 2024-04-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101623756B1 (en) | A method for interrupting power supply in an apparatus for interrupting power supply utilizing the voltage supplied to the system memory | |
| US7539808B2 (en) | Information processing apparatus, information processing system, and program | |
| US6062480A (en) | Hot docking system and methods for detecting and managing hot docking of bus cards | |
| US7831860B2 (en) | System and method for testing redundancy and hot-swapping capability of a redundant power supply | |
| CN101930274B (en) | Information processing apparatus and method of controlling the same | |
| US20020057019A1 (en) | Automatic power supply selector for a ACPI-compliant PCI devices | |
| KR101739501B1 (en) | A power saving method of a computer system | |
| JP4173942B2 (en) | Backup power supply module, backup power supply device and computer | |
| TWI726550B (en) | Method of providing power in standby phase | |
| KR101692538B1 (en) | An apparatus and method for interrupting power supply utilizing the GPIO port | |
| US6098143A (en) | Remote server management device | |
| US20050030680A1 (en) | Electric outlet for stanby power interruption and power saving, control method thereof, and power saving system | |
| US6993670B2 (en) | Method of configuring a computer system capable of being woken up on LAN | |
| US10678739B1 (en) | Electronic system, host device and control method | |
| CN106249832B (en) | Touch control all-in-one machine and power supply control method thereof | |
| KR101741225B1 (en) | A power saving apparatus and method of a computer system using SIO | |
| US6128682A (en) | Method and apparatus for bus isolation | |
| CN118170598A (en) | GPU card hot plug detection processing method, device, equipment and storage medium | |
| US7523336B2 (en) | Controlled power sequencing for independent logic circuits that transfers voltage at a first level for a predetermined period of time and subsequently at a highest level | |
| CN113687705A (en) | Method for supplying power in standby phase | |
| EP0724208A1 (en) | Control of power provisioning system in a computer | |
| CN116700461A (en) | Method and system for starting up computer by utilizing keyboard | |
| KR102244643B1 (en) | Switching mode power supply built-in standby power cut-off apparatus and method | |
| US10921875B2 (en) | Computer system, operational method for a microcontroller, and computer program product | |
| CN219831809U (en) | Network security industrial control main board with network Bypass |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |